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1/*
2 * Contains the definition of registers common to all PowerPC variants.
3 * If a register definition has been changed in a different PowerPC
4 * variant, we will case it in #ifndef XXX ... #endif, and have the
5 * number used in the Programming Environments Manual For 32-Bit
6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
7 */
8
9#ifndef _ASM_POWERPC_REG_H
10#define _ASM_POWERPC_REG_H
11#ifdef __KERNEL__
12
13#include <linux/stringify.h>
14#include <asm/cputable.h>
15
16/* Pickup Book E specific registers. */
17#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
18#include <asm/reg_booke.h>
19#endif /* CONFIG_BOOKE || CONFIG_40x */
20
21#ifdef CONFIG_FSL_EMB_PERFMON
22#include <asm/reg_fsl_emb.h>
23#endif
24
25#ifdef CONFIG_PPC_8xx
26#include <asm/reg_8xx.h>
27#endif /* CONFIG_PPC_8xx */
28
29#define MSR_SF_LG 63 /* Enable 64 bit mode */
30#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
31#define MSR_HV_LG 60 /* Hypervisor state */
32#define MSR_TS_T_LG 34 /* Trans Mem state: Transactional */
33#define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */
34#define MSR_TS_LG 33 /* Trans Mem state (2 bits) */
35#define MSR_TM_LG 32 /* Trans Mem Available */
36#define MSR_VEC_LG 25 /* Enable AltiVec */
37#define MSR_VSX_LG 23 /* Enable VSX */
38#define MSR_POW_LG 18 /* Enable Power Management */
39#define MSR_WE_LG 18 /* Wait State Enable */
40#define MSR_TGPR_LG 17 /* TLB Update registers in use */
41#define MSR_CE_LG 17 /* Critical Interrupt Enable */
42#define MSR_ILE_LG 16 /* Interrupt Little Endian */
43#define MSR_EE_LG 15 /* External Interrupt Enable */
44#define MSR_PR_LG 14 /* Problem State / Privilege Level */
45#define MSR_FP_LG 13 /* Floating Point enable */
46#define MSR_ME_LG 12 /* Machine Check Enable */
47#define MSR_FE0_LG 11 /* Floating Exception mode 0 */
48#define MSR_SE_LG 10 /* Single Step */
49#define MSR_BE_LG 9 /* Branch Trace */
50#define MSR_DE_LG 9 /* Debug Exception Enable */
51#define MSR_FE1_LG 8 /* Floating Exception mode 1 */
52#define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
53#define MSR_IR_LG 5 /* Instruction Relocate */
54#define MSR_DR_LG 4 /* Data Relocate */
55#define MSR_PE_LG 3 /* Protection Enable */
56#define MSR_PX_LG 2 /* Protection Exclusive Mode */
57#define MSR_PMM_LG 2 /* Performance monitor */
58#define MSR_RI_LG 1 /* Recoverable Exception */
59#define MSR_LE_LG 0 /* Little Endian */
60
61#ifdef __ASSEMBLY__
62#define __MASK(X) (1<<(X))
63#else
64#define __MASK(X) (1UL<<(X))
65#endif
66
67#ifdef CONFIG_PPC64
68#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
69#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
70#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
71#else
72/* so tests for these bits fail on 32-bit */
73#define MSR_SF 0
74#define MSR_ISF 0
75#define MSR_HV 0
76#endif
77
78/*
79 * To be used in shared book E/book S, this avoids needing to worry about
80 * book S/book E in shared code
81 */
82#ifndef MSR_SPE
83#define MSR_SPE 0
84#endif
85
86#define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
87#define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */
88#define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
89#define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */
90#define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */
91#define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */
92#define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */
93#define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */
94#define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */
95#define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */
96#define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */
97#define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
98#define MSR_SE __MASK(MSR_SE_LG) /* Single Step */
99#define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */
100#define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */
101#define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */
102#define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
103#define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */
104#define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */
105#define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */
106#define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */
107#ifndef MSR_PMM
108#define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */
109#endif
110#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
111#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
112
113#define MSR_TM __MASK(MSR_TM_LG) /* Transactional Mem Available */
114#define MSR_TS_N 0 /* Non-transactional */
115#define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */
116#define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */
117#define MSR_TS_MASK (MSR_TS_T | MSR_TS_S) /* Transaction State bits */
118#define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */
119#define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK) /* Reserved */
120#define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T)
121#define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S)
122
123#if defined(CONFIG_PPC_BOOK3S_64)
124#define MSR_64BIT MSR_SF
125
126/* Server variant */
127#define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV)
128#ifdef __BIG_ENDIAN__
129#define MSR_ __MSR
130#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV)
131#else
132#define MSR_ (__MSR | MSR_LE)
133#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV | MSR_LE)
134#endif
135#define MSR_KERNEL (MSR_ | MSR_64BIT)
136#define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
137#define MSR_USER64 (MSR_USER32 | MSR_64BIT)
138#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_8xx)
139/* Default MSR for kernel mode. */
140#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
141#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
142#endif
143
144#ifndef MSR_64BIT
145#define MSR_64BIT 0
146#endif
147
148/* Power Management - Processor Stop Status and Control Register Fields */
149#define PSSCR_RL_MASK 0x0000000F /* Requested Level */
150#define PSSCR_MTL_MASK 0x000000F0 /* Maximum Transition Level */
151#define PSSCR_TR_MASK 0x00000300 /* Transition State */
152#define PSSCR_PSLL_MASK 0x000F0000 /* Power-Saving Level Limit */
153#define PSSCR_EC 0x00100000 /* Exit Criterion */
154#define PSSCR_ESL 0x00200000 /* Enable State Loss */
155#define PSSCR_SD 0x00400000 /* Status Disable */
156#define PSSCR_PLS 0xf000000000000000 /* Power-saving Level Status */
157#define PSSCR_GUEST_VIS 0xf0000000000003ff /* Guest-visible PSSCR fields */
158
159/* Floating Point Status and Control Register (FPSCR) Fields */
160#define FPSCR_FX 0x80000000 /* FPU exception summary */
161#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
162#define FPSCR_VX 0x20000000 /* Invalid operation summary */
163#define FPSCR_OX 0x10000000 /* Overflow exception summary */
164#define FPSCR_UX 0x08000000 /* Underflow exception summary */
165#define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */
166#define FPSCR_XX 0x02000000 /* Inexact exception summary */
167#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
168#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
169#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
170#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
171#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
172#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
173#define FPSCR_FR 0x00040000 /* Fraction rounded */
174#define FPSCR_FI 0x00020000 /* Fraction inexact */
175#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
176#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
177#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
178#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
179#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
180#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
181#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
182#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
183#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
184#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
185#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
186#define FPSCR_RN 0x00000003 /* FPU rounding control */
187
188/* Bit definitions for SPEFSCR. */
189#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
190#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
191#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
192#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
193#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
194#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
195#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
196#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
197#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
198#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
199#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
200#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
201#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
202#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
203#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
204#define SPEFSCR_OV 0x00004000 /* Integer overflow */
205#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
206#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
207#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
208#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
209#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
210#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
211#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
212#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
213#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
214#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
215#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
216#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */
217
218/* Special Purpose Registers (SPRNs)*/
219
220#ifdef CONFIG_40x
221#define SPRN_PID 0x3B1 /* Process ID */
222#else
223#define SPRN_PID 0x030 /* Process ID */
224#ifdef CONFIG_BOOKE
225#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
226#endif
227#endif
228
229#define SPRN_CTR 0x009 /* Count Register */
230#define SPRN_DSCR 0x11
231#define SPRN_CFAR 0x1c /* Come From Address Register */
232#define SPRN_AMR 0x1d /* Authority Mask Register */
233#define SPRN_UAMOR 0x9d /* User Authority Mask Override Register */
234#define SPRN_AMOR 0x15d /* Authority Mask Override Register */
235#define SPRN_ACOP 0x1F /* Available Coprocessor Register */
236#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
237#define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */
238#define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */
239#define TEXASR_FS __MASK(63-36) /* TEXASR Failure Summary */
240#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
241#define SPRN_TIDR 144 /* Thread ID register */
242#define SPRN_CTRLF 0x088
243#define SPRN_CTRLT 0x098
244#define CTRL_CT 0xc0000000 /* current thread */
245#define CTRL_CT0 0x80000000 /* thread 0 */
246#define CTRL_CT1 0x40000000 /* thread 1 */
247#define CTRL_TE 0x00c00000 /* thread enable */
248#define CTRL_RUNLATCH 0x1
249#define SPRN_DAWR 0xB4
250#define SPRN_RPR 0xBA /* Relative Priority Register */
251#define SPRN_CIABR 0xBB
252#define CIABR_PRIV 0x3
253#define CIABR_PRIV_USER 1
254#define CIABR_PRIV_SUPER 2
255#define CIABR_PRIV_HYPER 3
256#define SPRN_DAWRX 0xBC
257#define DAWRX_USER __MASK(0)
258#define DAWRX_KERNEL __MASK(1)
259#define DAWRX_HYP __MASK(2)
260#define DAWRX_WTI __MASK(3)
261#define DAWRX_WT __MASK(4)
262#define DAWRX_DR __MASK(5)
263#define DAWRX_DW __MASK(6)
264#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
265#define SPRN_DABR2 0x13D /* e300 */
266#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */
267#define DABRX_USER __MASK(0)
268#define DABRX_KERNEL __MASK(1)
269#define DABRX_HYP __MASK(2)
270#define DABRX_BTI __MASK(3)
271#define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER)
272#define SPRN_DAR 0x013 /* Data Address Register */
273#define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */
274#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
275#define DSISR_BAD_DIRECT_ST 0x80000000 /* Obsolete: Direct store error */
276#define DSISR_NOHPTE 0x40000000 /* no translation found */
277#define DSISR_ATTR_CONFLICT 0x20000000 /* P9: Process vs. Partition attr */
278#define DSISR_NOEXEC_OR_G 0x10000000 /* Alias of SRR1 bit, see below */
279#define DSISR_PROTFAULT 0x08000000 /* protection fault */
280#define DSISR_BADACCESS 0x04000000 /* bad access to CI or G */
281#define DSISR_ISSTORE 0x02000000 /* access was a store */
282#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
283#define DSISR_NOSEGMENT 0x00200000 /* STAB miss (unsupported) */
284#define DSISR_KEYFAULT 0x00200000 /* Storage Key fault */
285#define DSISR_BAD_EXT_CTRL 0x00100000 /* Obsolete: External ctrl error */
286#define DSISR_UNSUPP_MMU 0x00080000 /* P9: Unsupported MMU config */
287#define DSISR_SET_RC 0x00040000 /* P9: Failed setting of R/C bits */
288#define DSISR_PRTABLE_FAULT 0x00020000 /* P9: Fault on process table */
289#define DSISR_ICSWX_NO_CT 0x00004000 /* P7: icswx unavailable cp type */
290#define DSISR_BAD_COPYPASTE 0x00000008 /* P9: Copy/Paste on wrong memtype */
291#define DSISR_BAD_AMO 0x00000004 /* P9: Incorrect AMO opcode */
292#define DSISR_BAD_CI_LDST 0x00000002 /* P8: Bad HV CI load/store */
293
294/*
295 * DSISR_NOEXEC_OR_G doesn't actually exist. This bit is always
296 * 0 on DSIs. However, on ISIs, the corresponding bit in SRR1
297 * indicates an attempt at executing from a no-execute PTE
298 * or segment or from a guarded page.
299 *
300 * We add a definition here for completeness as we alias
301 * DSISR and SRR1 in do_page_fault.
302 */
303
304/*
305 * DSISR bits that are treated as a fault. Any bit set
306 * here will skip hash_page, and cause do_page_fault to
307 * trigger a SIGBUS or SIGSEGV:
308 */
309#define DSISR_BAD_FAULT_32S (DSISR_BAD_DIRECT_ST | \
310 DSISR_BADACCESS | \
311 DSISR_BAD_EXT_CTRL)
312#define DSISR_BAD_FAULT_64S (DSISR_BAD_FAULT_32S | \
313 DSISR_ATTR_CONFLICT | \
314 DSISR_KEYFAULT | \
315 DSISR_UNSUPP_MMU | \
316 DSISR_PRTABLE_FAULT | \
317 DSISR_ICSWX_NO_CT | \
318 DSISR_BAD_COPYPASTE | \
319 DSISR_BAD_AMO | \
320 DSISR_BAD_CI_LDST)
321/*
322 * These bits are equivalent in SRR1 and DSISR for 0x400
323 * instruction access interrupts on Book3S
324 */
325#define DSISR_SRR1_MATCH_32S (DSISR_NOHPTE | \
326 DSISR_NOEXEC_OR_G | \
327 DSISR_PROTFAULT)
328#define DSISR_SRR1_MATCH_64S (DSISR_SRR1_MATCH_32S | \
329 DSISR_KEYFAULT | \
330 DSISR_UNSUPP_MMU | \
331 DSISR_SET_RC | \
332 DSISR_PRTABLE_FAULT)
333
334#define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */
335#define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
336#define SPRN_CIR 0x11B /* Chip Information Register (hyper, R/0) */
337#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
338#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
339#define SPRN_TBU40 0x11E /* Timebase upper 40 bits (hyper, R/W) */
340#define SPRN_SPURR 0x134 /* Scaled PURR */
341#define SPRN_HSPRG0 0x130 /* Hypervisor Scratch 0 */
342#define SPRN_HSPRG1 0x131 /* Hypervisor Scratch 1 */
343#define SPRN_HDSISR 0x132
344#define SPRN_HDAR 0x133
345#define SPRN_HDEC 0x136 /* Hypervisor Decrementer */
346#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
347#define SPRN_RMOR 0x138 /* Real mode offset register */
348#define SPRN_HRMOR 0x139 /* Real mode offset register */
349#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
350#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
351#define SPRN_ASDR 0x330 /* Access segment descriptor register */
352#define SPRN_IC 0x350 /* Virtual Instruction Count */
353#define SPRN_VTB 0x351 /* Virtual Time Base */
354#define SPRN_LDBAR 0x352 /* LD Base Address Register */
355#define SPRN_PMICR 0x354 /* Power Management Idle Control Reg */
356#define SPRN_PMSR 0x355 /* Power Management Status Reg */
357#define SPRN_PMMAR 0x356 /* Power Management Memory Activity Register */
358#define SPRN_PSSCR 0x357 /* Processor Stop Status and Control Register (ISA 3.0) */
359#define SPRN_PSSCR_PR 0x337 /* PSSCR ISA 3.0, privileged mode access */
360#define SPRN_PMCR 0x374 /* Power Management Control Register */
361
362/* HFSCR and FSCR bit numbers are the same */
363#define FSCR_SCV_LG 12 /* Enable System Call Vectored */
364#define FSCR_MSGP_LG 10 /* Enable MSGP */
365#define FSCR_TAR_LG 8 /* Enable Target Address Register */
366#define FSCR_EBB_LG 7 /* Enable Event Based Branching */
367#define FSCR_TM_LG 5 /* Enable Transactional Memory */
368#define FSCR_BHRB_LG 4 /* Enable Branch History Rolling Buffer*/
369#define FSCR_PM_LG 3 /* Enable prob/priv access to PMU SPRs */
370#define FSCR_DSCR_LG 2 /* Enable Data Stream Control Register */
371#define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */
372#define FSCR_FP_LG 0 /* Enable Floating Point */
373#define SPRN_FSCR 0x099 /* Facility Status & Control Register */
374#define FSCR_SCV __MASK(FSCR_SCV_LG)
375#define FSCR_TAR __MASK(FSCR_TAR_LG)
376#define FSCR_EBB __MASK(FSCR_EBB_LG)
377#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
378#define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */
379#define HFSCR_MSGP __MASK(FSCR_MSGP_LG)
380#define HFSCR_TAR __MASK(FSCR_TAR_LG)
381#define HFSCR_EBB __MASK(FSCR_EBB_LG)
382#define HFSCR_TM __MASK(FSCR_TM_LG)
383#define HFSCR_PM __MASK(FSCR_PM_LG)
384#define HFSCR_BHRB __MASK(FSCR_BHRB_LG)
385#define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
386#define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
387#define HFSCR_FP __MASK(FSCR_FP_LG)
388#define SPRN_TAR 0x32f /* Target Address Register */
389#define SPRN_LPCR 0x13E /* LPAR Control Register */
390#define LPCR_VPM0 ASM_CONST(0x8000000000000000)
391#define LPCR_VPM1 ASM_CONST(0x4000000000000000)
392#define LPCR_ISL ASM_CONST(0x2000000000000000)
393#define LPCR_VC_SH 61
394#define LPCR_DPFD_SH 52
395#define LPCR_DPFD (ASM_CONST(7) << LPCR_DPFD_SH)
396#define LPCR_VRMASD_SH 47
397#define LPCR_VRMASD (ASM_CONST(0x1f) << LPCR_VRMASD_SH)
398#define LPCR_VRMA_L ASM_CONST(0x0008000000000000)
399#define LPCR_VRMA_LP0 ASM_CONST(0x0001000000000000)
400#define LPCR_VRMA_LP1 ASM_CONST(0x0000800000000000)
401#define LPCR_RMLS 0x1C000000 /* Implementation dependent RMO limit sel */
402#define LPCR_RMLS_SH 26
403#define LPCR_ILE ASM_CONST(0x0000000002000000) /* !HV irqs set MSR:LE */
404#define LPCR_AIL ASM_CONST(0x0000000001800000) /* Alternate interrupt location */
405#define LPCR_AIL_0 ASM_CONST(0x0000000000000000) /* MMU off exception offset 0x0 */
406#define LPCR_AIL_3 ASM_CONST(0x0000000001800000) /* MMU on exception offset 0xc00...4xxx */
407#define LPCR_ONL ASM_CONST(0x0000000000040000) /* online - PURR/SPURR count */
408#define LPCR_LD ASM_CONST(0x0000000000020000) /* large decremeter */
409#define LPCR_PECE ASM_CONST(0x000000000001f000) /* powersave exit cause enable */
410#define LPCR_PECEDP ASM_CONST(0x0000000000010000) /* directed priv dbells cause exit */
411#define LPCR_PECEDH ASM_CONST(0x0000000000008000) /* directed hyp dbells cause exit */
412#define LPCR_PECE0 ASM_CONST(0x0000000000004000) /* ext. exceptions can cause exit */
413#define LPCR_PECE1 ASM_CONST(0x0000000000002000) /* decrementer can cause exit */
414#define LPCR_PECE2 ASM_CONST(0x0000000000001000) /* machine check etc can cause exit */
415#define LPCR_PECE_HVEE ASM_CONST(0x0000400000000000) /* P9 Wakeup on HV interrupts */
416#define LPCR_MER ASM_CONST(0x0000000000000800) /* Mediated External Exception */
417#define LPCR_MER_SH 11
418#define LPCR_GTSE ASM_CONST(0x0000000000000400) /* Guest Translation Shootdown Enable */
419#define LPCR_TC ASM_CONST(0x0000000000000200) /* Translation control */
420#define LPCR_HEIC ASM_CONST(0x0000000000000010) /* Hypervisor External Interrupt Control */
421#define LPCR_LPES 0x0000000c
422#define LPCR_LPES0 ASM_CONST(0x0000000000000008) /* LPAR Env selector 0 */
423#define LPCR_LPES1 ASM_CONST(0x0000000000000004) /* LPAR Env selector 1 */
424#define LPCR_LPES_SH 2
425#define LPCR_RMI ASM_CONST(0x0000000000000002) /* real mode is cache inhibit */
426#define LPCR_HVICE ASM_CONST(0x0000000000000002) /* P9: HV interrupt enable */
427#define LPCR_HDICE ASM_CONST(0x0000000000000001) /* Hyp Decr enable (HV,PR,EE) */
428#define LPCR_UPRT ASM_CONST(0x0000000000400000) /* Use Process Table (ISA 3) */
429#define LPCR_HR ASM_CONST(0x0000000000100000)
430#ifndef SPRN_LPID
431#define SPRN_LPID 0x13F /* Logical Partition Identifier */
432#endif
433#define LPID_RSVD 0x3ff /* Reserved LPID for partn switching */
434#define SPRN_HMER 0x150 /* Hardware m? error recovery */
435#define SPRN_HMEER 0x151 /* Hardware m? enable error recovery */
436#define SPRN_PCR 0x152 /* Processor compatibility register */
437#define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */
438#define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */
439#define PCR_TM_DIS (1ul << (63-2)) /* Trans. memory disable (POWER8) */
440/*
441 * These bits are used in the function kvmppc_set_arch_compat() to specify and
442 * determine both the compatibility level which we want to emulate and the
443 * compatibility level which the host is capable of emulating.
444 */
445#define PCR_ARCH_207 0x8 /* Architecture 2.07 */
446#define PCR_ARCH_206 0x4 /* Architecture 2.06 */
447#define PCR_ARCH_205 0x2 /* Architecture 2.05 */
448#define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */
449#define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */
450#define SPRN_TLBVPNR 0x155 /* P7 TLB control register */
451#define SPRN_TLBRPNR 0x156 /* P7 TLB control register */
452#define SPRN_TLBLPIDR 0x157 /* P7 TLB control register */
453#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
454#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
455#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
456#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
457#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
458#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
459#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
460#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
461#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
462#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
463#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
464#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
465#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
466#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
467#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
468#define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */
469#define SPRN_PPR 0x380 /* SMT Thread status Register */
470#define SPRN_TSCR 0x399 /* Thread Switch Control Register */
471
472#define SPRN_DEC 0x016 /* Decrement Register */
473#define SPRN_DER 0x095 /* Debug Enable Register */
474#define DER_RSTE 0x40000000 /* Reset Interrupt */
475#define DER_CHSTPE 0x20000000 /* Check Stop */
476#define DER_MCIE 0x10000000 /* Machine Check Interrupt */
477#define DER_EXTIE 0x02000000 /* External Interrupt */
478#define DER_ALIE 0x01000000 /* Alignment Interrupt */
479#define DER_PRIE 0x00800000 /* Program Interrupt */
480#define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */
481#define DER_DECIE 0x00200000 /* Decrementer Interrupt */
482#define DER_SYSIE 0x00040000 /* System Call Interrupt */
483#define DER_TRE 0x00020000 /* Trace Interrupt */
484#define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */
485#define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */
486#define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */
487#define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */
488#define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */
489#define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */
490#define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */
491#define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */
492#define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */
493#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
494#define SPRN_DHDES 0x0B1 /* Directed Hyp. Doorbell Exc. State */
495#define SPRN_DPDES 0x0B0 /* Directed Priv. Doorbell Exc. State */
496#define SPRN_EAR 0x11A /* External Address Register */
497#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
498#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Register */
499#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
500#define HID0_HDICE_SH (63 - 23) /* 970 HDEC interrupt enable */
501#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
502#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
503#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
504#define HID0_SBCLK (1<<27)
505#define HID0_EICE (1<<26)
506#define HID0_TBEN (1<<26) /* Timebase enable - 745x */
507#define HID0_ECLK (1<<25)
508#define HID0_PAR (1<<24)
509#define HID0_STEN (1<<24) /* Software table search enable - 745x */
510#define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */
511#define HID0_DOZE (1<<23)
512#define HID0_NAP (1<<22)
513#define HID0_SLEEP (1<<21)
514#define HID0_DPM (1<<20)
515#define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */
516#define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */
517#define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/
518#define HID0_ICE (1<<15) /* Instruction Cache Enable */
519#define HID0_DCE (1<<14) /* Data Cache Enable */
520#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
521#define HID0_DLOCK (1<<12) /* Data Cache Lock */
522#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
523#define HID0_DCI (1<<10) /* Data Cache Invalidate */
524#define HID0_SPD (1<<9) /* Speculative disable */
525#define HID0_DAPUEN (1<<8) /* Debug APU enable */
526#define HID0_SGE (1<<7) /* Store Gathering Enable */
527#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
528#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
529#define HID0_LRSTK (1<<4) /* Link register stack - 745x */
530#define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */
531#define HID0_ABE (1<<3) /* Address Broadcast Enable */
532#define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */
533#define HID0_BHTE (1<<2) /* Branch History Table Enable */
534#define HID0_BTCD (1<<1) /* Branch target cache disable */
535#define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */
536#define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */
537/* POWER8 HID0 bits */
538#define HID0_POWER8_4LPARMODE __MASK(61)
539#define HID0_POWER8_2LPARMODE __MASK(57)
540#define HID0_POWER8_1TO2LPAR __MASK(52)
541#define HID0_POWER8_1TO4LPAR __MASK(51)
542#define HID0_POWER8_DYNLPARDIS __MASK(48)
543
544/* POWER9 HID0 bits */
545#define HID0_POWER9_RADIX __MASK(63 - 8)
546
547#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
548#ifdef CONFIG_6xx
549#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */
550#define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */
551#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */
552#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */
553#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */
554#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */
555#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */
556#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */
557#define HID1_PS (1<<16) /* 750FX PLL selection */
558#endif
559#define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */
560#define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */
561#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
562#define SPRN_IABR2 0x3FA /* 83xx */
563#define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */
564#define SPRN_IAMR 0x03D /* Instr. Authority Mask Reg */
565#define SPRN_HID4 0x3F4 /* 970 HID4 */
566#define HID4_LPES0 (1ul << (63-0)) /* LPAR env. sel. bit 0 */
567#define HID4_RMLS2_SH (63 - 2) /* Real mode limit bottom 2 bits */
568#define HID4_LPID5_SH (63 - 6) /* partition ID bottom 4 bits */
569#define HID4_RMOR_SH (63 - 22) /* real mode offset (16 bits) */
570#define HID4_RMOR (0xFFFFul << HID4_RMOR_SH)
571#define HID4_LPES1 (1 << (63-57)) /* LPAR env. sel. bit 1 */
572#define HID4_RMLS0_SH (63 - 58) /* Real mode limit top bit */
573#define HID4_LPID1_SH 0 /* partition ID top 2 bits */
574#define SPRN_HID4_GEKKO 0x3F3 /* Gekko HID4 */
575#define SPRN_HID5 0x3F6 /* 970 HID5 */
576#define SPRN_HID6 0x3F9 /* BE HID 6 */
577#define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */
578#define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */
579#define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */
580#define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
581#define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
582#define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */
583#define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */
584#define SPRN_TSC 0x3FD /* Thread switch control on others */
585#define SPRN_TST 0x3FC /* Thread switch timeout on others */
586#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
587#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
588#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
589#endif
590#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
591#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
592#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
593#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
594#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
595#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
596#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
597#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
598#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
599#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
600#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
601#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
602#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
603#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
604#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
605#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
606#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
607#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
608#ifndef SPRN_ICTRL
609#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */
610#endif
611#define ICTRL_EICE 0x08000000 /* enable icache parity errs */
612#define ICTRL_EDC 0x04000000 /* enable dcache parity errs */
613#define ICTRL_EICP 0x00000100 /* enable icache par. check */
614#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
615#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
616#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Register */
617#define SPRN_L2CR2 0x3f8
618#define L2CR_L2E 0x80000000 /* L2 enable */
619#define L2CR_L2PE 0x40000000 /* L2 parity enable */
620#define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */
621#define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */
622#define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */
623#define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */
624#define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */
625#define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */
626#define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */
627#define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */
628#define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */
629#define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */
630#define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */
631#define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */
632#define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */
633#define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */
634#define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */
635#define L2CR_L2DO 0x00400000 /* L2 data only */
636#define L2CR_L2I 0x00200000 /* L2 global invalidate */
637#define L2CR_L2CTL 0x00100000 /* L2 RAM control */
638#define L2CR_L2WT 0x00080000 /* L2 write-through */
639#define L2CR_L2TS 0x00040000 /* L2 test support */
640#define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */
641#define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */
642#define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */
643#define L2CR_L2SL 0x00008000 /* L2 DLL slow */
644#define L2CR_L2DF 0x00004000 /* L2 differential clock */
645#define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */
646#define L2CR_L2IP 0x00000001 /* L2 GI in progress */
647#define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */
648#define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */
649#define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */
650#define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */
651#define SPRN_L3CR 0x3FA /* Level 3 Cache Control Register */
652#define L3CR_L3E 0x80000000 /* L3 enable */
653#define L3CR_L3PE 0x40000000 /* L3 data parity enable */
654#define L3CR_L3APE 0x20000000 /* L3 addr parity enable */
655#define L3CR_L3SIZ 0x10000000 /* L3 size */
656#define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */
657#define L3CR_L3RES 0x04000000 /* L3 special reserved bit */
658#define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */
659#define L3CR_L3IO 0x00400000 /* L3 instruction only */
660#define L3CR_L3SPO 0x00040000 /* L3 sample point override */
661#define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */
662#define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */
663#define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */
664#define L3CR_L3HWF 0x00000800 /* L3 hardware flush */
665#define L3CR_L3I 0x00000400 /* L3 global invalidate */
666#define L3CR_L3RT 0x00000300 /* L3 SRAM type */
667#define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */
668#define L3CR_L3DO 0x00000040 /* L3 data only mode */
669#define L3CR_PMEN 0x00000004 /* L3 private memory enable */
670#define L3CR_PMSIZ 0x00000001 /* L3 private memory size */
671
672#define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */
673#define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */
674#define SPRN_LDSTCR 0x3f8 /* Load/Store control register */
675#define SPRN_LDSTDB 0x3f4 /* */
676#define SPRN_LR 0x008 /* Link Register */
677#ifndef SPRN_PIR
678#define SPRN_PIR 0x3FF /* Processor Identification Register */
679#endif
680#define SPRN_TIR 0x1BE /* Thread Identification Register */
681#define SPRN_PTCR 0x1D0 /* Partition table control Register */
682#define SPRN_PSPB 0x09F /* Problem State Priority Boost reg */
683#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
684#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
685#define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
686#define SPRN_PVR 0x11F /* Processor Version Register */
687#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
688#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
689#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
690#define SPRN_ASR 0x118 /* Address Space Register */
691#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
692#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
693#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
694#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
695#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
696#define SPRN_USPRG3 0x103 /* SPRG3 userspace read */
697#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
698#define SPRN_USPRG4 0x104 /* SPRG4 userspace read */
699#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
700#define SPRN_USPRG5 0x105 /* SPRG5 userspace read */
701#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
702#define SPRN_USPRG6 0x106 /* SPRG6 userspace read */
703#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
704#define SPRN_USPRG7 0x107 /* SPRG7 userspace read */
705#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
706#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
707#define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */
708#define SRR1_ISI_N_OR_G 0x10000000 /* ISI: Access is no-exec or G */
709#define SRR1_ISI_PROT 0x08000000 /* ISI: Other protection fault */
710#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */
711#define SRR1_WAKEMASK_P8 0x003c0000 /* reason for wakeup on POWER8 and 9 */
712#define SRR1_WAKEMCE_RESVD 0x003c0000 /* Unused/reserved value used by MCE wakeup to indicate cause to idle wakeup handler */
713#define SRR1_WAKESYSERR 0x00300000 /* System error */
714#define SRR1_WAKEEE 0x00200000 /* External interrupt */
715#define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virtualization Interrupt (P9) */
716#define SRR1_WAKEMT 0x00280000 /* mtctrl */
717#define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
718#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
719#define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell on P8 */
720#define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */
721#define SRR1_WAKERESET 0x00100000 /* System reset */
722#define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell on P8 */
723#define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask [46:47] */
724#define SRR1_WS_DEEPEST 0x00030000 /* Some resources not maintained,
725 * may not be recoverable */
726#define SRR1_WS_DEEPER 0x00020000 /* Some resources not maintained */
727#define SRR1_WS_DEEP 0x00010000 /* All resources maintained */
728#define SRR1_PROGTM 0x00200000 /* TM Bad Thing */
729#define SRR1_PROGFPE 0x00100000 /* Floating Point Enabled */
730#define SRR1_PROGILL 0x00080000 /* Illegal instruction */
731#define SRR1_PROGPRIV 0x00040000 /* Privileged instruction */
732#define SRR1_PROGTRAP 0x00020000 /* Trap */
733#define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */
734
735#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */
736#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */
737#define HSRR1_DENORM 0x00100000 /* Denorm exception */
738
739#define SPRN_TBCTL 0x35f /* PA6T Timebase control register */
740#define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */
741#define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */
742#define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */
743#define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */
744
745#ifndef SPRN_SVR
746#define SPRN_SVR 0x11E /* System Version Register */
747#endif
748#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
749/* these bits were defined in inverted endian sense originally, ugh, confusing */
750#define THRM1_TIN (1 << 31)
751#define THRM1_TIV (1 << 30)
752#define THRM1_THRES(x) ((x&0x7f)<<23)
753#define THRM3_SITV(x) ((x&0x3fff)<<1)
754#define THRM1_TID (1<<2)
755#define THRM1_TIE (1<<1)
756#define THRM1_V (1<<0)
757#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
758#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
759#define THRM3_E (1<<0)
760#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
761#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
762#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
763#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
764#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
765#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
766#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
767#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
768#define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
769#define SPRN_XER 0x001 /* Fixed Point Exception Register */
770
771#define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */
772#define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */
773#define SPRN_PMC1_GEKKO 0x3B9 /* Gekko Performance Monitor Control 1 */
774#define SPRN_PMC2_GEKKO 0x3BA /* Gekko Performance Monitor Control 2 */
775#define SPRN_PMC3_GEKKO 0x3BD /* Gekko Performance Monitor Control 3 */
776#define SPRN_PMC4_GEKKO 0x3BE /* Gekko Performance Monitor Control 4 */
777#define SPRN_WPAR_GEKKO 0x399 /* Gekko Write Pipe Address Register */
778
779#define SPRN_SCOMC 0x114 /* SCOM Access Control */
780#define SPRN_SCOMD 0x115 /* SCOM Access DATA */
781
782/* Performance monitor SPRs */
783#ifdef CONFIG_PPC64
784#define SPRN_MMCR0 795
785#define MMCR0_FC 0x80000000UL /* freeze counters */
786#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
787#define MMCR0_KERNEL_DISABLE MMCR0_FCS
788#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
789#define MMCR0_PROBLEM_DISABLE MMCR0_FCP
790#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
791#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
792#define MMCR0_PMXE ASM_CONST(0x04000000) /* perf mon exception enable */
793#define MMCR0_FCECE ASM_CONST(0x02000000) /* freeze ctrs on enabled cond or event */
794#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
795#define MMCR0_BHRBA 0x00200000UL /* BHRB Access allowed in userspace */
796#define MMCR0_EBE 0x00100000UL /* Event based branch enable */
797#define MMCR0_PMCC 0x000c0000UL /* PMC control */
798#define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */
799#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
800#define MMCR0_PMCjCE ASM_CONST(0x00004000) /* PMCj count enable*/
801#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
802#define MMCR0_PMAO_SYNC ASM_CONST(0x00000800) /* PMU intr is synchronous */
803#define MMCR0_C56RUN ASM_CONST(0x00000100) /* PMC5/6 count when RUN=0 */
804/* performance monitor alert has occurred, set to 0 after handling exception */
805#define MMCR0_PMAO ASM_CONST(0x00000080)
806#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
807#define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */
808#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
809#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */
810#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
811#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
812#define SPRN_MMCR1 798
813#define SPRN_MMCR2 785
814#define SPRN_UMMCR2 769
815#define SPRN_MMCRA 0x312
816#define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */
817#define MMCRA_SDAR_DCACHE_MISS 0x40000000UL
818#define MMCRA_SDAR_ERAT_MISS 0x20000000UL
819#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
820#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
821#define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */
822#define MMCRA_SLOT_SHIFT 24
823#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
824#define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL /* SDAR/SIAR synced */
825#define POWER6_MMCRA_SIHV 0x0000040000000000ULL
826#define POWER6_MMCRA_SIPR 0x0000020000000000ULL
827#define POWER6_MMCRA_THRM 0x00000020UL
828#define POWER6_MMCRA_OTHER 0x0000000EUL
829
830#define POWER7P_MMCRA_SIAR_VALID 0x10000000 /* P7+ SIAR contents valid */
831#define POWER7P_MMCRA_SDAR_VALID 0x08000000 /* P7+ SDAR contents valid */
832
833#define SPRN_MMCRH 316 /* Hypervisor monitor mode control register */
834#define SPRN_MMCRS 894 /* Supervisor monitor mode control register */
835#define SPRN_MMCRC 851 /* Core monitor mode control register */
836#define SPRN_EBBHR 804 /* Event based branch handler register */
837#define SPRN_EBBRR 805 /* Event based branch return register */
838#define SPRN_BESCR 806 /* Branch event status and control register */
839#define BESCR_GE 0x8000000000000000ULL /* Global Enable */
840#define SPRN_WORT 895 /* Workload optimization register - thread */
841#define SPRN_WORC 863 /* Workload optimization register - core */
842
843#define SPRN_PMC1 787
844#define SPRN_PMC2 788
845#define SPRN_PMC3 789
846#define SPRN_PMC4 790
847#define SPRN_PMC5 791
848#define SPRN_PMC6 792
849#define SPRN_PMC7 793
850#define SPRN_PMC8 794
851#define SPRN_SIER 784
852#define SIER_SIPR 0x2000000 /* Sampled MSR_PR */
853#define SIER_SIHV 0x1000000 /* Sampled MSR_HV */
854#define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */
855#define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */
856#define SPRN_SIAR 796
857#define SPRN_SDAR 797
858#define SPRN_TACR 888
859#define SPRN_TCSCR 889
860#define SPRN_CSIGR 890
861#define SPRN_SPMC1 892
862#define SPRN_SPMC2 893
863
864/* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */
865#define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO)
866#define MMCR2_USER_MASK 0x4020100804020000UL /* (FC1P|FC2P|FC3P|FC4P|FC5P|FC6P) */
867#define SIER_USER_MASK 0x7fffffUL
868
869#define SPRN_PA6T_MMCR0 795
870#define PA6T_MMCR0_EN0 0x0000000000000001UL
871#define PA6T_MMCR0_EN1 0x0000000000000002UL
872#define PA6T_MMCR0_EN2 0x0000000000000004UL
873#define PA6T_MMCR0_EN3 0x0000000000000008UL
874#define PA6T_MMCR0_EN4 0x0000000000000010UL
875#define PA6T_MMCR0_EN5 0x0000000000000020UL
876#define PA6T_MMCR0_SUPEN 0x0000000000000040UL
877#define PA6T_MMCR0_PREN 0x0000000000000080UL
878#define PA6T_MMCR0_HYPEN 0x0000000000000100UL
879#define PA6T_MMCR0_FCM0 0x0000000000000200UL
880#define PA6T_MMCR0_FCM1 0x0000000000000400UL
881#define PA6T_MMCR0_INTGEN 0x0000000000000800UL
882#define PA6T_MMCR0_INTEN0 0x0000000000001000UL
883#define PA6T_MMCR0_INTEN1 0x0000000000002000UL
884#define PA6T_MMCR0_INTEN2 0x0000000000004000UL
885#define PA6T_MMCR0_INTEN3 0x0000000000008000UL
886#define PA6T_MMCR0_INTEN4 0x0000000000010000UL
887#define PA6T_MMCR0_INTEN5 0x0000000000020000UL
888#define PA6T_MMCR0_DISCNT 0x0000000000040000UL
889#define PA6T_MMCR0_UOP 0x0000000000080000UL
890#define PA6T_MMCR0_TRG 0x0000000000100000UL
891#define PA6T_MMCR0_TRGEN 0x0000000000200000UL
892#define PA6T_MMCR0_TRGREG 0x0000000001600000UL
893#define PA6T_MMCR0_SIARLOG 0x0000000002000000UL
894#define PA6T_MMCR0_SDARLOG 0x0000000004000000UL
895#define PA6T_MMCR0_PROEN 0x0000000008000000UL
896#define PA6T_MMCR0_PROLOG 0x0000000010000000UL
897#define PA6T_MMCR0_DAMEN2 0x0000000020000000UL
898#define PA6T_MMCR0_DAMEN3 0x0000000040000000UL
899#define PA6T_MMCR0_DAMEN4 0x0000000080000000UL
900#define PA6T_MMCR0_DAMEN5 0x0000000100000000UL
901#define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL
902#define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL
903#define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL
904#define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL
905#define PA6T_MMCR0_HANDDIS 0x0000002000000000UL
906#define PA6T_MMCR0_PCTEN 0x0000004000000000UL
907#define PA6T_MMCR0_SOCEN 0x0000008000000000UL
908#define PA6T_MMCR0_SOCMOD 0x0000010000000000UL
909
910#define SPRN_PA6T_MMCR1 798
911#define PA6T_MMCR1_ES2 0x00000000000000ffUL
912#define PA6T_MMCR1_ES3 0x000000000000ff00UL
913#define PA6T_MMCR1_ES4 0x0000000000ff0000UL
914#define PA6T_MMCR1_ES5 0x00000000ff000000UL
915
916#define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */
917#define SPRN_PA6T_UPMC1 772 /* ... */
918#define SPRN_PA6T_UPMC2 773
919#define SPRN_PA6T_UPMC3 774
920#define SPRN_PA6T_UPMC4 775
921#define SPRN_PA6T_UPMC5 776
922#define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */
923#define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */
924#define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */
925#define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */
926#define SPRN_PA6T_PMC0 787
927#define SPRN_PA6T_PMC1 788
928#define SPRN_PA6T_PMC2 789
929#define SPRN_PA6T_PMC3 790
930#define SPRN_PA6T_PMC4 791
931#define SPRN_PA6T_PMC5 792
932#define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */
933#define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */
934#define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */
935#define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */
936
937#define SPRN_PA6T_IER 981 /* Icache Error Register */
938#define SPRN_PA6T_DER 982 /* Dcache Error Register */
939#define SPRN_PA6T_BER 862 /* BIU Error Address Register */
940#define SPRN_PA6T_MER 849 /* MMU Error Register */
941
942#define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */
943#define SPRN_PA6T_IMA1 881 /* ... */
944#define SPRN_PA6T_IMA2 882
945#define SPRN_PA6T_IMA3 883
946#define SPRN_PA6T_IMA4 884
947#define SPRN_PA6T_IMA5 885
948#define SPRN_PA6T_IMA6 886
949#define SPRN_PA6T_IMA7 887
950#define SPRN_PA6T_IMA8 888
951#define SPRN_PA6T_IMA9 889
952#define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */
953#define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */
954#define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */
955#define SPRN_BKMK 1020 /* Cell Bookmark Register */
956#define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */
957
958
959#else /* 32-bit */
960#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
961#define MMCR0_FC 0x80000000UL /* freeze counters */
962#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
963#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
964#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
965#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
966#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
967#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
968#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
969#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
970#define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/
971#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
972#define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
973#define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
974
975#define SPRN_MMCR1 956
976#define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
977#define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
978#define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
979#define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
980#define SPRN_MMCR2 944
981#define SPRN_PMC1 953 /* Performance Counter Register 1 */
982#define SPRN_PMC2 954 /* Performance Counter Register 2 */
983#define SPRN_PMC3 957 /* Performance Counter Register 3 */
984#define SPRN_PMC4 958 /* Performance Counter Register 4 */
985#define SPRN_PMC5 945 /* Performance Counter Register 5 */
986#define SPRN_PMC6 946 /* Performance Counter Register 6 */
987
988#define SPRN_SIAR 955 /* Sampled Instruction Address Register */
989
990/* Bit definitions for MMCR0 and PMC1 / PMC2. */
991#define MMCR0_PMC1_CYCLES (1 << 7)
992#define MMCR0_PMC1_ICACHEMISS (5 << 7)
993#define MMCR0_PMC1_DTLB (6 << 7)
994#define MMCR0_PMC2_DCACHEMISS 0x6
995#define MMCR0_PMC2_CYCLES 0x1
996#define MMCR0_PMC2_ITLB 0x7
997#define MMCR0_PMC2_LOADMISSTIME 0x5
998#endif
999
1000/*
1001 * SPRG usage:
1002 *
1003 * All 64-bit:
1004 * - SPRG1 stores PACA pointer except 64-bit server in
1005 * HV mode in which case it is HSPRG0
1006 *
1007 * 64-bit server:
1008 * - SPRG0 scratch for TM recheckpoint/reclaim (reserved for HV on Power4)
1009 * - SPRG2 scratch for exception vectors
1010 * - SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
1011 * - HSPRG0 stores PACA in HV mode
1012 * - HSPRG1 scratch for "HV" exceptions
1013 *
1014 * 64-bit embedded
1015 * - SPRG0 generic exception scratch
1016 * - SPRG2 TLB exception stack
1017 * - SPRG3 critical exception scratch (user visible, sorry!)
1018 * - SPRG4 unused (user visible)
1019 * - SPRG6 TLB miss scratch (user visible, sorry !)
1020 * - SPRG7 CPU and NUMA node for VDSO getcpu (user visible)
1021 * - SPRG8 machine check exception scratch
1022 * - SPRG9 debug exception scratch
1023 *
1024 * All 32-bit:
1025 * - SPRG3 current thread_info pointer
1026 * (virtual on BookE, physical on others)
1027 *
1028 * 32-bit classic:
1029 * - SPRG0 scratch for exception vectors
1030 * - SPRG1 scratch for exception vectors
1031 * - SPRG2 indicator that we are in RTAS
1032 * - SPRG4 (603 only) pseudo TLB LRU data
1033 *
1034 * 32-bit 40x:
1035 * - SPRG0 scratch for exception vectors
1036 * - SPRG1 scratch for exception vectors
1037 * - SPRG2 scratch for exception vectors
1038 * - SPRG4 scratch for exception vectors (not 403)
1039 * - SPRG5 scratch for exception vectors (not 403)
1040 * - SPRG6 scratch for exception vectors (not 403)
1041 * - SPRG7 scratch for exception vectors (not 403)
1042 *
1043 * 32-bit 440 and FSL BookE:
1044 * - SPRG0 scratch for exception vectors
1045 * - SPRG1 scratch for exception vectors (*)
1046 * - SPRG2 scratch for crit interrupts handler
1047 * - SPRG4 scratch for exception vectors
1048 * - SPRG5 scratch for exception vectors
1049 * - SPRG6 scratch for machine check handler
1050 * - SPRG7 scratch for exception vectors
1051 * - SPRG9 scratch for debug vectors (e500 only)
1052 *
1053 * Additionally, BookE separates "read" and "write"
1054 * of those registers. That allows to use the userspace
1055 * readable variant for reads, which can avoid a fault
1056 * with KVM type virtualization.
1057 *
1058 * 32-bit 8xx:
1059 * - SPRG0 scratch for exception vectors
1060 * - SPRG1 scratch for exception vectors
1061 * - SPRG2 scratch for exception vectors
1062 *
1063 */
1064#ifdef CONFIG_PPC64
1065#define SPRN_SPRG_PACA SPRN_SPRG1
1066#else
1067#define SPRN_SPRG_THREAD SPRN_SPRG3
1068#endif
1069
1070#ifdef CONFIG_PPC_BOOK3S_64
1071#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2
1072#define SPRN_SPRG_HPACA SPRN_HSPRG0
1073#define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1
1074#define SPRN_SPRG_VDSO_READ SPRN_USPRG3
1075#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG3
1076
1077#define GET_PACA(rX) \
1078 BEGIN_FTR_SECTION_NESTED(66); \
1079 mfspr rX,SPRN_SPRG_PACA; \
1080 FTR_SECTION_ELSE_NESTED(66); \
1081 mfspr rX,SPRN_SPRG_HPACA; \
1082 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1083
1084#define SET_PACA(rX) \
1085 BEGIN_FTR_SECTION_NESTED(66); \
1086 mtspr SPRN_SPRG_PACA,rX; \
1087 FTR_SECTION_ELSE_NESTED(66); \
1088 mtspr SPRN_SPRG_HPACA,rX; \
1089 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1090
1091#define GET_SCRATCH0(rX) \
1092 BEGIN_FTR_SECTION_NESTED(66); \
1093 mfspr rX,SPRN_SPRG_SCRATCH0; \
1094 FTR_SECTION_ELSE_NESTED(66); \
1095 mfspr rX,SPRN_SPRG_HSCRATCH0; \
1096 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1097
1098#define SET_SCRATCH0(rX) \
1099 BEGIN_FTR_SECTION_NESTED(66); \
1100 mtspr SPRN_SPRG_SCRATCH0,rX; \
1101 FTR_SECTION_ELSE_NESTED(66); \
1102 mtspr SPRN_SPRG_HSCRATCH0,rX; \
1103 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1104
1105#else /* CONFIG_PPC_BOOK3S_64 */
1106#define GET_SCRATCH0(rX) mfspr rX,SPRN_SPRG_SCRATCH0
1107#define SET_SCRATCH0(rX) mtspr SPRN_SPRG_SCRATCH0,rX
1108
1109#endif
1110
1111#ifdef CONFIG_PPC_BOOK3E_64
1112#define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8
1113#define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG3
1114#define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9
1115#define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2
1116#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6
1117#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0
1118#define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH
1119#define SPRN_SPRG_VDSO_READ SPRN_USPRG7
1120#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG7
1121
1122#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX
1123#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA
1124
1125#endif
1126
1127#ifdef CONFIG_PPC_BOOK3S_32
1128#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1129#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1130#define SPRN_SPRG_RTAS SPRN_SPRG2
1131#define SPRN_SPRG_603_LRU SPRN_SPRG4
1132#endif
1133
1134#ifdef CONFIG_40x
1135#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1136#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1137#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1138#define SPRN_SPRG_SCRATCH3 SPRN_SPRG4
1139#define SPRN_SPRG_SCRATCH4 SPRN_SPRG5
1140#define SPRN_SPRG_SCRATCH5 SPRN_SPRG6
1141#define SPRN_SPRG_SCRATCH6 SPRN_SPRG7
1142#endif
1143
1144#ifdef CONFIG_BOOKE
1145#define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0
1146#define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0
1147#define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1
1148#define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1
1149#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
1150#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
1151#define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R
1152#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W
1153#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R
1154#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W
1155#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1
1156#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1
1157#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R
1158#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W
1159#ifdef CONFIG_E200
1160#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG6R
1161#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG6W
1162#else
1163#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9
1164#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9
1165#endif
1166#endif
1167
1168#ifdef CONFIG_PPC_8xx
1169#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1170#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1171#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1172#endif
1173
1174
1175
1176/*
1177 * An mtfsf instruction with the L bit set. On CPUs that support this a
1178 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
1179 *
1180 * Until binutils gets the new form of mtfsf, hardwire the instruction.
1181 */
1182#ifdef CONFIG_PPC64
1183#define MTFSF_L(REG) \
1184 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
1185#else
1186#define MTFSF_L(REG) mtfsf 0xff, (REG)
1187#endif
1188
1189/* Processor Version Register (PVR) field extraction */
1190
1191#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
1192#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
1193
1194#define pvr_version_is(pvr) (PVR_VER(mfspr(SPRN_PVR)) == (pvr))
1195
1196/*
1197 * IBM has further subdivided the standard PowerPC 16-bit version and
1198 * revision subfields of the PVR for the PowerPC 403s into the following:
1199 */
1200
1201#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
1202#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
1203#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
1204#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
1205#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
1206#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
1207
1208/* Processor Version Numbers */
1209
1210#define PVR_403GA 0x00200000
1211#define PVR_403GB 0x00200100
1212#define PVR_403GC 0x00200200
1213#define PVR_403GCX 0x00201400
1214#define PVR_405GP 0x40110000
1215#define PVR_476 0x11a52000
1216#define PVR_476FPE 0x7ff50000
1217#define PVR_STB03XXX 0x40310000
1218#define PVR_NP405H 0x41410000
1219#define PVR_NP405L 0x41610000
1220#define PVR_601 0x00010000
1221#define PVR_602 0x00050000
1222#define PVR_603 0x00030000
1223#define PVR_603e 0x00060000
1224#define PVR_603ev 0x00070000
1225#define PVR_603r 0x00071000
1226#define PVR_604 0x00040000
1227#define PVR_604e 0x00090000
1228#define PVR_604r 0x000A0000
1229#define PVR_620 0x00140000
1230#define PVR_740 0x00080000
1231#define PVR_750 PVR_740
1232#define PVR_740P 0x10080000
1233#define PVR_750P PVR_740P
1234#define PVR_7400 0x000C0000
1235#define PVR_7410 0x800C0000
1236#define PVR_7450 0x80000000
1237#define PVR_8540 0x80200000
1238#define PVR_8560 0x80200000
1239#define PVR_VER_E500V1 0x8020
1240#define PVR_VER_E500V2 0x8021
1241#define PVR_VER_E500MC 0x8023
1242#define PVR_VER_E5500 0x8024
1243#define PVR_VER_E6500 0x8040
1244
1245/*
1246 * For the 8xx processors, all of them report the same PVR family for
1247 * the PowerPC core. The various versions of these processors must be
1248 * differentiated by the version number in the Communication Processor
1249 * Module (CPM).
1250 */
1251#define PVR_8xx 0x00500000
1252
1253#define PVR_8240 0x00810100
1254#define PVR_8245 0x80811014
1255#define PVR_8260 PVR_8240
1256
1257/* 476 Simulator seems to currently have the PVR of the 602... */
1258#define PVR_476_ISS 0x00052000
1259
1260/* 64-bit processors */
1261#define PVR_NORTHSTAR 0x0033
1262#define PVR_PULSAR 0x0034
1263#define PVR_POWER4 0x0035
1264#define PVR_ICESTAR 0x0036
1265#define PVR_SSTAR 0x0037
1266#define PVR_POWER4p 0x0038
1267#define PVR_970 0x0039
1268#define PVR_POWER5 0x003A
1269#define PVR_POWER5p 0x003B
1270#define PVR_970FX 0x003C
1271#define PVR_POWER6 0x003E
1272#define PVR_POWER7 0x003F
1273#define PVR_630 0x0040
1274#define PVR_630p 0x0041
1275#define PVR_970MP 0x0044
1276#define PVR_970GX 0x0045
1277#define PVR_POWER7p 0x004A
1278#define PVR_POWER8E 0x004B
1279#define PVR_POWER8NVL 0x004C
1280#define PVR_POWER8 0x004D
1281#define PVR_POWER9 0x004E
1282#define PVR_BE 0x0070
1283#define PVR_PA6T 0x0090
1284
1285/* "Logical" PVR values defined in PAPR, representing architecture levels */
1286#define PVR_ARCH_204 0x0f000001
1287#define PVR_ARCH_205 0x0f000002
1288#define PVR_ARCH_206 0x0f000003
1289#define PVR_ARCH_206p 0x0f100003
1290#define PVR_ARCH_207 0x0f000004
1291#define PVR_ARCH_300 0x0f000005
1292
1293/* Macros for setting and retrieving special purpose registers */
1294#ifndef __ASSEMBLY__
1295#define mfmsr() ({unsigned long rval; \
1296 asm volatile("mfmsr %0" : "=r" (rval) : \
1297 : "memory"); rval;})
1298#ifdef CONFIG_PPC_BOOK3S_64
1299#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
1300 : : "r" (v) : "memory")
1301#define mtmsr(v) __mtmsrd((v), 0)
1302#define __MTMSR "mtmsrd"
1303#else
1304#define mtmsr(v) asm volatile("mtmsr %0" : \
1305 : "r" ((unsigned long)(v)) \
1306 : "memory")
1307#define __MTMSR "mtmsr"
1308#endif
1309
1310static inline void mtmsr_isync(unsigned long val)
1311{
1312 asm volatile(__MTMSR " %0; " ASM_FTR_IFCLR("isync", "nop", %1) : :
1313 "r" (val), "i" (CPU_FTR_ARCH_206) : "memory");
1314}
1315
1316#define mfspr(rn) ({unsigned long rval; \
1317 asm volatile("mfspr %0," __stringify(rn) \
1318 : "=r" (rval)); rval;})
1319#ifndef mtspr
1320#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \
1321 : "r" ((unsigned long)(v)) \
1322 : "memory")
1323#endif
1324#define wrtspr(rn) asm volatile("mtspr " __stringify(rn) ",0" : \
1325 : : "memory")
1326
1327extern unsigned long msr_check_and_set(unsigned long bits);
1328extern bool strict_msr_control;
1329extern void __msr_check_and_clear(unsigned long bits);
1330static inline void msr_check_and_clear(unsigned long bits)
1331{
1332 if (strict_msr_control)
1333 __msr_check_and_clear(bits);
1334}
1335
1336#ifdef __powerpc64__
1337#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
1338#define mftb() ({unsigned long rval; \
1339 asm volatile( \
1340 "90: mfspr %0, %2;\n" \
1341 "97: cmpwi %0,0;\n" \
1342 " beq- 90b;\n" \
1343 "99:\n" \
1344 ".section __ftr_fixup,\"a\"\n" \
1345 ".align 3\n" \
1346 "98:\n" \
1347 " .8byte %1\n" \
1348 " .8byte %1\n" \
1349 " .8byte 97b-98b\n" \
1350 " .8byte 99b-98b\n" \
1351 " .8byte 0\n" \
1352 " .8byte 0\n" \
1353 ".previous" \
1354 : "=r" (rval) \
1355 : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \
1356 rval;})
1357#else
1358#define mftb() ({unsigned long rval; \
1359 asm volatile("mfspr %0, %1" : \
1360 "=r" (rval) : "i" (SPRN_TBRL)); rval;})
1361#endif /* !CONFIG_PPC_CELL */
1362
1363#else /* __powerpc64__ */
1364
1365#if defined(CONFIG_PPC_8xx)
1366#define mftbl() ({unsigned long rval; \
1367 asm volatile("mftbl %0" : "=r" (rval)); rval;})
1368#define mftbu() ({unsigned long rval; \
1369 asm volatile("mftbu %0" : "=r" (rval)); rval;})
1370#else
1371#define mftbl() ({unsigned long rval; \
1372 asm volatile("mfspr %0, %1" : "=r" (rval) : \
1373 "i" (SPRN_TBRL)); rval;})
1374#define mftbu() ({unsigned long rval; \
1375 asm volatile("mfspr %0, %1" : "=r" (rval) : \
1376 "i" (SPRN_TBRU)); rval;})
1377#endif
1378#define mftb() mftbl()
1379#endif /* !__powerpc64__ */
1380
1381#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
1382#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
1383
1384#ifdef CONFIG_PPC32
1385#define mfsrin(v) ({unsigned int rval; \
1386 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
1387 rval;})
1388#endif
1389
1390#define proc_trap() asm volatile("trap")
1391
1392extern unsigned long current_stack_pointer(void);
1393
1394extern unsigned long scom970_read(unsigned int address);
1395extern void scom970_write(unsigned int address, unsigned long value);
1396
1397struct pt_regs;
1398
1399extern void ppc_save_regs(struct pt_regs *regs);
1400
1401static inline void update_power8_hid0(unsigned long hid0)
1402{
1403 /*
1404 * The HID0 update on Power8 should at the very least be
1405 * preceded by a a SYNC instruction followed by an ISYNC
1406 * instruction
1407 */
1408 asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0));
1409}
1410#endif /* __ASSEMBLY__ */
1411#endif /* __KERNEL__ */
1412#endif /* _ASM_POWERPC_REG_H */