tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Autogenerated file by GPU Top : https://github.com/rib/gputop
3 * DO NOT EDIT manually!
4 *
5 *
6 * Copyright (c) 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 *
27 */
28
29#include <linux/sysfs.h>
30
31#include "i915_drv.h"
32#include "i915_oa_bxt.h"
33
34enum metric_set_id {
35 METRIC_SET_ID_RENDER_BASIC = 1,
36 METRIC_SET_ID_COMPUTE_BASIC,
37 METRIC_SET_ID_RENDER_PIPE_PROFILE,
38 METRIC_SET_ID_MEMORY_READS,
39 METRIC_SET_ID_MEMORY_WRITES,
40 METRIC_SET_ID_COMPUTE_EXTENDED,
41 METRIC_SET_ID_COMPUTE_L3_CACHE,
42 METRIC_SET_ID_HDC_AND_SF,
43 METRIC_SET_ID_L3_1,
44 METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
45 METRIC_SET_ID_SAMPLER,
46 METRIC_SET_ID_TDL_1,
47 METRIC_SET_ID_TDL_2,
48 METRIC_SET_ID_COMPUTE_EXTRA,
49 METRIC_SET_ID_TEST_OA,
50};
51
52int i915_oa_n_builtin_metric_sets_bxt = 15;
53
54static const struct i915_oa_reg b_counter_config_render_basic[] = {
55 { _MMIO(0x2710), 0x00000000 },
56 { _MMIO(0x2714), 0x00800000 },
57 { _MMIO(0x2720), 0x00000000 },
58 { _MMIO(0x2724), 0x00800000 },
59 { _MMIO(0x2740), 0x00000000 },
60};
61
62static const struct i915_oa_reg flex_eu_config_render_basic[] = {
63 { _MMIO(0xe458), 0x00005004 },
64 { _MMIO(0xe558), 0x00010003 },
65 { _MMIO(0xe658), 0x00012011 },
66 { _MMIO(0xe758), 0x00015014 },
67 { _MMIO(0xe45c), 0x00051050 },
68 { _MMIO(0xe55c), 0x00053052 },
69 { _MMIO(0xe65c), 0x00055054 },
70};
71
72static const struct i915_oa_reg mux_config_render_basic_0_sku_gte_0x03[] = {
73 { _MMIO(0x9888), 0x166c00f0 },
74 { _MMIO(0x9888), 0x12120280 },
75 { _MMIO(0x9888), 0x12320280 },
76 { _MMIO(0x9888), 0x11930317 },
77 { _MMIO(0x9888), 0x159303df },
78 { _MMIO(0x9888), 0x3f900c00 },
79 { _MMIO(0x9888), 0x419000a0 },
80 { _MMIO(0x9888), 0x002d1000 },
81 { _MMIO(0x9888), 0x062d4000 },
82 { _MMIO(0x9888), 0x082d5000 },
83 { _MMIO(0x9888), 0x0a2d1000 },
84 { _MMIO(0x9888), 0x0c2e0800 },
85 { _MMIO(0x9888), 0x0e2e5900 },
86 { _MMIO(0x9888), 0x0a4c8000 },
87 { _MMIO(0x9888), 0x0c4c8000 },
88 { _MMIO(0x9888), 0x0e4c4000 },
89 { _MMIO(0x9888), 0x064e8000 },
90 { _MMIO(0x9888), 0x084e8000 },
91 { _MMIO(0x9888), 0x0a4e2000 },
92 { _MMIO(0x9888), 0x1c4f0010 },
93 { _MMIO(0x9888), 0x0a6c0053 },
94 { _MMIO(0x9888), 0x106c0000 },
95 { _MMIO(0x9888), 0x1c6c0000 },
96 { _MMIO(0x9888), 0x1a0fcc00 },
97 { _MMIO(0x9888), 0x1c0f0002 },
98 { _MMIO(0x9888), 0x1c2c0040 },
99 { _MMIO(0x9888), 0x00101000 },
100 { _MMIO(0x9888), 0x04101000 },
101 { _MMIO(0x9888), 0x00114000 },
102 { _MMIO(0x9888), 0x08114000 },
103 { _MMIO(0x9888), 0x00120020 },
104 { _MMIO(0x9888), 0x08120021 },
105 { _MMIO(0x9888), 0x00141000 },
106 { _MMIO(0x9888), 0x08141000 },
107 { _MMIO(0x9888), 0x02308000 },
108 { _MMIO(0x9888), 0x04302000 },
109 { _MMIO(0x9888), 0x06318000 },
110 { _MMIO(0x9888), 0x08318000 },
111 { _MMIO(0x9888), 0x06320800 },
112 { _MMIO(0x9888), 0x08320840 },
113 { _MMIO(0x9888), 0x00320000 },
114 { _MMIO(0x9888), 0x06344000 },
115 { _MMIO(0x9888), 0x08344000 },
116 { _MMIO(0x9888), 0x0d931831 },
117 { _MMIO(0x9888), 0x0f939f3f },
118 { _MMIO(0x9888), 0x01939e80 },
119 { _MMIO(0x9888), 0x039303bc },
120 { _MMIO(0x9888), 0x0593000e },
121 { _MMIO(0x9888), 0x1993002a },
122 { _MMIO(0x9888), 0x07930000 },
123 { _MMIO(0x9888), 0x09930000 },
124 { _MMIO(0x9888), 0x1d900177 },
125 { _MMIO(0x9888), 0x1f900187 },
126 { _MMIO(0x9888), 0x35900000 },
127 { _MMIO(0x9888), 0x13904000 },
128 { _MMIO(0x9888), 0x21904000 },
129 { _MMIO(0x9888), 0x23904000 },
130 { _MMIO(0x9888), 0x25904000 },
131 { _MMIO(0x9888), 0x27904000 },
132 { _MMIO(0x9888), 0x2b904000 },
133 { _MMIO(0x9888), 0x2d904000 },
134 { _MMIO(0x9888), 0x2f904000 },
135 { _MMIO(0x9888), 0x31904000 },
136 { _MMIO(0x9888), 0x15904000 },
137 { _MMIO(0x9888), 0x17904000 },
138 { _MMIO(0x9888), 0x19904000 },
139 { _MMIO(0x9888), 0x1b904000 },
140 { _MMIO(0x9888), 0x53901110 },
141 { _MMIO(0x9888), 0x43900423 },
142 { _MMIO(0x9888), 0x55900111 },
143 { _MMIO(0x9888), 0x47900c02 },
144 { _MMIO(0x9888), 0x57900000 },
145 { _MMIO(0x9888), 0x49900020 },
146 { _MMIO(0x9888), 0x59901111 },
147 { _MMIO(0x9888), 0x4b900421 },
148 { _MMIO(0x9888), 0x37900000 },
149 { _MMIO(0x9888), 0x33900000 },
150 { _MMIO(0x9888), 0x4d900001 },
151 { _MMIO(0x9888), 0x45900821 },
152};
153
154static int
155get_render_basic_mux_config(struct drm_i915_private *dev_priv,
156 const struct i915_oa_reg **regs,
157 int *lens)
158{
159 int n = 0;
160
161 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
162 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
163
164 if (dev_priv->drm.pdev->revision >= 0x03) {
165 regs[n] = mux_config_render_basic_0_sku_gte_0x03;
166 lens[n] = ARRAY_SIZE(mux_config_render_basic_0_sku_gte_0x03);
167 n++;
168 }
169
170 return n;
171}
172
173static const struct i915_oa_reg b_counter_config_compute_basic[] = {
174 { _MMIO(0x2710), 0x00000000 },
175 { _MMIO(0x2714), 0x00800000 },
176 { _MMIO(0x2720), 0x00000000 },
177 { _MMIO(0x2724), 0x00800000 },
178 { _MMIO(0x2740), 0x00000000 },
179};
180
181static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
182 { _MMIO(0xe458), 0x00005004 },
183 { _MMIO(0xe558), 0x00000003 },
184 { _MMIO(0xe658), 0x00002001 },
185 { _MMIO(0xe758), 0x00778008 },
186 { _MMIO(0xe45c), 0x00088078 },
187 { _MMIO(0xe55c), 0x00808708 },
188 { _MMIO(0xe65c), 0x00a08908 },
189};
190
191static const struct i915_oa_reg mux_config_compute_basic[] = {
192 { _MMIO(0x9888), 0x104f00e0 },
193 { _MMIO(0x9888), 0x124f1c00 },
194 { _MMIO(0x9888), 0x39900340 },
195 { _MMIO(0x9888), 0x3f900c00 },
196 { _MMIO(0x9888), 0x41900000 },
197 { _MMIO(0x9888), 0x002d5000 },
198 { _MMIO(0x9888), 0x062d4000 },
199 { _MMIO(0x9888), 0x082d4000 },
200 { _MMIO(0x9888), 0x0a2d1000 },
201 { _MMIO(0x9888), 0x0c2d5000 },
202 { _MMIO(0x9888), 0x0e2d4000 },
203 { _MMIO(0x9888), 0x0c2e1400 },
204 { _MMIO(0x9888), 0x0e2e5100 },
205 { _MMIO(0x9888), 0x102e0114 },
206 { _MMIO(0x9888), 0x044cc000 },
207 { _MMIO(0x9888), 0x0a4c8000 },
208 { _MMIO(0x9888), 0x0c4c8000 },
209 { _MMIO(0x9888), 0x0e4c4000 },
210 { _MMIO(0x9888), 0x104c8000 },
211 { _MMIO(0x9888), 0x124c8000 },
212 { _MMIO(0x9888), 0x164c2000 },
213 { _MMIO(0x9888), 0x004ea000 },
214 { _MMIO(0x9888), 0x064e8000 },
215 { _MMIO(0x9888), 0x084e8000 },
216 { _MMIO(0x9888), 0x0a4e2000 },
217 { _MMIO(0x9888), 0x0c4ea000 },
218 { _MMIO(0x9888), 0x0e4e8000 },
219 { _MMIO(0x9888), 0x004f6b42 },
220 { _MMIO(0x9888), 0x064f6200 },
221 { _MMIO(0x9888), 0x084f4100 },
222 { _MMIO(0x9888), 0x0a4f0061 },
223 { _MMIO(0x9888), 0x0c4f6c4c },
224 { _MMIO(0x9888), 0x0e4f4b00 },
225 { _MMIO(0x9888), 0x1a4f0000 },
226 { _MMIO(0x9888), 0x1c4f0000 },
227 { _MMIO(0x9888), 0x180f5000 },
228 { _MMIO(0x9888), 0x1a0f8800 },
229 { _MMIO(0x9888), 0x1c0f08a2 },
230 { _MMIO(0x9888), 0x182c4000 },
231 { _MMIO(0x9888), 0x1c2c1451 },
232 { _MMIO(0x9888), 0x1e2c0001 },
233 { _MMIO(0x9888), 0x1a2c0010 },
234 { _MMIO(0x9888), 0x01938000 },
235 { _MMIO(0x9888), 0x0f938000 },
236 { _MMIO(0x9888), 0x19938a28 },
237 { _MMIO(0x9888), 0x03938000 },
238 { _MMIO(0x9888), 0x19900177 },
239 { _MMIO(0x9888), 0x1b900178 },
240 { _MMIO(0x9888), 0x1d900125 },
241 { _MMIO(0x9888), 0x1f900123 },
242 { _MMIO(0x9888), 0x35900000 },
243 { _MMIO(0x9888), 0x13904000 },
244 { _MMIO(0x9888), 0x21904000 },
245 { _MMIO(0x9888), 0x25904000 },
246 { _MMIO(0x9888), 0x27904000 },
247 { _MMIO(0x9888), 0x2b904000 },
248 { _MMIO(0x9888), 0x2d904000 },
249 { _MMIO(0x9888), 0x31904000 },
250 { _MMIO(0x9888), 0x15904000 },
251 { _MMIO(0x9888), 0x53901000 },
252 { _MMIO(0x9888), 0x43900000 },
253 { _MMIO(0x9888), 0x55900111 },
254 { _MMIO(0x9888), 0x47900000 },
255 { _MMIO(0x9888), 0x57900000 },
256 { _MMIO(0x9888), 0x49900000 },
257 { _MMIO(0x9888), 0x59900000 },
258 { _MMIO(0x9888), 0x4b900000 },
259 { _MMIO(0x9888), 0x37900000 },
260 { _MMIO(0x9888), 0x33900000 },
261 { _MMIO(0x9888), 0x4d900000 },
262 { _MMIO(0x9888), 0x45900000 },
263};
264
265static int
266get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
267 const struct i915_oa_reg **regs,
268 int *lens)
269{
270 int n = 0;
271
272 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
273 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
274
275 regs[n] = mux_config_compute_basic;
276 lens[n] = ARRAY_SIZE(mux_config_compute_basic);
277 n++;
278
279 return n;
280}
281
282static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
283 { _MMIO(0x2724), 0xf0800000 },
284 { _MMIO(0x2720), 0x00000000 },
285 { _MMIO(0x2714), 0xf0800000 },
286 { _MMIO(0x2710), 0x00000000 },
287 { _MMIO(0x2740), 0x00000000 },
288 { _MMIO(0x2770), 0x0007ffea },
289 { _MMIO(0x2774), 0x00007ffc },
290 { _MMIO(0x2778), 0x0007affa },
291 { _MMIO(0x277c), 0x0000f5fd },
292 { _MMIO(0x2780), 0x00079ffa },
293 { _MMIO(0x2784), 0x0000f3fb },
294 { _MMIO(0x2788), 0x0007bf7a },
295 { _MMIO(0x278c), 0x0000f7e7 },
296 { _MMIO(0x2790), 0x0007fefa },
297 { _MMIO(0x2794), 0x0000f7cf },
298 { _MMIO(0x2798), 0x00077ffa },
299 { _MMIO(0x279c), 0x0000efdf },
300 { _MMIO(0x27a0), 0x0006fffa },
301 { _MMIO(0x27a4), 0x0000cfbf },
302 { _MMIO(0x27a8), 0x0003fffa },
303 { _MMIO(0x27ac), 0x00005f7f },
304};
305
306static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
307 { _MMIO(0xe458), 0x00005004 },
308 { _MMIO(0xe558), 0x00015014 },
309 { _MMIO(0xe658), 0x00025024 },
310 { _MMIO(0xe758), 0x00035034 },
311 { _MMIO(0xe45c), 0x00045044 },
312 { _MMIO(0xe55c), 0x00055054 },
313 { _MMIO(0xe65c), 0x00065064 },
314};
315
316static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
317 { _MMIO(0x9888), 0x0c2e001f },
318 { _MMIO(0x9888), 0x0a2f0000 },
319 { _MMIO(0x9888), 0x10186800 },
320 { _MMIO(0x9888), 0x11810019 },
321 { _MMIO(0x9888), 0x15810013 },
322 { _MMIO(0x9888), 0x13820020 },
323 { _MMIO(0x9888), 0x11830020 },
324 { _MMIO(0x9888), 0x17840000 },
325 { _MMIO(0x9888), 0x11860007 },
326 { _MMIO(0x9888), 0x21860000 },
327 { _MMIO(0x9888), 0x178703e0 },
328 { _MMIO(0x9888), 0x0c2d8000 },
329 { _MMIO(0x9888), 0x042d4000 },
330 { _MMIO(0x9888), 0x062d1000 },
331 { _MMIO(0x9888), 0x022e5400 },
332 { _MMIO(0x9888), 0x002e0000 },
333 { _MMIO(0x9888), 0x0e2e0080 },
334 { _MMIO(0x9888), 0x082f0040 },
335 { _MMIO(0x9888), 0x002f0000 },
336 { _MMIO(0x9888), 0x06143000 },
337 { _MMIO(0x9888), 0x06174000 },
338 { _MMIO(0x9888), 0x06180012 },
339 { _MMIO(0x9888), 0x00180000 },
340 { _MMIO(0x9888), 0x0d804000 },
341 { _MMIO(0x9888), 0x0f804000 },
342 { _MMIO(0x9888), 0x05804000 },
343 { _MMIO(0x9888), 0x09810200 },
344 { _MMIO(0x9888), 0x0b810030 },
345 { _MMIO(0x9888), 0x03810003 },
346 { _MMIO(0x9888), 0x21819140 },
347 { _MMIO(0x9888), 0x23819050 },
348 { _MMIO(0x9888), 0x25810018 },
349 { _MMIO(0x9888), 0x0b820980 },
350 { _MMIO(0x9888), 0x03820d80 },
351 { _MMIO(0x9888), 0x11820000 },
352 { _MMIO(0x9888), 0x0182c000 },
353 { _MMIO(0x9888), 0x07828000 },
354 { _MMIO(0x9888), 0x09824000 },
355 { _MMIO(0x9888), 0x0f828000 },
356 { _MMIO(0x9888), 0x0d830004 },
357 { _MMIO(0x9888), 0x0583000c },
358 { _MMIO(0x9888), 0x0f831000 },
359 { _MMIO(0x9888), 0x01848072 },
360 { _MMIO(0x9888), 0x11840000 },
361 { _MMIO(0x9888), 0x07848000 },
362 { _MMIO(0x9888), 0x09844000 },
363 { _MMIO(0x9888), 0x0f848000 },
364 { _MMIO(0x9888), 0x07860000 },
365 { _MMIO(0x9888), 0x09860092 },
366 { _MMIO(0x9888), 0x0f860400 },
367 { _MMIO(0x9888), 0x01869100 },
368 { _MMIO(0x9888), 0x0f870065 },
369 { _MMIO(0x9888), 0x01870000 },
370 { _MMIO(0x9888), 0x19930800 },
371 { _MMIO(0x9888), 0x0b938000 },
372 { _MMIO(0x9888), 0x0d938000 },
373 { _MMIO(0x9888), 0x1b952000 },
374 { _MMIO(0x9888), 0x1d955055 },
375 { _MMIO(0x9888), 0x1f951455 },
376 { _MMIO(0x9888), 0x0992a000 },
377 { _MMIO(0x9888), 0x0f928000 },
378 { _MMIO(0x9888), 0x1192a800 },
379 { _MMIO(0x9888), 0x1392028a },
380 { _MMIO(0x9888), 0x0b92a000 },
381 { _MMIO(0x9888), 0x0d922000 },
382 { _MMIO(0x9888), 0x13908000 },
383 { _MMIO(0x9888), 0x21908000 },
384 { _MMIO(0x9888), 0x23908000 },
385 { _MMIO(0x9888), 0x25908000 },
386 { _MMIO(0x9888), 0x27908000 },
387 { _MMIO(0x9888), 0x29908000 },
388 { _MMIO(0x9888), 0x2b908000 },
389 { _MMIO(0x9888), 0x2d904000 },
390 { _MMIO(0x9888), 0x2f908000 },
391 { _MMIO(0x9888), 0x31908000 },
392 { _MMIO(0x9888), 0x15908000 },
393 { _MMIO(0x9888), 0x17908000 },
394 { _MMIO(0x9888), 0x19908000 },
395 { _MMIO(0x9888), 0x1b908000 },
396 { _MMIO(0x9888), 0x1d904000 },
397 { _MMIO(0x9888), 0x1f904000 },
398 { _MMIO(0x9888), 0x53900000 },
399 { _MMIO(0x9888), 0x43900c01 },
400 { _MMIO(0x9888), 0x55900000 },
401 { _MMIO(0x9888), 0x47900000 },
402 { _MMIO(0x9888), 0x57900000 },
403 { _MMIO(0x9888), 0x49900863 },
404 { _MMIO(0x9888), 0x59900000 },
405 { _MMIO(0x9888), 0x4b900061 },
406 { _MMIO(0x9888), 0x37900000 },
407 { _MMIO(0x9888), 0x33900000 },
408 { _MMIO(0x9888), 0x4d900000 },
409 { _MMIO(0x9888), 0x45900c22 },
410};
411
412static int
413get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
414 const struct i915_oa_reg **regs,
415 int *lens)
416{
417 int n = 0;
418
419 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
420 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
421
422 regs[n] = mux_config_render_pipe_profile;
423 lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile);
424 n++;
425
426 return n;
427}
428
429static const struct i915_oa_reg b_counter_config_memory_reads[] = {
430 { _MMIO(0x272c), 0xffffffff },
431 { _MMIO(0x2728), 0xffffffff },
432 { _MMIO(0x2724), 0xf0800000 },
433 { _MMIO(0x2720), 0x00000000 },
434 { _MMIO(0x271c), 0xffffffff },
435 { _MMIO(0x2718), 0xffffffff },
436 { _MMIO(0x2714), 0xf0800000 },
437 { _MMIO(0x2710), 0x00000000 },
438 { _MMIO(0x274c), 0x86543210 },
439 { _MMIO(0x2748), 0x86543210 },
440 { _MMIO(0x2744), 0x00006667 },
441 { _MMIO(0x2740), 0x00000000 },
442 { _MMIO(0x275c), 0x86543210 },
443 { _MMIO(0x2758), 0x86543210 },
444 { _MMIO(0x2754), 0x00006465 },
445 { _MMIO(0x2750), 0x00000000 },
446 { _MMIO(0x2770), 0x0007f81a },
447 { _MMIO(0x2774), 0x0000fe00 },
448 { _MMIO(0x2778), 0x0007f82a },
449 { _MMIO(0x277c), 0x0000fe00 },
450 { _MMIO(0x2780), 0x0007f872 },
451 { _MMIO(0x2784), 0x0000fe00 },
452 { _MMIO(0x2788), 0x0007f8ba },
453 { _MMIO(0x278c), 0x0000fe00 },
454 { _MMIO(0x2790), 0x0007f87a },
455 { _MMIO(0x2794), 0x0000fe00 },
456 { _MMIO(0x2798), 0x0007f8ea },
457 { _MMIO(0x279c), 0x0000fe00 },
458 { _MMIO(0x27a0), 0x0007f8e2 },
459 { _MMIO(0x27a4), 0x0000fe00 },
460 { _MMIO(0x27a8), 0x0007f8f2 },
461 { _MMIO(0x27ac), 0x0000fe00 },
462};
463
464static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
465 { _MMIO(0xe458), 0x00005004 },
466 { _MMIO(0xe558), 0x00015014 },
467 { _MMIO(0xe658), 0x00025024 },
468 { _MMIO(0xe758), 0x00035034 },
469 { _MMIO(0xe45c), 0x00045044 },
470 { _MMIO(0xe55c), 0x00055054 },
471 { _MMIO(0xe65c), 0x00065064 },
472};
473
474static const struct i915_oa_reg mux_config_memory_reads[] = {
475 { _MMIO(0x9888), 0x19800343 },
476 { _MMIO(0x9888), 0x39900340 },
477 { _MMIO(0x9888), 0x3f901000 },
478 { _MMIO(0x9888), 0x41900003 },
479 { _MMIO(0x9888), 0x03803180 },
480 { _MMIO(0x9888), 0x058035e2 },
481 { _MMIO(0x9888), 0x0780006a },
482 { _MMIO(0x9888), 0x11800000 },
483 { _MMIO(0x9888), 0x2181a000 },
484 { _MMIO(0x9888), 0x2381000a },
485 { _MMIO(0x9888), 0x1d950550 },
486 { _MMIO(0x9888), 0x0b928000 },
487 { _MMIO(0x9888), 0x0d92a000 },
488 { _MMIO(0x9888), 0x0f922000 },
489 { _MMIO(0x9888), 0x13900170 },
490 { _MMIO(0x9888), 0x21900171 },
491 { _MMIO(0x9888), 0x23900172 },
492 { _MMIO(0x9888), 0x25900173 },
493 { _MMIO(0x9888), 0x27900174 },
494 { _MMIO(0x9888), 0x29900175 },
495 { _MMIO(0x9888), 0x2b900176 },
496 { _MMIO(0x9888), 0x2d900177 },
497 { _MMIO(0x9888), 0x2f90017f },
498 { _MMIO(0x9888), 0x31900125 },
499 { _MMIO(0x9888), 0x15900123 },
500 { _MMIO(0x9888), 0x17900121 },
501 { _MMIO(0x9888), 0x35900000 },
502 { _MMIO(0x9888), 0x19908000 },
503 { _MMIO(0x9888), 0x1b908000 },
504 { _MMIO(0x9888), 0x1d908000 },
505 { _MMIO(0x9888), 0x1f908000 },
506 { _MMIO(0x9888), 0x53900000 },
507 { _MMIO(0x9888), 0x43901084 },
508 { _MMIO(0x9888), 0x55900000 },
509 { _MMIO(0x9888), 0x47901080 },
510 { _MMIO(0x9888), 0x57900000 },
511 { _MMIO(0x9888), 0x49901084 },
512 { _MMIO(0x9888), 0x59900000 },
513 { _MMIO(0x9888), 0x4b901084 },
514 { _MMIO(0x9888), 0x37900000 },
515 { _MMIO(0x9888), 0x33900000 },
516 { _MMIO(0x9888), 0x4d900004 },
517 { _MMIO(0x9888), 0x45900000 },
518};
519
520static int
521get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
522 const struct i915_oa_reg **regs,
523 int *lens)
524{
525 int n = 0;
526
527 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
528 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
529
530 regs[n] = mux_config_memory_reads;
531 lens[n] = ARRAY_SIZE(mux_config_memory_reads);
532 n++;
533
534 return n;
535}
536
537static const struct i915_oa_reg b_counter_config_memory_writes[] = {
538 { _MMIO(0x272c), 0xffffffff },
539 { _MMIO(0x2728), 0xffffffff },
540 { _MMIO(0x2724), 0xf0800000 },
541 { _MMIO(0x2720), 0x00000000 },
542 { _MMIO(0x271c), 0xffffffff },
543 { _MMIO(0x2718), 0xffffffff },
544 { _MMIO(0x2714), 0xf0800000 },
545 { _MMIO(0x2710), 0x00000000 },
546 { _MMIO(0x274c), 0x86543210 },
547 { _MMIO(0x2748), 0x86543210 },
548 { _MMIO(0x2744), 0x00006667 },
549 { _MMIO(0x2740), 0x00000000 },
550 { _MMIO(0x275c), 0x86543210 },
551 { _MMIO(0x2758), 0x86543210 },
552 { _MMIO(0x2754), 0x00006465 },
553 { _MMIO(0x2750), 0x00000000 },
554 { _MMIO(0x2770), 0x0007f81a },
555 { _MMIO(0x2774), 0x0000fe00 },
556 { _MMIO(0x2778), 0x0007f82a },
557 { _MMIO(0x277c), 0x0000fe00 },
558 { _MMIO(0x2780), 0x0007f822 },
559 { _MMIO(0x2784), 0x0000fe00 },
560 { _MMIO(0x2788), 0x0007f8ba },
561 { _MMIO(0x278c), 0x0000fe00 },
562 { _MMIO(0x2790), 0x0007f87a },
563 { _MMIO(0x2794), 0x0000fe00 },
564 { _MMIO(0x2798), 0x0007f8ea },
565 { _MMIO(0x279c), 0x0000fe00 },
566 { _MMIO(0x27a0), 0x0007f8e2 },
567 { _MMIO(0x27a4), 0x0000fe00 },
568 { _MMIO(0x27a8), 0x0007f8f2 },
569 { _MMIO(0x27ac), 0x0000fe00 },
570};
571
572static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
573 { _MMIO(0xe458), 0x00005004 },
574 { _MMIO(0xe558), 0x00015014 },
575 { _MMIO(0xe658), 0x00025024 },
576 { _MMIO(0xe758), 0x00035034 },
577 { _MMIO(0xe45c), 0x00045044 },
578 { _MMIO(0xe55c), 0x00055054 },
579 { _MMIO(0xe65c), 0x00065064 },
580};
581
582static const struct i915_oa_reg mux_config_memory_writes[] = {
583 { _MMIO(0x9888), 0x19800343 },
584 { _MMIO(0x9888), 0x39900340 },
585 { _MMIO(0x9888), 0x3f900000 },
586 { _MMIO(0x9888), 0x41900080 },
587 { _MMIO(0x9888), 0x03803180 },
588 { _MMIO(0x9888), 0x058035e2 },
589 { _MMIO(0x9888), 0x0780006a },
590 { _MMIO(0x9888), 0x11800000 },
591 { _MMIO(0x9888), 0x2181a000 },
592 { _MMIO(0x9888), 0x2381000a },
593 { _MMIO(0x9888), 0x1d950550 },
594 { _MMIO(0x9888), 0x0b928000 },
595 { _MMIO(0x9888), 0x0d92a000 },
596 { _MMIO(0x9888), 0x0f922000 },
597 { _MMIO(0x9888), 0x13900180 },
598 { _MMIO(0x9888), 0x21900181 },
599 { _MMIO(0x9888), 0x23900182 },
600 { _MMIO(0x9888), 0x25900183 },
601 { _MMIO(0x9888), 0x27900184 },
602 { _MMIO(0x9888), 0x29900185 },
603 { _MMIO(0x9888), 0x2b900186 },
604 { _MMIO(0x9888), 0x2d900187 },
605 { _MMIO(0x9888), 0x2f900170 },
606 { _MMIO(0x9888), 0x31900125 },
607 { _MMIO(0x9888), 0x15900123 },
608 { _MMIO(0x9888), 0x17900121 },
609 { _MMIO(0x9888), 0x35900000 },
610 { _MMIO(0x9888), 0x19908000 },
611 { _MMIO(0x9888), 0x1b908000 },
612 { _MMIO(0x9888), 0x1d908000 },
613 { _MMIO(0x9888), 0x1f908000 },
614 { _MMIO(0x9888), 0x53900000 },
615 { _MMIO(0x9888), 0x43901084 },
616 { _MMIO(0x9888), 0x55900000 },
617 { _MMIO(0x9888), 0x47901080 },
618 { _MMIO(0x9888), 0x57900000 },
619 { _MMIO(0x9888), 0x49901084 },
620 { _MMIO(0x9888), 0x59900000 },
621 { _MMIO(0x9888), 0x4b901084 },
622 { _MMIO(0x9888), 0x37900000 },
623 { _MMIO(0x9888), 0x33900000 },
624 { _MMIO(0x9888), 0x4d900004 },
625 { _MMIO(0x9888), 0x45900000 },
626};
627
628static int
629get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
630 const struct i915_oa_reg **regs,
631 int *lens)
632{
633 int n = 0;
634
635 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
636 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
637
638 regs[n] = mux_config_memory_writes;
639 lens[n] = ARRAY_SIZE(mux_config_memory_writes);
640 n++;
641
642 return n;
643}
644
645static const struct i915_oa_reg b_counter_config_compute_extended[] = {
646 { _MMIO(0x2724), 0xf0800000 },
647 { _MMIO(0x2720), 0x00000000 },
648 { _MMIO(0x2714), 0xf0800000 },
649 { _MMIO(0x2710), 0x00000000 },
650 { _MMIO(0x2740), 0x00000000 },
651 { _MMIO(0x2770), 0x0007fc2a },
652 { _MMIO(0x2774), 0x0000bf00 },
653 { _MMIO(0x2778), 0x0007fc6a },
654 { _MMIO(0x277c), 0x0000bf00 },
655 { _MMIO(0x2780), 0x0007fc92 },
656 { _MMIO(0x2784), 0x0000bf00 },
657 { _MMIO(0x2788), 0x0007fca2 },
658 { _MMIO(0x278c), 0x0000bf00 },
659 { _MMIO(0x2790), 0x0007fc32 },
660 { _MMIO(0x2794), 0x0000bf00 },
661 { _MMIO(0x2798), 0x0007fc9a },
662 { _MMIO(0x279c), 0x0000bf00 },
663 { _MMIO(0x27a0), 0x0007fe6a },
664 { _MMIO(0x27a4), 0x0000bf00 },
665 { _MMIO(0x27a8), 0x0007fe7a },
666 { _MMIO(0x27ac), 0x0000bf00 },
667};
668
669static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
670 { _MMIO(0xe458), 0x00005004 },
671 { _MMIO(0xe558), 0x00000003 },
672 { _MMIO(0xe658), 0x00002001 },
673 { _MMIO(0xe758), 0x00778008 },
674 { _MMIO(0xe45c), 0x00088078 },
675 { _MMIO(0xe55c), 0x00808708 },
676 { _MMIO(0xe65c), 0x00a08908 },
677};
678
679static const struct i915_oa_reg mux_config_compute_extended[] = {
680 { _MMIO(0x9888), 0x104f00e0 },
681 { _MMIO(0x9888), 0x141c0160 },
682 { _MMIO(0x9888), 0x161c0015 },
683 { _MMIO(0x9888), 0x181c0120 },
684 { _MMIO(0x9888), 0x002d5000 },
685 { _MMIO(0x9888), 0x062d4000 },
686 { _MMIO(0x9888), 0x082d5000 },
687 { _MMIO(0x9888), 0x0a2d5000 },
688 { _MMIO(0x9888), 0x0c2d5000 },
689 { _MMIO(0x9888), 0x0e2d5000 },
690 { _MMIO(0x9888), 0x022d5000 },
691 { _MMIO(0x9888), 0x042d5000 },
692 { _MMIO(0x9888), 0x0c2e5400 },
693 { _MMIO(0x9888), 0x0e2e5515 },
694 { _MMIO(0x9888), 0x102e0155 },
695 { _MMIO(0x9888), 0x044cc000 },
696 { _MMIO(0x9888), 0x0a4c8000 },
697 { _MMIO(0x9888), 0x0c4cc000 },
698 { _MMIO(0x9888), 0x0e4cc000 },
699 { _MMIO(0x9888), 0x104c8000 },
700 { _MMIO(0x9888), 0x124c8000 },
701 { _MMIO(0x9888), 0x144c8000 },
702 { _MMIO(0x9888), 0x164c2000 },
703 { _MMIO(0x9888), 0x064cc000 },
704 { _MMIO(0x9888), 0x084cc000 },
705 { _MMIO(0x9888), 0x004ea000 },
706 { _MMIO(0x9888), 0x064e8000 },
707 { _MMIO(0x9888), 0x084ea000 },
708 { _MMIO(0x9888), 0x0a4ea000 },
709 { _MMIO(0x9888), 0x0c4ea000 },
710 { _MMIO(0x9888), 0x0e4ea000 },
711 { _MMIO(0x9888), 0x024ea000 },
712 { _MMIO(0x9888), 0x044ea000 },
713 { _MMIO(0x9888), 0x0e4f4b41 },
714 { _MMIO(0x9888), 0x004f4200 },
715 { _MMIO(0x9888), 0x024f404c },
716 { _MMIO(0x9888), 0x1c4f0000 },
717 { _MMIO(0x9888), 0x1a4f0000 },
718 { _MMIO(0x9888), 0x001b4000 },
719 { _MMIO(0x9888), 0x061b8000 },
720 { _MMIO(0x9888), 0x081bc000 },
721 { _MMIO(0x9888), 0x0a1bc000 },
722 { _MMIO(0x9888), 0x0c1bc000 },
723 { _MMIO(0x9888), 0x041bc000 },
724 { _MMIO(0x9888), 0x001c0031 },
725 { _MMIO(0x9888), 0x061c1900 },
726 { _MMIO(0x9888), 0x081c1a33 },
727 { _MMIO(0x9888), 0x0a1c1b35 },
728 { _MMIO(0x9888), 0x0c1c3337 },
729 { _MMIO(0x9888), 0x041c31c7 },
730 { _MMIO(0x9888), 0x180f5000 },
731 { _MMIO(0x9888), 0x1a0fa8aa },
732 { _MMIO(0x9888), 0x1c0f0aaa },
733 { _MMIO(0x9888), 0x182c8000 },
734 { _MMIO(0x9888), 0x1c2c6aaa },
735 { _MMIO(0x9888), 0x1e2c0001 },
736 { _MMIO(0x9888), 0x1a2c2950 },
737 { _MMIO(0x9888), 0x01938000 },
738 { _MMIO(0x9888), 0x0f938000 },
739 { _MMIO(0x9888), 0x1993aaaa },
740 { _MMIO(0x9888), 0x03938000 },
741 { _MMIO(0x9888), 0x05938000 },
742 { _MMIO(0x9888), 0x07938000 },
743 { _MMIO(0x9888), 0x09938000 },
744 { _MMIO(0x9888), 0x0b938000 },
745 { _MMIO(0x9888), 0x13904000 },
746 { _MMIO(0x9888), 0x21904000 },
747 { _MMIO(0x9888), 0x23904000 },
748 { _MMIO(0x9888), 0x25904000 },
749 { _MMIO(0x9888), 0x27904000 },
750 { _MMIO(0x9888), 0x29904000 },
751 { _MMIO(0x9888), 0x2b904000 },
752 { _MMIO(0x9888), 0x2d904000 },
753 { _MMIO(0x9888), 0x2f904000 },
754 { _MMIO(0x9888), 0x31904000 },
755 { _MMIO(0x9888), 0x15904000 },
756 { _MMIO(0x9888), 0x17904000 },
757 { _MMIO(0x9888), 0x19904000 },
758 { _MMIO(0x9888), 0x1b904000 },
759 { _MMIO(0x9888), 0x1d904000 },
760 { _MMIO(0x9888), 0x53900000 },
761 { _MMIO(0x9888), 0x43900420 },
762 { _MMIO(0x9888), 0x55900000 },
763 { _MMIO(0x9888), 0x47900000 },
764 { _MMIO(0x9888), 0x57900000 },
765 { _MMIO(0x9888), 0x49900000 },
766 { _MMIO(0x9888), 0x59900000 },
767 { _MMIO(0x9888), 0x4b900400 },
768 { _MMIO(0x9888), 0x37900000 },
769 { _MMIO(0x9888), 0x33900000 },
770 { _MMIO(0x9888), 0x4d900001 },
771 { _MMIO(0x9888), 0x45900001 },
772};
773
774static int
775get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
776 const struct i915_oa_reg **regs,
777 int *lens)
778{
779 int n = 0;
780
781 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
782 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
783
784 regs[n] = mux_config_compute_extended;
785 lens[n] = ARRAY_SIZE(mux_config_compute_extended);
786 n++;
787
788 return n;
789}
790
791static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
792 { _MMIO(0x2710), 0x00000000 },
793 { _MMIO(0x2714), 0x30800000 },
794 { _MMIO(0x2720), 0x00000000 },
795 { _MMIO(0x2724), 0x30800000 },
796 { _MMIO(0x2740), 0x00000000 },
797 { _MMIO(0x2770), 0x0007fffa },
798 { _MMIO(0x2774), 0x0000fefe },
799 { _MMIO(0x2778), 0x0007fffa },
800 { _MMIO(0x277c), 0x0000fefd },
801 { _MMIO(0x2790), 0x0007fffa },
802 { _MMIO(0x2794), 0x0000fbef },
803 { _MMIO(0x2798), 0x0007fffa },
804 { _MMIO(0x279c), 0x0000fbdf },
805};
806
807static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
808 { _MMIO(0xe458), 0x00005004 },
809 { _MMIO(0xe558), 0x00000003 },
810 { _MMIO(0xe658), 0x00002001 },
811 { _MMIO(0xe758), 0x00101100 },
812 { _MMIO(0xe45c), 0x00201200 },
813 { _MMIO(0xe55c), 0x00301300 },
814 { _MMIO(0xe65c), 0x00401400 },
815};
816
817static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
818 { _MMIO(0x9888), 0x166c03b0 },
819 { _MMIO(0x9888), 0x1593001e },
820 { _MMIO(0x9888), 0x3f900c00 },
821 { _MMIO(0x9888), 0x41900000 },
822 { _MMIO(0x9888), 0x002d1000 },
823 { _MMIO(0x9888), 0x062d4000 },
824 { _MMIO(0x9888), 0x082d5000 },
825 { _MMIO(0x9888), 0x0e2d5000 },
826 { _MMIO(0x9888), 0x0c2e0400 },
827 { _MMIO(0x9888), 0x0e2e1500 },
828 { _MMIO(0x9888), 0x102e0140 },
829 { _MMIO(0x9888), 0x044c4000 },
830 { _MMIO(0x9888), 0x0a4c8000 },
831 { _MMIO(0x9888), 0x0c4cc000 },
832 { _MMIO(0x9888), 0x144c8000 },
833 { _MMIO(0x9888), 0x164c2000 },
834 { _MMIO(0x9888), 0x004e2000 },
835 { _MMIO(0x9888), 0x064e8000 },
836 { _MMIO(0x9888), 0x084ea000 },
837 { _MMIO(0x9888), 0x0e4ea000 },
838 { _MMIO(0x9888), 0x1a4f4001 },
839 { _MMIO(0x9888), 0x1c4f5005 },
840 { _MMIO(0x9888), 0x006c0051 },
841 { _MMIO(0x9888), 0x066c5000 },
842 { _MMIO(0x9888), 0x086c5c5d },
843 { _MMIO(0x9888), 0x0e6c5e5f },
844 { _MMIO(0x9888), 0x106c0000 },
845 { _MMIO(0x9888), 0x146c0000 },
846 { _MMIO(0x9888), 0x1a6c0000 },
847 { _MMIO(0x9888), 0x1c6c0000 },
848 { _MMIO(0x9888), 0x180f1000 },
849 { _MMIO(0x9888), 0x1a0fa800 },
850 { _MMIO(0x9888), 0x1c0f0a00 },
851 { _MMIO(0x9888), 0x182c4000 },
852 { _MMIO(0x9888), 0x1c2c4015 },
853 { _MMIO(0x9888), 0x1e2c0001 },
854 { _MMIO(0x9888), 0x03931980 },
855 { _MMIO(0x9888), 0x05930032 },
856 { _MMIO(0x9888), 0x11930000 },
857 { _MMIO(0x9888), 0x01938000 },
858 { _MMIO(0x9888), 0x0f938000 },
859 { _MMIO(0x9888), 0x1993a00a },
860 { _MMIO(0x9888), 0x07930000 },
861 { _MMIO(0x9888), 0x09930000 },
862 { _MMIO(0x9888), 0x1d900177 },
863 { _MMIO(0x9888), 0x1f900178 },
864 { _MMIO(0x9888), 0x35900000 },
865 { _MMIO(0x9888), 0x13904000 },
866 { _MMIO(0x9888), 0x21904000 },
867 { _MMIO(0x9888), 0x23904000 },
868 { _MMIO(0x9888), 0x25904000 },
869 { _MMIO(0x9888), 0x2f904000 },
870 { _MMIO(0x9888), 0x31904000 },
871 { _MMIO(0x9888), 0x19904000 },
872 { _MMIO(0x9888), 0x1b904000 },
873 { _MMIO(0x9888), 0x53901000 },
874 { _MMIO(0x9888), 0x43900000 },
875 { _MMIO(0x9888), 0x55900111 },
876 { _MMIO(0x9888), 0x47900001 },
877 { _MMIO(0x9888), 0x57900000 },
878 { _MMIO(0x9888), 0x49900000 },
879 { _MMIO(0x9888), 0x37900000 },
880 { _MMIO(0x9888), 0x33900000 },
881 { _MMIO(0x9888), 0x59900000 },
882 { _MMIO(0x9888), 0x4b900000 },
883 { _MMIO(0x9888), 0x4d900000 },
884 { _MMIO(0x9888), 0x45900400 },
885};
886
887static int
888get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
889 const struct i915_oa_reg **regs,
890 int *lens)
891{
892 int n = 0;
893
894 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
895 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
896
897 regs[n] = mux_config_compute_l3_cache;
898 lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache);
899 n++;
900
901 return n;
902}
903
904static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
905 { _MMIO(0x2740), 0x00000000 },
906 { _MMIO(0x2744), 0x00800000 },
907 { _MMIO(0x2710), 0x00000000 },
908 { _MMIO(0x2714), 0x10800000 },
909 { _MMIO(0x2720), 0x00000000 },
910 { _MMIO(0x2724), 0x00800000 },
911 { _MMIO(0x2770), 0x00000002 },
912 { _MMIO(0x2774), 0x0000fdff },
913};
914
915static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
916 { _MMIO(0xe458), 0x00005004 },
917 { _MMIO(0xe558), 0x00010003 },
918 { _MMIO(0xe658), 0x00012011 },
919 { _MMIO(0xe758), 0x00015014 },
920 { _MMIO(0xe45c), 0x00051050 },
921 { _MMIO(0xe55c), 0x00053052 },
922 { _MMIO(0xe65c), 0x00055054 },
923};
924
925static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
926 { _MMIO(0x9888), 0x104f0232 },
927 { _MMIO(0x9888), 0x124f4640 },
928 { _MMIO(0x9888), 0x11834400 },
929 { _MMIO(0x9888), 0x022d4000 },
930 { _MMIO(0x9888), 0x042d5000 },
931 { _MMIO(0x9888), 0x062d1000 },
932 { _MMIO(0x9888), 0x0e2e0055 },
933 { _MMIO(0x9888), 0x064c8000 },
934 { _MMIO(0x9888), 0x084cc000 },
935 { _MMIO(0x9888), 0x0a4c4000 },
936 { _MMIO(0x9888), 0x024e8000 },
937 { _MMIO(0x9888), 0x044ea000 },
938 { _MMIO(0x9888), 0x064e2000 },
939 { _MMIO(0x9888), 0x024f6100 },
940 { _MMIO(0x9888), 0x044f416b },
941 { _MMIO(0x9888), 0x064f004b },
942 { _MMIO(0x9888), 0x1a4f0000 },
943 { _MMIO(0x9888), 0x1a0f02a8 },
944 { _MMIO(0x9888), 0x1a2c5500 },
945 { _MMIO(0x9888), 0x0f808000 },
946 { _MMIO(0x9888), 0x25810020 },
947 { _MMIO(0x9888), 0x0f8305c0 },
948 { _MMIO(0x9888), 0x07938000 },
949 { _MMIO(0x9888), 0x09938000 },
950 { _MMIO(0x9888), 0x0b938000 },
951 { _MMIO(0x9888), 0x0d938000 },
952 { _MMIO(0x9888), 0x1f951000 },
953 { _MMIO(0x9888), 0x13920200 },
954 { _MMIO(0x9888), 0x31908000 },
955 { _MMIO(0x9888), 0x19904000 },
956 { _MMIO(0x9888), 0x1b904000 },
957 { _MMIO(0x9888), 0x1d904000 },
958 { _MMIO(0x9888), 0x1f904000 },
959 { _MMIO(0x9888), 0x37900000 },
960 { _MMIO(0x9888), 0x59900000 },
961 { _MMIO(0x9888), 0x4d900003 },
962 { _MMIO(0x9888), 0x53900000 },
963 { _MMIO(0x9888), 0x45900000 },
964 { _MMIO(0x9888), 0x55900000 },
965 { _MMIO(0x9888), 0x47900000 },
966 { _MMIO(0x9888), 0x33900000 },
967};
968
969static int
970get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
971 const struct i915_oa_reg **regs,
972 int *lens)
973{
974 int n = 0;
975
976 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
977 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
978
979 regs[n] = mux_config_hdc_and_sf;
980 lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf);
981 n++;
982
983 return n;
984}
985
986static const struct i915_oa_reg b_counter_config_l3_1[] = {
987 { _MMIO(0x2740), 0x00000000 },
988 { _MMIO(0x2744), 0x00800000 },
989 { _MMIO(0x2710), 0x00000000 },
990 { _MMIO(0x2714), 0xf0800000 },
991 { _MMIO(0x2720), 0x00000000 },
992 { _MMIO(0x2724), 0xf0800000 },
993 { _MMIO(0x2770), 0x00100070 },
994 { _MMIO(0x2774), 0x0000fff1 },
995 { _MMIO(0x2778), 0x00014002 },
996 { _MMIO(0x277c), 0x0000c3ff },
997 { _MMIO(0x2780), 0x00010002 },
998 { _MMIO(0x2784), 0x0000c7ff },
999 { _MMIO(0x2788), 0x00004002 },
1000 { _MMIO(0x278c), 0x0000d3ff },
1001 { _MMIO(0x2790), 0x00100700 },
1002 { _MMIO(0x2794), 0x0000ff1f },
1003 { _MMIO(0x2798), 0x00001402 },
1004 { _MMIO(0x279c), 0x0000fc3f },
1005 { _MMIO(0x27a0), 0x00001002 },
1006 { _MMIO(0x27a4), 0x0000fc7f },
1007 { _MMIO(0x27a8), 0x00000402 },
1008 { _MMIO(0x27ac), 0x0000fd3f },
1009};
1010
1011static const struct i915_oa_reg flex_eu_config_l3_1[] = {
1012 { _MMIO(0xe458), 0x00005004 },
1013 { _MMIO(0xe558), 0x00010003 },
1014 { _MMIO(0xe658), 0x00012011 },
1015 { _MMIO(0xe758), 0x00015014 },
1016 { _MMIO(0xe45c), 0x00051050 },
1017 { _MMIO(0xe55c), 0x00053052 },
1018 { _MMIO(0xe65c), 0x00055054 },
1019};
1020
1021static const struct i915_oa_reg mux_config_l3_1_0_sku_gte_0x03[] = {
1022 { _MMIO(0x9888), 0x12643400 },
1023 { _MMIO(0x9888), 0x12653400 },
1024 { _MMIO(0x9888), 0x106c6800 },
1025 { _MMIO(0x9888), 0x126c001e },
1026 { _MMIO(0x9888), 0x166c0010 },
1027 { _MMIO(0x9888), 0x0c2d5000 },
1028 { _MMIO(0x9888), 0x0e2d5000 },
1029 { _MMIO(0x9888), 0x002d4000 },
1030 { _MMIO(0x9888), 0x022d5000 },
1031 { _MMIO(0x9888), 0x042d5000 },
1032 { _MMIO(0x9888), 0x062d1000 },
1033 { _MMIO(0x9888), 0x102e0154 },
1034 { _MMIO(0x9888), 0x0c2e5000 },
1035 { _MMIO(0x9888), 0x0e2e0055 },
1036 { _MMIO(0x9888), 0x104c8000 },
1037 { _MMIO(0x9888), 0x124c8000 },
1038 { _MMIO(0x9888), 0x144c8000 },
1039 { _MMIO(0x9888), 0x164c2000 },
1040 { _MMIO(0x9888), 0x044c8000 },
1041 { _MMIO(0x9888), 0x064cc000 },
1042 { _MMIO(0x9888), 0x084cc000 },
1043 { _MMIO(0x9888), 0x0a4c4000 },
1044 { _MMIO(0x9888), 0x0c4ea000 },
1045 { _MMIO(0x9888), 0x0e4ea000 },
1046 { _MMIO(0x9888), 0x004e8000 },
1047 { _MMIO(0x9888), 0x024ea000 },
1048 { _MMIO(0x9888), 0x044ea000 },
1049 { _MMIO(0x9888), 0x064e2000 },
1050 { _MMIO(0x9888), 0x1c4f5500 },
1051 { _MMIO(0x9888), 0x1a4f1554 },
1052 { _MMIO(0x9888), 0x0a640024 },
1053 { _MMIO(0x9888), 0x10640000 },
1054 { _MMIO(0x9888), 0x04640000 },
1055 { _MMIO(0x9888), 0x0c650024 },
1056 { _MMIO(0x9888), 0x10650000 },
1057 { _MMIO(0x9888), 0x06650000 },
1058 { _MMIO(0x9888), 0x0c6c5327 },
1059 { _MMIO(0x9888), 0x0e6c5425 },
1060 { _MMIO(0x9888), 0x006c2a00 },
1061 { _MMIO(0x9888), 0x026c285b },
1062 { _MMIO(0x9888), 0x046c005c },
1063 { _MMIO(0x9888), 0x1c6c0000 },
1064 { _MMIO(0x9888), 0x1a6c0900 },
1065 { _MMIO(0x9888), 0x1c0f0aa0 },
1066 { _MMIO(0x9888), 0x180f4000 },
1067 { _MMIO(0x9888), 0x1a0f02aa },
1068 { _MMIO(0x9888), 0x1c2c5400 },
1069 { _MMIO(0x9888), 0x1e2c0001 },
1070 { _MMIO(0x9888), 0x1a2c5550 },
1071 { _MMIO(0x9888), 0x1993aa00 },
1072 { _MMIO(0x9888), 0x03938000 },
1073 { _MMIO(0x9888), 0x05938000 },
1074 { _MMIO(0x9888), 0x07938000 },
1075 { _MMIO(0x9888), 0x09938000 },
1076 { _MMIO(0x9888), 0x0b938000 },
1077 { _MMIO(0x9888), 0x0d938000 },
1078 { _MMIO(0x9888), 0x2b904000 },
1079 { _MMIO(0x9888), 0x2d904000 },
1080 { _MMIO(0x9888), 0x2f904000 },
1081 { _MMIO(0x9888), 0x31904000 },
1082 { _MMIO(0x9888), 0x15904000 },
1083 { _MMIO(0x9888), 0x17904000 },
1084 { _MMIO(0x9888), 0x19904000 },
1085 { _MMIO(0x9888), 0x1b904000 },
1086 { _MMIO(0x9888), 0x1d904000 },
1087 { _MMIO(0x9888), 0x1f904000 },
1088 { _MMIO(0x9888), 0x59900000 },
1089 { _MMIO(0x9888), 0x4b900421 },
1090 { _MMIO(0x9888), 0x37900000 },
1091 { _MMIO(0x9888), 0x33900000 },
1092 { _MMIO(0x9888), 0x4d900001 },
1093 { _MMIO(0x9888), 0x53900000 },
1094 { _MMIO(0x9888), 0x43900420 },
1095 { _MMIO(0x9888), 0x45900021 },
1096 { _MMIO(0x9888), 0x55900000 },
1097 { _MMIO(0x9888), 0x47900000 },
1098};
1099
1100static const struct i915_oa_reg mux_config_l3_1_0_sku_lt_0x03[] = {
1101 { _MMIO(0x9888), 0x14640340 },
1102 { _MMIO(0x9888), 0x14650340 },
1103 { _MMIO(0x9888), 0x106c6800 },
1104 { _MMIO(0x9888), 0x126c001e },
1105 { _MMIO(0x9888), 0x166c0010 },
1106 { _MMIO(0x9888), 0x0c2d5000 },
1107 { _MMIO(0x9888), 0x0e2d5000 },
1108 { _MMIO(0x9888), 0x002d4000 },
1109 { _MMIO(0x9888), 0x022d5000 },
1110 { _MMIO(0x9888), 0x042d5000 },
1111 { _MMIO(0x9888), 0x062d1000 },
1112 { _MMIO(0x9888), 0x102e0154 },
1113 { _MMIO(0x9888), 0x0c2e5000 },
1114 { _MMIO(0x9888), 0x0e2e0055 },
1115 { _MMIO(0x9888), 0x104c8000 },
1116 { _MMIO(0x9888), 0x124c8000 },
1117 { _MMIO(0x9888), 0x144c8000 },
1118 { _MMIO(0x9888), 0x164c2000 },
1119 { _MMIO(0x9888), 0x044c8000 },
1120 { _MMIO(0x9888), 0x064cc000 },
1121 { _MMIO(0x9888), 0x084cc000 },
1122 { _MMIO(0x9888), 0x0a4c4000 },
1123 { _MMIO(0x9888), 0x0c4ea000 },
1124 { _MMIO(0x9888), 0x0e4ea000 },
1125 { _MMIO(0x9888), 0x004e8000 },
1126 { _MMIO(0x9888), 0x024ea000 },
1127 { _MMIO(0x9888), 0x044ea000 },
1128 { _MMIO(0x9888), 0x064e2000 },
1129 { _MMIO(0x9888), 0x1c4f5500 },
1130 { _MMIO(0x9888), 0x1a4f1554 },
1131 { _MMIO(0x9888), 0x04642400 },
1132 { _MMIO(0x9888), 0x22640000 },
1133 { _MMIO(0x9888), 0x1a640000 },
1134 { _MMIO(0x9888), 0x06650024 },
1135 { _MMIO(0x9888), 0x22650000 },
1136 { _MMIO(0x9888), 0x1c650000 },
1137 { _MMIO(0x9888), 0x0c6c5327 },
1138 { _MMIO(0x9888), 0x0e6c5425 },
1139 { _MMIO(0x9888), 0x006c2a00 },
1140 { _MMIO(0x9888), 0x026c285b },
1141 { _MMIO(0x9888), 0x046c005c },
1142 { _MMIO(0x9888), 0x1c6c0000 },
1143 { _MMIO(0x9888), 0x1a6c0900 },
1144 { _MMIO(0x9888), 0x1c0f0aa0 },
1145 { _MMIO(0x9888), 0x180f4000 },
1146 { _MMIO(0x9888), 0x1a0f02aa },
1147 { _MMIO(0x9888), 0x1c2c5400 },
1148 { _MMIO(0x9888), 0x1e2c0001 },
1149 { _MMIO(0x9888), 0x1a2c5550 },
1150 { _MMIO(0x9888), 0x1993aa00 },
1151 { _MMIO(0x9888), 0x03938000 },
1152 { _MMIO(0x9888), 0x05938000 },
1153 { _MMIO(0x9888), 0x07938000 },
1154 { _MMIO(0x9888), 0x09938000 },
1155 { _MMIO(0x9888), 0x0b938000 },
1156 { _MMIO(0x9888), 0x0d938000 },
1157 { _MMIO(0x9888), 0x2b904000 },
1158 { _MMIO(0x9888), 0x2d904000 },
1159 { _MMIO(0x9888), 0x2f904000 },
1160 { _MMIO(0x9888), 0x31904000 },
1161 { _MMIO(0x9888), 0x15904000 },
1162 { _MMIO(0x9888), 0x17904000 },
1163 { _MMIO(0x9888), 0x19904000 },
1164 { _MMIO(0x9888), 0x1b904000 },
1165 { _MMIO(0x9888), 0x1d904000 },
1166 { _MMIO(0x9888), 0x1f904000 },
1167 { _MMIO(0x9888), 0x59900000 },
1168 { _MMIO(0x9888), 0x4b900421 },
1169 { _MMIO(0x9888), 0x37900000 },
1170 { _MMIO(0x9888), 0x33900000 },
1171 { _MMIO(0x9888), 0x4d900001 },
1172 { _MMIO(0x9888), 0x53900000 },
1173 { _MMIO(0x9888), 0x43900420 },
1174 { _MMIO(0x9888), 0x45900021 },
1175 { _MMIO(0x9888), 0x55900000 },
1176 { _MMIO(0x9888), 0x47900000 },
1177};
1178
1179static int
1180get_l3_1_mux_config(struct drm_i915_private *dev_priv,
1181 const struct i915_oa_reg **regs,
1182 int *lens)
1183{
1184 int n = 0;
1185
1186 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2);
1187 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2);
1188
1189 if (dev_priv->drm.pdev->revision >= 0x03) {
1190 regs[n] = mux_config_l3_1_0_sku_gte_0x03;
1191 lens[n] = ARRAY_SIZE(mux_config_l3_1_0_sku_gte_0x03);
1192 n++;
1193 }
1194 if (dev_priv->drm.pdev->revision < 0x03) {
1195 regs[n] = mux_config_l3_1_0_sku_lt_0x03;
1196 lens[n] = ARRAY_SIZE(mux_config_l3_1_0_sku_lt_0x03);
1197 n++;
1198 }
1199
1200 return n;
1201}
1202
1203static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
1204 { _MMIO(0x2740), 0x00000000 },
1205 { _MMIO(0x2744), 0x00800000 },
1206 { _MMIO(0x2710), 0x00000000 },
1207 { _MMIO(0x2714), 0x30800000 },
1208 { _MMIO(0x2720), 0x00000000 },
1209 { _MMIO(0x2724), 0x00800000 },
1210 { _MMIO(0x2770), 0x00000002 },
1211 { _MMIO(0x2774), 0x0000efff },
1212 { _MMIO(0x2778), 0x00006000 },
1213 { _MMIO(0x277c), 0x0000f3ff },
1214};
1215
1216static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
1217 { _MMIO(0xe458), 0x00005004 },
1218 { _MMIO(0xe558), 0x00010003 },
1219 { _MMIO(0xe658), 0x00012011 },
1220 { _MMIO(0xe758), 0x00015014 },
1221 { _MMIO(0xe45c), 0x00051050 },
1222 { _MMIO(0xe55c), 0x00053052 },
1223 { _MMIO(0xe65c), 0x00055054 },
1224};
1225
1226static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
1227 { _MMIO(0x9888), 0x102d7800 },
1228 { _MMIO(0x9888), 0x122d79e0 },
1229 { _MMIO(0x9888), 0x0c2f0004 },
1230 { _MMIO(0x9888), 0x100e3800 },
1231 { _MMIO(0x9888), 0x180f0005 },
1232 { _MMIO(0x9888), 0x002d0940 },
1233 { _MMIO(0x9888), 0x022d802f },
1234 { _MMIO(0x9888), 0x042d4013 },
1235 { _MMIO(0x9888), 0x062d1000 },
1236 { _MMIO(0x9888), 0x0e2e0050 },
1237 { _MMIO(0x9888), 0x022f0010 },
1238 { _MMIO(0x9888), 0x002f0000 },
1239 { _MMIO(0x9888), 0x084c8000 },
1240 { _MMIO(0x9888), 0x0a4c4000 },
1241 { _MMIO(0x9888), 0x044e8000 },
1242 { _MMIO(0x9888), 0x064e2000 },
1243 { _MMIO(0x9888), 0x040e0480 },
1244 { _MMIO(0x9888), 0x000e0000 },
1245 { _MMIO(0x9888), 0x060f0027 },
1246 { _MMIO(0x9888), 0x100f0000 },
1247 { _MMIO(0x9888), 0x1a0f0040 },
1248 { _MMIO(0x9888), 0x03938000 },
1249 { _MMIO(0x9888), 0x05938000 },
1250 { _MMIO(0x9888), 0x07938000 },
1251 { _MMIO(0x9888), 0x09938000 },
1252 { _MMIO(0x9888), 0x0b938000 },
1253 { _MMIO(0x9888), 0x0d938000 },
1254 { _MMIO(0x9888), 0x15904000 },
1255 { _MMIO(0x9888), 0x17904000 },
1256 { _MMIO(0x9888), 0x19904000 },
1257 { _MMIO(0x9888), 0x1b904000 },
1258 { _MMIO(0x9888), 0x1d904000 },
1259 { _MMIO(0x9888), 0x1f904000 },
1260 { _MMIO(0x9888), 0x37900000 },
1261 { _MMIO(0x9888), 0x53900000 },
1262 { _MMIO(0x9888), 0x439014a0 },
1263 { _MMIO(0x9888), 0x459000a4 },
1264 { _MMIO(0x9888), 0x55900000 },
1265 { _MMIO(0x9888), 0x47900001 },
1266 { _MMIO(0x9888), 0x33900000 },
1267};
1268
1269static int
1270get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
1271 const struct i915_oa_reg **regs,
1272 int *lens)
1273{
1274 int n = 0;
1275
1276 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1277 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1278
1279 regs[n] = mux_config_rasterizer_and_pixel_backend;
1280 lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
1281 n++;
1282
1283 return n;
1284}
1285
1286static const struct i915_oa_reg b_counter_config_sampler[] = {
1287 { _MMIO(0x2740), 0x00000000 },
1288 { _MMIO(0x2744), 0x00800000 },
1289 { _MMIO(0x2710), 0x00000000 },
1290 { _MMIO(0x2714), 0x70800000 },
1291 { _MMIO(0x2720), 0x00000000 },
1292 { _MMIO(0x2724), 0x00800000 },
1293 { _MMIO(0x2770), 0x0000c000 },
1294 { _MMIO(0x2774), 0x0000e7ff },
1295 { _MMIO(0x2778), 0x00003000 },
1296 { _MMIO(0x277c), 0x0000f9ff },
1297 { _MMIO(0x2780), 0x00000c00 },
1298 { _MMIO(0x2784), 0x0000fe7f },
1299};
1300
1301static const struct i915_oa_reg flex_eu_config_sampler[] = {
1302 { _MMIO(0xe458), 0x00005004 },
1303 { _MMIO(0xe558), 0x00010003 },
1304 { _MMIO(0xe658), 0x00012011 },
1305 { _MMIO(0xe758), 0x00015014 },
1306 { _MMIO(0xe45c), 0x00051050 },
1307 { _MMIO(0xe55c), 0x00053052 },
1308 { _MMIO(0xe65c), 0x00055054 },
1309};
1310
1311static const struct i915_oa_reg mux_config_sampler[] = {
1312 { _MMIO(0x9888), 0x121300a0 },
1313 { _MMIO(0x9888), 0x141600ab },
1314 { _MMIO(0x9888), 0x123300a0 },
1315 { _MMIO(0x9888), 0x143600ab },
1316 { _MMIO(0x9888), 0x125300a0 },
1317 { _MMIO(0x9888), 0x145600ab },
1318 { _MMIO(0x9888), 0x0c2d4000 },
1319 { _MMIO(0x9888), 0x0e2d5000 },
1320 { _MMIO(0x9888), 0x002d4000 },
1321 { _MMIO(0x9888), 0x022d5000 },
1322 { _MMIO(0x9888), 0x042d5000 },
1323 { _MMIO(0x9888), 0x062d1000 },
1324 { _MMIO(0x9888), 0x102e01a0 },
1325 { _MMIO(0x9888), 0x0c2e5000 },
1326 { _MMIO(0x9888), 0x0e2e0065 },
1327 { _MMIO(0x9888), 0x164c2000 },
1328 { _MMIO(0x9888), 0x044c8000 },
1329 { _MMIO(0x9888), 0x064cc000 },
1330 { _MMIO(0x9888), 0x084c4000 },
1331 { _MMIO(0x9888), 0x0a4c4000 },
1332 { _MMIO(0x9888), 0x0e4e8000 },
1333 { _MMIO(0x9888), 0x004e8000 },
1334 { _MMIO(0x9888), 0x024ea000 },
1335 { _MMIO(0x9888), 0x044e2000 },
1336 { _MMIO(0x9888), 0x064e2000 },
1337 { _MMIO(0x9888), 0x1c0f0800 },
1338 { _MMIO(0x9888), 0x180f4000 },
1339 { _MMIO(0x9888), 0x1a0f023f },
1340 { _MMIO(0x9888), 0x1e2c0003 },
1341 { _MMIO(0x9888), 0x1a2cc030 },
1342 { _MMIO(0x9888), 0x04132180 },
1343 { _MMIO(0x9888), 0x02130000 },
1344 { _MMIO(0x9888), 0x0c148000 },
1345 { _MMIO(0x9888), 0x0e142000 },
1346 { _MMIO(0x9888), 0x04148000 },
1347 { _MMIO(0x9888), 0x1e150140 },
1348 { _MMIO(0x9888), 0x1c150040 },
1349 { _MMIO(0x9888), 0x0c163000 },
1350 { _MMIO(0x9888), 0x0e160068 },
1351 { _MMIO(0x9888), 0x10160000 },
1352 { _MMIO(0x9888), 0x18160000 },
1353 { _MMIO(0x9888), 0x0a164000 },
1354 { _MMIO(0x9888), 0x04330043 },
1355 { _MMIO(0x9888), 0x02330000 },
1356 { _MMIO(0x9888), 0x0234a000 },
1357 { _MMIO(0x9888), 0x04342000 },
1358 { _MMIO(0x9888), 0x1c350015 },
1359 { _MMIO(0x9888), 0x02363460 },
1360 { _MMIO(0x9888), 0x10360000 },
1361 { _MMIO(0x9888), 0x04360000 },
1362 { _MMIO(0x9888), 0x06360000 },
1363 { _MMIO(0x9888), 0x08364000 },
1364 { _MMIO(0x9888), 0x06530043 },
1365 { _MMIO(0x9888), 0x02530000 },
1366 { _MMIO(0x9888), 0x0e548000 },
1367 { _MMIO(0x9888), 0x00548000 },
1368 { _MMIO(0x9888), 0x06542000 },
1369 { _MMIO(0x9888), 0x1e550400 },
1370 { _MMIO(0x9888), 0x1a552000 },
1371 { _MMIO(0x9888), 0x1c550100 },
1372 { _MMIO(0x9888), 0x0e563000 },
1373 { _MMIO(0x9888), 0x00563400 },
1374 { _MMIO(0x9888), 0x10560000 },
1375 { _MMIO(0x9888), 0x18560000 },
1376 { _MMIO(0x9888), 0x02560000 },
1377 { _MMIO(0x9888), 0x0c564000 },
1378 { _MMIO(0x9888), 0x1993a800 },
1379 { _MMIO(0x9888), 0x03938000 },
1380 { _MMIO(0x9888), 0x05938000 },
1381 { _MMIO(0x9888), 0x07938000 },
1382 { _MMIO(0x9888), 0x09938000 },
1383 { _MMIO(0x9888), 0x0b938000 },
1384 { _MMIO(0x9888), 0x0d938000 },
1385 { _MMIO(0x9888), 0x2d904000 },
1386 { _MMIO(0x9888), 0x2f904000 },
1387 { _MMIO(0x9888), 0x31904000 },
1388 { _MMIO(0x9888), 0x15904000 },
1389 { _MMIO(0x9888), 0x17904000 },
1390 { _MMIO(0x9888), 0x19904000 },
1391 { _MMIO(0x9888), 0x1b904000 },
1392 { _MMIO(0x9888), 0x1d904000 },
1393 { _MMIO(0x9888), 0x1f904000 },
1394 { _MMIO(0x9888), 0x59900000 },
1395 { _MMIO(0x9888), 0x4b9014a0 },
1396 { _MMIO(0x9888), 0x37900000 },
1397 { _MMIO(0x9888), 0x33900000 },
1398 { _MMIO(0x9888), 0x4d900001 },
1399 { _MMIO(0x9888), 0x53900000 },
1400 { _MMIO(0x9888), 0x43900820 },
1401 { _MMIO(0x9888), 0x45901022 },
1402 { _MMIO(0x9888), 0x55900000 },
1403 { _MMIO(0x9888), 0x47900000 },
1404};
1405
1406static int
1407get_sampler_mux_config(struct drm_i915_private *dev_priv,
1408 const struct i915_oa_reg **regs,
1409 int *lens)
1410{
1411 int n = 0;
1412
1413 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1414 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1415
1416 regs[n] = mux_config_sampler;
1417 lens[n] = ARRAY_SIZE(mux_config_sampler);
1418 n++;
1419
1420 return n;
1421}
1422
1423static const struct i915_oa_reg b_counter_config_tdl_1[] = {
1424 { _MMIO(0x2740), 0x00000000 },
1425 { _MMIO(0x2744), 0x00800000 },
1426 { _MMIO(0x2710), 0x00000000 },
1427 { _MMIO(0x2714), 0xf0800000 },
1428 { _MMIO(0x2720), 0x00000000 },
1429 { _MMIO(0x2724), 0x30800000 },
1430 { _MMIO(0x2770), 0x00000002 },
1431 { _MMIO(0x2774), 0x00007fff },
1432 { _MMIO(0x2778), 0x00000000 },
1433 { _MMIO(0x277c), 0x00009fff },
1434 { _MMIO(0x2780), 0x00000002 },
1435 { _MMIO(0x2784), 0x0000efff },
1436 { _MMIO(0x2788), 0x00000000 },
1437 { _MMIO(0x278c), 0x0000f3ff },
1438 { _MMIO(0x2790), 0x00000002 },
1439 { _MMIO(0x2794), 0x0000fdff },
1440 { _MMIO(0x2798), 0x00000000 },
1441 { _MMIO(0x279c), 0x0000fe7f },
1442};
1443
1444static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
1445 { _MMIO(0xe458), 0x00005004 },
1446 { _MMIO(0xe558), 0x00010003 },
1447 { _MMIO(0xe658), 0x00012011 },
1448 { _MMIO(0xe758), 0x00015014 },
1449 { _MMIO(0xe45c), 0x00051050 },
1450 { _MMIO(0xe55c), 0x00053052 },
1451 { _MMIO(0xe65c), 0x00055054 },
1452};
1453
1454static const struct i915_oa_reg mux_config_tdl_1[] = {
1455 { _MMIO(0x9888), 0x141a0000 },
1456 { _MMIO(0x9888), 0x143a0000 },
1457 { _MMIO(0x9888), 0x145a0000 },
1458 { _MMIO(0x9888), 0x0c2d4000 },
1459 { _MMIO(0x9888), 0x0e2d5000 },
1460 { _MMIO(0x9888), 0x002d4000 },
1461 { _MMIO(0x9888), 0x022d5000 },
1462 { _MMIO(0x9888), 0x042d5000 },
1463 { _MMIO(0x9888), 0x062d1000 },
1464 { _MMIO(0x9888), 0x102e0150 },
1465 { _MMIO(0x9888), 0x0c2e5000 },
1466 { _MMIO(0x9888), 0x0e2e006a },
1467 { _MMIO(0x9888), 0x124c8000 },
1468 { _MMIO(0x9888), 0x144c8000 },
1469 { _MMIO(0x9888), 0x164c2000 },
1470 { _MMIO(0x9888), 0x044c8000 },
1471 { _MMIO(0x9888), 0x064c4000 },
1472 { _MMIO(0x9888), 0x0a4c4000 },
1473 { _MMIO(0x9888), 0x0c4e8000 },
1474 { _MMIO(0x9888), 0x0e4ea000 },
1475 { _MMIO(0x9888), 0x004e8000 },
1476 { _MMIO(0x9888), 0x024e2000 },
1477 { _MMIO(0x9888), 0x064e2000 },
1478 { _MMIO(0x9888), 0x1c0f0bc0 },
1479 { _MMIO(0x9888), 0x180f4000 },
1480 { _MMIO(0x9888), 0x1a0f0302 },
1481 { _MMIO(0x9888), 0x1e2c0003 },
1482 { _MMIO(0x9888), 0x1a2c00f0 },
1483 { _MMIO(0x9888), 0x021a3080 },
1484 { _MMIO(0x9888), 0x041a31e5 },
1485 { _MMIO(0x9888), 0x02148000 },
1486 { _MMIO(0x9888), 0x0414a000 },
1487 { _MMIO(0x9888), 0x1c150054 },
1488 { _MMIO(0x9888), 0x06168000 },
1489 { _MMIO(0x9888), 0x08168000 },
1490 { _MMIO(0x9888), 0x0a168000 },
1491 { _MMIO(0x9888), 0x0c3a3280 },
1492 { _MMIO(0x9888), 0x0e3a0063 },
1493 { _MMIO(0x9888), 0x063a0061 },
1494 { _MMIO(0x9888), 0x023a0000 },
1495 { _MMIO(0x9888), 0x0c348000 },
1496 { _MMIO(0x9888), 0x0e342000 },
1497 { _MMIO(0x9888), 0x06342000 },
1498 { _MMIO(0x9888), 0x1e350140 },
1499 { _MMIO(0x9888), 0x1c350100 },
1500 { _MMIO(0x9888), 0x18360028 },
1501 { _MMIO(0x9888), 0x0c368000 },
1502 { _MMIO(0x9888), 0x0e5a3080 },
1503 { _MMIO(0x9888), 0x005a3280 },
1504 { _MMIO(0x9888), 0x025a0063 },
1505 { _MMIO(0x9888), 0x0e548000 },
1506 { _MMIO(0x9888), 0x00548000 },
1507 { _MMIO(0x9888), 0x02542000 },
1508 { _MMIO(0x9888), 0x1e550400 },
1509 { _MMIO(0x9888), 0x1a552000 },
1510 { _MMIO(0x9888), 0x1c550001 },
1511 { _MMIO(0x9888), 0x18560080 },
1512 { _MMIO(0x9888), 0x02568000 },
1513 { _MMIO(0x9888), 0x04568000 },
1514 { _MMIO(0x9888), 0x1993a800 },
1515 { _MMIO(0x9888), 0x03938000 },
1516 { _MMIO(0x9888), 0x05938000 },
1517 { _MMIO(0x9888), 0x07938000 },
1518 { _MMIO(0x9888), 0x09938000 },
1519 { _MMIO(0x9888), 0x0b938000 },
1520 { _MMIO(0x9888), 0x0d938000 },
1521 { _MMIO(0x9888), 0x2d904000 },
1522 { _MMIO(0x9888), 0x2f904000 },
1523 { _MMIO(0x9888), 0x31904000 },
1524 { _MMIO(0x9888), 0x15904000 },
1525 { _MMIO(0x9888), 0x17904000 },
1526 { _MMIO(0x9888), 0x19904000 },
1527 { _MMIO(0x9888), 0x1b904000 },
1528 { _MMIO(0x9888), 0x1d904000 },
1529 { _MMIO(0x9888), 0x1f904000 },
1530 { _MMIO(0x9888), 0x59900000 },
1531 { _MMIO(0x9888), 0x4b900420 },
1532 { _MMIO(0x9888), 0x37900000 },
1533 { _MMIO(0x9888), 0x33900000 },
1534 { _MMIO(0x9888), 0x4d900000 },
1535 { _MMIO(0x9888), 0x53900000 },
1536 { _MMIO(0x9888), 0x43900000 },
1537 { _MMIO(0x9888), 0x45901084 },
1538 { _MMIO(0x9888), 0x55900000 },
1539 { _MMIO(0x9888), 0x47900001 },
1540};
1541
1542static int
1543get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
1544 const struct i915_oa_reg **regs,
1545 int *lens)
1546{
1547 int n = 0;
1548
1549 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1550 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1551
1552 regs[n] = mux_config_tdl_1;
1553 lens[n] = ARRAY_SIZE(mux_config_tdl_1);
1554 n++;
1555
1556 return n;
1557}
1558
1559static const struct i915_oa_reg b_counter_config_tdl_2[] = {
1560 { _MMIO(0x2740), 0x00000000 },
1561 { _MMIO(0x2744), 0x00800000 },
1562 { _MMIO(0x2710), 0x00000000 },
1563 { _MMIO(0x2714), 0x00800000 },
1564 { _MMIO(0x2720), 0x00000000 },
1565 { _MMIO(0x2724), 0x00800000 },
1566};
1567
1568static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
1569 { _MMIO(0xe458), 0x00005004 },
1570 { _MMIO(0xe558), 0x00010003 },
1571 { _MMIO(0xe658), 0x00012011 },
1572 { _MMIO(0xe758), 0x00015014 },
1573 { _MMIO(0xe45c), 0x00051050 },
1574 { _MMIO(0xe55c), 0x00053052 },
1575 { _MMIO(0xe65c), 0x00055054 },
1576};
1577
1578static const struct i915_oa_reg mux_config_tdl_2[] = {
1579 { _MMIO(0x9888), 0x141a026b },
1580 { _MMIO(0x9888), 0x143a0173 },
1581 { _MMIO(0x9888), 0x145a026b },
1582 { _MMIO(0x9888), 0x002d4000 },
1583 { _MMIO(0x9888), 0x022d5000 },
1584 { _MMIO(0x9888), 0x042d5000 },
1585 { _MMIO(0x9888), 0x062d1000 },
1586 { _MMIO(0x9888), 0x0c2e5000 },
1587 { _MMIO(0x9888), 0x0e2e0069 },
1588 { _MMIO(0x9888), 0x044c8000 },
1589 { _MMIO(0x9888), 0x064cc000 },
1590 { _MMIO(0x9888), 0x0a4c4000 },
1591 { _MMIO(0x9888), 0x004e8000 },
1592 { _MMIO(0x9888), 0x024ea000 },
1593 { _MMIO(0x9888), 0x064e2000 },
1594 { _MMIO(0x9888), 0x180f6000 },
1595 { _MMIO(0x9888), 0x1a0f030a },
1596 { _MMIO(0x9888), 0x1a2c03c0 },
1597 { _MMIO(0x9888), 0x041a37e7 },
1598 { _MMIO(0x9888), 0x021a0000 },
1599 { _MMIO(0x9888), 0x0414a000 },
1600 { _MMIO(0x9888), 0x1c150050 },
1601 { _MMIO(0x9888), 0x08168000 },
1602 { _MMIO(0x9888), 0x0a168000 },
1603 { _MMIO(0x9888), 0x003a3380 },
1604 { _MMIO(0x9888), 0x063a006f },
1605 { _MMIO(0x9888), 0x023a0000 },
1606 { _MMIO(0x9888), 0x00348000 },
1607 { _MMIO(0x9888), 0x06342000 },
1608 { _MMIO(0x9888), 0x1a352000 },
1609 { _MMIO(0x9888), 0x1c350100 },
1610 { _MMIO(0x9888), 0x02368000 },
1611 { _MMIO(0x9888), 0x0c368000 },
1612 { _MMIO(0x9888), 0x025a37e7 },
1613 { _MMIO(0x9888), 0x0254a000 },
1614 { _MMIO(0x9888), 0x1c550005 },
1615 { _MMIO(0x9888), 0x04568000 },
1616 { _MMIO(0x9888), 0x06568000 },
1617 { _MMIO(0x9888), 0x03938000 },
1618 { _MMIO(0x9888), 0x05938000 },
1619 { _MMIO(0x9888), 0x07938000 },
1620 { _MMIO(0x9888), 0x09938000 },
1621 { _MMIO(0x9888), 0x0b938000 },
1622 { _MMIO(0x9888), 0x0d938000 },
1623 { _MMIO(0x9888), 0x15904000 },
1624 { _MMIO(0x9888), 0x17904000 },
1625 { _MMIO(0x9888), 0x19904000 },
1626 { _MMIO(0x9888), 0x1b904000 },
1627 { _MMIO(0x9888), 0x1d904000 },
1628 { _MMIO(0x9888), 0x1f904000 },
1629 { _MMIO(0x9888), 0x37900000 },
1630 { _MMIO(0x9888), 0x53900000 },
1631 { _MMIO(0x9888), 0x43900020 },
1632 { _MMIO(0x9888), 0x45901080 },
1633 { _MMIO(0x9888), 0x55900000 },
1634 { _MMIO(0x9888), 0x47900001 },
1635 { _MMIO(0x9888), 0x33900000 },
1636};
1637
1638static int
1639get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
1640 const struct i915_oa_reg **regs,
1641 int *lens)
1642{
1643 int n = 0;
1644
1645 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1646 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1647
1648 regs[n] = mux_config_tdl_2;
1649 lens[n] = ARRAY_SIZE(mux_config_tdl_2);
1650 n++;
1651
1652 return n;
1653}
1654
1655static const struct i915_oa_reg b_counter_config_compute_extra[] = {
1656 { _MMIO(0x2740), 0x00000000 },
1657 { _MMIO(0x2744), 0x00800000 },
1658 { _MMIO(0x2710), 0x00000000 },
1659 { _MMIO(0x2714), 0x00800000 },
1660 { _MMIO(0x2720), 0x00000000 },
1661 { _MMIO(0x2724), 0x00800000 },
1662};
1663
1664static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
1665 { _MMIO(0xe458), 0x00001000 },
1666 { _MMIO(0xe558), 0x00003002 },
1667 { _MMIO(0xe658), 0x00005004 },
1668 { _MMIO(0xe758), 0x00011010 },
1669 { _MMIO(0xe45c), 0x00050012 },
1670 { _MMIO(0xe55c), 0x00052051 },
1671 { _MMIO(0xe65c), 0x00000008 },
1672};
1673
1674static const struct i915_oa_reg mux_config_compute_extra[] = {
1675 { _MMIO(0x9888), 0x141a001f },
1676 { _MMIO(0x9888), 0x143a001f },
1677 { _MMIO(0x9888), 0x145a001f },
1678 { _MMIO(0x9888), 0x042d5000 },
1679 { _MMIO(0x9888), 0x062d1000 },
1680 { _MMIO(0x9888), 0x0e2e0094 },
1681 { _MMIO(0x9888), 0x084cc000 },
1682 { _MMIO(0x9888), 0x044ea000 },
1683 { _MMIO(0x9888), 0x1a0f00e0 },
1684 { _MMIO(0x9888), 0x1a2c0c00 },
1685 { _MMIO(0x9888), 0x061a0063 },
1686 { _MMIO(0x9888), 0x021a0000 },
1687 { _MMIO(0x9888), 0x06142000 },
1688 { _MMIO(0x9888), 0x1c150100 },
1689 { _MMIO(0x9888), 0x0c168000 },
1690 { _MMIO(0x9888), 0x043a3180 },
1691 { _MMIO(0x9888), 0x023a0000 },
1692 { _MMIO(0x9888), 0x04348000 },
1693 { _MMIO(0x9888), 0x1c350040 },
1694 { _MMIO(0x9888), 0x0a368000 },
1695 { _MMIO(0x9888), 0x045a0063 },
1696 { _MMIO(0x9888), 0x025a0000 },
1697 { _MMIO(0x9888), 0x04542000 },
1698 { _MMIO(0x9888), 0x1c550010 },
1699 { _MMIO(0x9888), 0x08568000 },
1700 { _MMIO(0x9888), 0x09938000 },
1701 { _MMIO(0x9888), 0x0b938000 },
1702 { _MMIO(0x9888), 0x0d938000 },
1703 { _MMIO(0x9888), 0x1b904000 },
1704 { _MMIO(0x9888), 0x1d904000 },
1705 { _MMIO(0x9888), 0x1f904000 },
1706 { _MMIO(0x9888), 0x37900000 },
1707 { _MMIO(0x9888), 0x55900000 },
1708 { _MMIO(0x9888), 0x45900400 },
1709 { _MMIO(0x9888), 0x47900004 },
1710 { _MMIO(0x9888), 0x33900000 },
1711};
1712
1713static int
1714get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
1715 const struct i915_oa_reg **regs,
1716 int *lens)
1717{
1718 int n = 0;
1719
1720 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1721 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1722
1723 regs[n] = mux_config_compute_extra;
1724 lens[n] = ARRAY_SIZE(mux_config_compute_extra);
1725 n++;
1726
1727 return n;
1728}
1729
1730static const struct i915_oa_reg b_counter_config_test_oa[] = {
1731 { _MMIO(0x2740), 0x00000000 },
1732 { _MMIO(0x2744), 0x00800000 },
1733 { _MMIO(0x2714), 0xf0800000 },
1734 { _MMIO(0x2710), 0x00000000 },
1735 { _MMIO(0x2724), 0xf0800000 },
1736 { _MMIO(0x2720), 0x00000000 },
1737 { _MMIO(0x2770), 0x00000004 },
1738 { _MMIO(0x2774), 0x00000000 },
1739 { _MMIO(0x2778), 0x00000003 },
1740 { _MMIO(0x277c), 0x00000000 },
1741 { _MMIO(0x2780), 0x00000007 },
1742 { _MMIO(0x2784), 0x00000000 },
1743 { _MMIO(0x2788), 0x00100002 },
1744 { _MMIO(0x278c), 0x0000fff7 },
1745 { _MMIO(0x2790), 0x00100002 },
1746 { _MMIO(0x2794), 0x0000ffcf },
1747 { _MMIO(0x2798), 0x00100082 },
1748 { _MMIO(0x279c), 0x0000ffef },
1749 { _MMIO(0x27a0), 0x001000c2 },
1750 { _MMIO(0x27a4), 0x0000ffe7 },
1751 { _MMIO(0x27a8), 0x00100001 },
1752 { _MMIO(0x27ac), 0x0000ffe7 },
1753};
1754
1755static const struct i915_oa_reg flex_eu_config_test_oa[] = {
1756};
1757
1758static const struct i915_oa_reg mux_config_test_oa[] = {
1759 { _MMIO(0x9888), 0x19800000 },
1760 { _MMIO(0x9888), 0x07800063 },
1761 { _MMIO(0x9888), 0x11800000 },
1762 { _MMIO(0x9888), 0x23810008 },
1763 { _MMIO(0x9888), 0x1d950400 },
1764 { _MMIO(0x9888), 0x0f922000 },
1765 { _MMIO(0x9888), 0x1f908000 },
1766 { _MMIO(0x9888), 0x37900000 },
1767 { _MMIO(0x9888), 0x55900000 },
1768 { _MMIO(0x9888), 0x47900000 },
1769 { _MMIO(0x9888), 0x33900000 },
1770};
1771
1772static int
1773get_test_oa_mux_config(struct drm_i915_private *dev_priv,
1774 const struct i915_oa_reg **regs,
1775 int *lens)
1776{
1777 int n = 0;
1778
1779 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1780 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1781
1782 regs[n] = mux_config_test_oa;
1783 lens[n] = ARRAY_SIZE(mux_config_test_oa);
1784 n++;
1785
1786 return n;
1787}
1788
1789int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv)
1790{
1791 dev_priv->perf.oa.n_mux_configs = 0;
1792 dev_priv->perf.oa.b_counter_regs = NULL;
1793 dev_priv->perf.oa.b_counter_regs_len = 0;
1794 dev_priv->perf.oa.flex_regs = NULL;
1795 dev_priv->perf.oa.flex_regs_len = 0;
1796
1797 switch (dev_priv->perf.oa.metrics_set) {
1798 case METRIC_SET_ID_RENDER_BASIC:
1799 dev_priv->perf.oa.n_mux_configs =
1800 get_render_basic_mux_config(dev_priv,
1801 dev_priv->perf.oa.mux_regs,
1802 dev_priv->perf.oa.mux_regs_lens);
1803 if (dev_priv->perf.oa.n_mux_configs == 0) {
1804 DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
1805
1806 /* EINVAL because *_register_sysfs already checked this
1807 * and so it wouldn't have been advertised to userspace and
1808 * so shouldn't have been requested
1809 */
1810 return -EINVAL;
1811 }
1812
1813 dev_priv->perf.oa.b_counter_regs =
1814 b_counter_config_render_basic;
1815 dev_priv->perf.oa.b_counter_regs_len =
1816 ARRAY_SIZE(b_counter_config_render_basic);
1817
1818 dev_priv->perf.oa.flex_regs =
1819 flex_eu_config_render_basic;
1820 dev_priv->perf.oa.flex_regs_len =
1821 ARRAY_SIZE(flex_eu_config_render_basic);
1822
1823 return 0;
1824 case METRIC_SET_ID_COMPUTE_BASIC:
1825 dev_priv->perf.oa.n_mux_configs =
1826 get_compute_basic_mux_config(dev_priv,
1827 dev_priv->perf.oa.mux_regs,
1828 dev_priv->perf.oa.mux_regs_lens);
1829 if (dev_priv->perf.oa.n_mux_configs == 0) {
1830 DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
1831
1832 /* EINVAL because *_register_sysfs already checked this
1833 * and so it wouldn't have been advertised to userspace and
1834 * so shouldn't have been requested
1835 */
1836 return -EINVAL;
1837 }
1838
1839 dev_priv->perf.oa.b_counter_regs =
1840 b_counter_config_compute_basic;
1841 dev_priv->perf.oa.b_counter_regs_len =
1842 ARRAY_SIZE(b_counter_config_compute_basic);
1843
1844 dev_priv->perf.oa.flex_regs =
1845 flex_eu_config_compute_basic;
1846 dev_priv->perf.oa.flex_regs_len =
1847 ARRAY_SIZE(flex_eu_config_compute_basic);
1848
1849 return 0;
1850 case METRIC_SET_ID_RENDER_PIPE_PROFILE:
1851 dev_priv->perf.oa.n_mux_configs =
1852 get_render_pipe_profile_mux_config(dev_priv,
1853 dev_priv->perf.oa.mux_regs,
1854 dev_priv->perf.oa.mux_regs_lens);
1855 if (dev_priv->perf.oa.n_mux_configs == 0) {
1856 DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n");
1857
1858 /* EINVAL because *_register_sysfs already checked this
1859 * and so it wouldn't have been advertised to userspace and
1860 * so shouldn't have been requested
1861 */
1862 return -EINVAL;
1863 }
1864
1865 dev_priv->perf.oa.b_counter_regs =
1866 b_counter_config_render_pipe_profile;
1867 dev_priv->perf.oa.b_counter_regs_len =
1868 ARRAY_SIZE(b_counter_config_render_pipe_profile);
1869
1870 dev_priv->perf.oa.flex_regs =
1871 flex_eu_config_render_pipe_profile;
1872 dev_priv->perf.oa.flex_regs_len =
1873 ARRAY_SIZE(flex_eu_config_render_pipe_profile);
1874
1875 return 0;
1876 case METRIC_SET_ID_MEMORY_READS:
1877 dev_priv->perf.oa.n_mux_configs =
1878 get_memory_reads_mux_config(dev_priv,
1879 dev_priv->perf.oa.mux_regs,
1880 dev_priv->perf.oa.mux_regs_lens);
1881 if (dev_priv->perf.oa.n_mux_configs == 0) {
1882 DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n");
1883
1884 /* EINVAL because *_register_sysfs already checked this
1885 * and so it wouldn't have been advertised to userspace and
1886 * so shouldn't have been requested
1887 */
1888 return -EINVAL;
1889 }
1890
1891 dev_priv->perf.oa.b_counter_regs =
1892 b_counter_config_memory_reads;
1893 dev_priv->perf.oa.b_counter_regs_len =
1894 ARRAY_SIZE(b_counter_config_memory_reads);
1895
1896 dev_priv->perf.oa.flex_regs =
1897 flex_eu_config_memory_reads;
1898 dev_priv->perf.oa.flex_regs_len =
1899 ARRAY_SIZE(flex_eu_config_memory_reads);
1900
1901 return 0;
1902 case METRIC_SET_ID_MEMORY_WRITES:
1903 dev_priv->perf.oa.n_mux_configs =
1904 get_memory_writes_mux_config(dev_priv,
1905 dev_priv->perf.oa.mux_regs,
1906 dev_priv->perf.oa.mux_regs_lens);
1907 if (dev_priv->perf.oa.n_mux_configs == 0) {
1908 DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n");
1909
1910 /* EINVAL because *_register_sysfs already checked this
1911 * and so it wouldn't have been advertised to userspace and
1912 * so shouldn't have been requested
1913 */
1914 return -EINVAL;
1915 }
1916
1917 dev_priv->perf.oa.b_counter_regs =
1918 b_counter_config_memory_writes;
1919 dev_priv->perf.oa.b_counter_regs_len =
1920 ARRAY_SIZE(b_counter_config_memory_writes);
1921
1922 dev_priv->perf.oa.flex_regs =
1923 flex_eu_config_memory_writes;
1924 dev_priv->perf.oa.flex_regs_len =
1925 ARRAY_SIZE(flex_eu_config_memory_writes);
1926
1927 return 0;
1928 case METRIC_SET_ID_COMPUTE_EXTENDED:
1929 dev_priv->perf.oa.n_mux_configs =
1930 get_compute_extended_mux_config(dev_priv,
1931 dev_priv->perf.oa.mux_regs,
1932 dev_priv->perf.oa.mux_regs_lens);
1933 if (dev_priv->perf.oa.n_mux_configs == 0) {
1934 DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n");
1935
1936 /* EINVAL because *_register_sysfs already checked this
1937 * and so it wouldn't have been advertised to userspace and
1938 * so shouldn't have been requested
1939 */
1940 return -EINVAL;
1941 }
1942
1943 dev_priv->perf.oa.b_counter_regs =
1944 b_counter_config_compute_extended;
1945 dev_priv->perf.oa.b_counter_regs_len =
1946 ARRAY_SIZE(b_counter_config_compute_extended);
1947
1948 dev_priv->perf.oa.flex_regs =
1949 flex_eu_config_compute_extended;
1950 dev_priv->perf.oa.flex_regs_len =
1951 ARRAY_SIZE(flex_eu_config_compute_extended);
1952
1953 return 0;
1954 case METRIC_SET_ID_COMPUTE_L3_CACHE:
1955 dev_priv->perf.oa.n_mux_configs =
1956 get_compute_l3_cache_mux_config(dev_priv,
1957 dev_priv->perf.oa.mux_regs,
1958 dev_priv->perf.oa.mux_regs_lens);
1959 if (dev_priv->perf.oa.n_mux_configs == 0) {
1960 DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n");
1961
1962 /* EINVAL because *_register_sysfs already checked this
1963 * and so it wouldn't have been advertised to userspace and
1964 * so shouldn't have been requested
1965 */
1966 return -EINVAL;
1967 }
1968
1969 dev_priv->perf.oa.b_counter_regs =
1970 b_counter_config_compute_l3_cache;
1971 dev_priv->perf.oa.b_counter_regs_len =
1972 ARRAY_SIZE(b_counter_config_compute_l3_cache);
1973
1974 dev_priv->perf.oa.flex_regs =
1975 flex_eu_config_compute_l3_cache;
1976 dev_priv->perf.oa.flex_regs_len =
1977 ARRAY_SIZE(flex_eu_config_compute_l3_cache);
1978
1979 return 0;
1980 case METRIC_SET_ID_HDC_AND_SF:
1981 dev_priv->perf.oa.n_mux_configs =
1982 get_hdc_and_sf_mux_config(dev_priv,
1983 dev_priv->perf.oa.mux_regs,
1984 dev_priv->perf.oa.mux_regs_lens);
1985 if (dev_priv->perf.oa.n_mux_configs == 0) {
1986 DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n");
1987
1988 /* EINVAL because *_register_sysfs already checked this
1989 * and so it wouldn't have been advertised to userspace and
1990 * so shouldn't have been requested
1991 */
1992 return -EINVAL;
1993 }
1994
1995 dev_priv->perf.oa.b_counter_regs =
1996 b_counter_config_hdc_and_sf;
1997 dev_priv->perf.oa.b_counter_regs_len =
1998 ARRAY_SIZE(b_counter_config_hdc_and_sf);
1999
2000 dev_priv->perf.oa.flex_regs =
2001 flex_eu_config_hdc_and_sf;
2002 dev_priv->perf.oa.flex_regs_len =
2003 ARRAY_SIZE(flex_eu_config_hdc_and_sf);
2004
2005 return 0;
2006 case METRIC_SET_ID_L3_1:
2007 dev_priv->perf.oa.n_mux_configs =
2008 get_l3_1_mux_config(dev_priv,
2009 dev_priv->perf.oa.mux_regs,
2010 dev_priv->perf.oa.mux_regs_lens);
2011 if (dev_priv->perf.oa.n_mux_configs == 0) {
2012 DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n");
2013
2014 /* EINVAL because *_register_sysfs already checked this
2015 * and so it wouldn't have been advertised to userspace and
2016 * so shouldn't have been requested
2017 */
2018 return -EINVAL;
2019 }
2020
2021 dev_priv->perf.oa.b_counter_regs =
2022 b_counter_config_l3_1;
2023 dev_priv->perf.oa.b_counter_regs_len =
2024 ARRAY_SIZE(b_counter_config_l3_1);
2025
2026 dev_priv->perf.oa.flex_regs =
2027 flex_eu_config_l3_1;
2028 dev_priv->perf.oa.flex_regs_len =
2029 ARRAY_SIZE(flex_eu_config_l3_1);
2030
2031 return 0;
2032 case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
2033 dev_priv->perf.oa.n_mux_configs =
2034 get_rasterizer_and_pixel_backend_mux_config(dev_priv,
2035 dev_priv->perf.oa.mux_regs,
2036 dev_priv->perf.oa.mux_regs_lens);
2037 if (dev_priv->perf.oa.n_mux_configs == 0) {
2038 DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n");
2039
2040 /* EINVAL because *_register_sysfs already checked this
2041 * and so it wouldn't have been advertised to userspace and
2042 * so shouldn't have been requested
2043 */
2044 return -EINVAL;
2045 }
2046
2047 dev_priv->perf.oa.b_counter_regs =
2048 b_counter_config_rasterizer_and_pixel_backend;
2049 dev_priv->perf.oa.b_counter_regs_len =
2050 ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
2051
2052 dev_priv->perf.oa.flex_regs =
2053 flex_eu_config_rasterizer_and_pixel_backend;
2054 dev_priv->perf.oa.flex_regs_len =
2055 ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
2056
2057 return 0;
2058 case METRIC_SET_ID_SAMPLER:
2059 dev_priv->perf.oa.n_mux_configs =
2060 get_sampler_mux_config(dev_priv,
2061 dev_priv->perf.oa.mux_regs,
2062 dev_priv->perf.oa.mux_regs_lens);
2063 if (dev_priv->perf.oa.n_mux_configs == 0) {
2064 DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n");
2065
2066 /* EINVAL because *_register_sysfs already checked this
2067 * and so it wouldn't have been advertised to userspace and
2068 * so shouldn't have been requested
2069 */
2070 return -EINVAL;
2071 }
2072
2073 dev_priv->perf.oa.b_counter_regs =
2074 b_counter_config_sampler;
2075 dev_priv->perf.oa.b_counter_regs_len =
2076 ARRAY_SIZE(b_counter_config_sampler);
2077
2078 dev_priv->perf.oa.flex_regs =
2079 flex_eu_config_sampler;
2080 dev_priv->perf.oa.flex_regs_len =
2081 ARRAY_SIZE(flex_eu_config_sampler);
2082
2083 return 0;
2084 case METRIC_SET_ID_TDL_1:
2085 dev_priv->perf.oa.n_mux_configs =
2086 get_tdl_1_mux_config(dev_priv,
2087 dev_priv->perf.oa.mux_regs,
2088 dev_priv->perf.oa.mux_regs_lens);
2089 if (dev_priv->perf.oa.n_mux_configs == 0) {
2090 DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n");
2091
2092 /* EINVAL because *_register_sysfs already checked this
2093 * and so it wouldn't have been advertised to userspace and
2094 * so shouldn't have been requested
2095 */
2096 return -EINVAL;
2097 }
2098
2099 dev_priv->perf.oa.b_counter_regs =
2100 b_counter_config_tdl_1;
2101 dev_priv->perf.oa.b_counter_regs_len =
2102 ARRAY_SIZE(b_counter_config_tdl_1);
2103
2104 dev_priv->perf.oa.flex_regs =
2105 flex_eu_config_tdl_1;
2106 dev_priv->perf.oa.flex_regs_len =
2107 ARRAY_SIZE(flex_eu_config_tdl_1);
2108
2109 return 0;
2110 case METRIC_SET_ID_TDL_2:
2111 dev_priv->perf.oa.n_mux_configs =
2112 get_tdl_2_mux_config(dev_priv,
2113 dev_priv->perf.oa.mux_regs,
2114 dev_priv->perf.oa.mux_regs_lens);
2115 if (dev_priv->perf.oa.n_mux_configs == 0) {
2116 DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n");
2117
2118 /* EINVAL because *_register_sysfs already checked this
2119 * and so it wouldn't have been advertised to userspace and
2120 * so shouldn't have been requested
2121 */
2122 return -EINVAL;
2123 }
2124
2125 dev_priv->perf.oa.b_counter_regs =
2126 b_counter_config_tdl_2;
2127 dev_priv->perf.oa.b_counter_regs_len =
2128 ARRAY_SIZE(b_counter_config_tdl_2);
2129
2130 dev_priv->perf.oa.flex_regs =
2131 flex_eu_config_tdl_2;
2132 dev_priv->perf.oa.flex_regs_len =
2133 ARRAY_SIZE(flex_eu_config_tdl_2);
2134
2135 return 0;
2136 case METRIC_SET_ID_COMPUTE_EXTRA:
2137 dev_priv->perf.oa.n_mux_configs =
2138 get_compute_extra_mux_config(dev_priv,
2139 dev_priv->perf.oa.mux_regs,
2140 dev_priv->perf.oa.mux_regs_lens);
2141 if (dev_priv->perf.oa.n_mux_configs == 0) {
2142 DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n");
2143
2144 /* EINVAL because *_register_sysfs already checked this
2145 * and so it wouldn't have been advertised to userspace and
2146 * so shouldn't have been requested
2147 */
2148 return -EINVAL;
2149 }
2150
2151 dev_priv->perf.oa.b_counter_regs =
2152 b_counter_config_compute_extra;
2153 dev_priv->perf.oa.b_counter_regs_len =
2154 ARRAY_SIZE(b_counter_config_compute_extra);
2155
2156 dev_priv->perf.oa.flex_regs =
2157 flex_eu_config_compute_extra;
2158 dev_priv->perf.oa.flex_regs_len =
2159 ARRAY_SIZE(flex_eu_config_compute_extra);
2160
2161 return 0;
2162 case METRIC_SET_ID_TEST_OA:
2163 dev_priv->perf.oa.n_mux_configs =
2164 get_test_oa_mux_config(dev_priv,
2165 dev_priv->perf.oa.mux_regs,
2166 dev_priv->perf.oa.mux_regs_lens);
2167 if (dev_priv->perf.oa.n_mux_configs == 0) {
2168 DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n");
2169
2170 /* EINVAL because *_register_sysfs already checked this
2171 * and so it wouldn't have been advertised to userspace and
2172 * so shouldn't have been requested
2173 */
2174 return -EINVAL;
2175 }
2176
2177 dev_priv->perf.oa.b_counter_regs =
2178 b_counter_config_test_oa;
2179 dev_priv->perf.oa.b_counter_regs_len =
2180 ARRAY_SIZE(b_counter_config_test_oa);
2181
2182 dev_priv->perf.oa.flex_regs =
2183 flex_eu_config_test_oa;
2184 dev_priv->perf.oa.flex_regs_len =
2185 ARRAY_SIZE(flex_eu_config_test_oa);
2186
2187 return 0;
2188 default:
2189 return -ENODEV;
2190 }
2191}
2192
2193static ssize_t
2194show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
2195{
2196 return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
2197}
2198
2199static struct device_attribute dev_attr_render_basic_id = {
2200 .attr = { .name = "id", .mode = 0444 },
2201 .show = show_render_basic_id,
2202 .store = NULL,
2203};
2204
2205static struct attribute *attrs_render_basic[] = {
2206 &dev_attr_render_basic_id.attr,
2207 NULL,
2208};
2209
2210static struct attribute_group group_render_basic = {
2211 .name = "22b9519a-e9ba-4c41-8b54-f4f8ca14fa0a",
2212 .attrs = attrs_render_basic,
2213};
2214
2215static ssize_t
2216show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
2217{
2218 return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
2219}
2220
2221static struct device_attribute dev_attr_compute_basic_id = {
2222 .attr = { .name = "id", .mode = 0444 },
2223 .show = show_compute_basic_id,
2224 .store = NULL,
2225};
2226
2227static struct attribute *attrs_compute_basic[] = {
2228 &dev_attr_compute_basic_id.attr,
2229 NULL,
2230};
2231
2232static struct attribute_group group_compute_basic = {
2233 .name = "012d72cf-82a9-4d25-8ddf-74076fd30797",
2234 .attrs = attrs_compute_basic,
2235};
2236
2237static ssize_t
2238show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
2239{
2240 return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
2241}
2242
2243static struct device_attribute dev_attr_render_pipe_profile_id = {
2244 .attr = { .name = "id", .mode = 0444 },
2245 .show = show_render_pipe_profile_id,
2246 .store = NULL,
2247};
2248
2249static struct attribute *attrs_render_pipe_profile[] = {
2250 &dev_attr_render_pipe_profile_id.attr,
2251 NULL,
2252};
2253
2254static struct attribute_group group_render_pipe_profile = {
2255 .name = "ce416533-e49e-4211-80af-ec513590a914",
2256 .attrs = attrs_render_pipe_profile,
2257};
2258
2259static ssize_t
2260show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
2261{
2262 return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
2263}
2264
2265static struct device_attribute dev_attr_memory_reads_id = {
2266 .attr = { .name = "id", .mode = 0444 },
2267 .show = show_memory_reads_id,
2268 .store = NULL,
2269};
2270
2271static struct attribute *attrs_memory_reads[] = {
2272 &dev_attr_memory_reads_id.attr,
2273 NULL,
2274};
2275
2276static struct attribute_group group_memory_reads = {
2277 .name = "398e2452-18d7-42d0-b241-e4d0a9148ada",
2278 .attrs = attrs_memory_reads,
2279};
2280
2281static ssize_t
2282show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
2283{
2284 return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
2285}
2286
2287static struct device_attribute dev_attr_memory_writes_id = {
2288 .attr = { .name = "id", .mode = 0444 },
2289 .show = show_memory_writes_id,
2290 .store = NULL,
2291};
2292
2293static struct attribute *attrs_memory_writes[] = {
2294 &dev_attr_memory_writes_id.attr,
2295 NULL,
2296};
2297
2298static struct attribute_group group_memory_writes = {
2299 .name = "d324a0d6-7269-4847-a5c2-6f71ddc7fed5",
2300 .attrs = attrs_memory_writes,
2301};
2302
2303static ssize_t
2304show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
2305{
2306 return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
2307}
2308
2309static struct device_attribute dev_attr_compute_extended_id = {
2310 .attr = { .name = "id", .mode = 0444 },
2311 .show = show_compute_extended_id,
2312 .store = NULL,
2313};
2314
2315static struct attribute *attrs_compute_extended[] = {
2316 &dev_attr_compute_extended_id.attr,
2317 NULL,
2318};
2319
2320static struct attribute_group group_compute_extended = {
2321 .name = "caf3596a-7bb1-4dec-b3b3-2a080d283b49",
2322 .attrs = attrs_compute_extended,
2323};
2324
2325static ssize_t
2326show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
2327{
2328 return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
2329}
2330
2331static struct device_attribute dev_attr_compute_l3_cache_id = {
2332 .attr = { .name = "id", .mode = 0444 },
2333 .show = show_compute_l3_cache_id,
2334 .store = NULL,
2335};
2336
2337static struct attribute *attrs_compute_l3_cache[] = {
2338 &dev_attr_compute_l3_cache_id.attr,
2339 NULL,
2340};
2341
2342static struct attribute_group group_compute_l3_cache = {
2343 .name = "49b956e2-d5b9-47e0-9d8a-cee5e8cec527",
2344 .attrs = attrs_compute_l3_cache,
2345};
2346
2347static ssize_t
2348show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
2349{
2350 return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
2351}
2352
2353static struct device_attribute dev_attr_hdc_and_sf_id = {
2354 .attr = { .name = "id", .mode = 0444 },
2355 .show = show_hdc_and_sf_id,
2356 .store = NULL,
2357};
2358
2359static struct attribute *attrs_hdc_and_sf[] = {
2360 &dev_attr_hdc_and_sf_id.attr,
2361 NULL,
2362};
2363
2364static struct attribute_group group_hdc_and_sf = {
2365 .name = "f64ef50a-bdba-4b35-8f09-203c13d8ee5a",
2366 .attrs = attrs_hdc_and_sf,
2367};
2368
2369static ssize_t
2370show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
2371{
2372 return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
2373}
2374
2375static struct device_attribute dev_attr_l3_1_id = {
2376 .attr = { .name = "id", .mode = 0444 },
2377 .show = show_l3_1_id,
2378 .store = NULL,
2379};
2380
2381static struct attribute *attrs_l3_1[] = {
2382 &dev_attr_l3_1_id.attr,
2383 NULL,
2384};
2385
2386static struct attribute_group group_l3_1 = {
2387 .name = "00ad5a41-7eab-4f7a-9103-49d411c67219",
2388 .attrs = attrs_l3_1,
2389};
2390
2391static ssize_t
2392show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
2393{
2394 return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
2395}
2396
2397static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
2398 .attr = { .name = "id", .mode = 0444 },
2399 .show = show_rasterizer_and_pixel_backend_id,
2400 .store = NULL,
2401};
2402
2403static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
2404 &dev_attr_rasterizer_and_pixel_backend_id.attr,
2405 NULL,
2406};
2407
2408static struct attribute_group group_rasterizer_and_pixel_backend = {
2409 .name = "46dc44ca-491c-4cc1-a951-e7b3e62bf02b",
2410 .attrs = attrs_rasterizer_and_pixel_backend,
2411};
2412
2413static ssize_t
2414show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf)
2415{
2416 return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER);
2417}
2418
2419static struct device_attribute dev_attr_sampler_id = {
2420 .attr = { .name = "id", .mode = 0444 },
2421 .show = show_sampler_id,
2422 .store = NULL,
2423};
2424
2425static struct attribute *attrs_sampler[] = {
2426 &dev_attr_sampler_id.attr,
2427 NULL,
2428};
2429
2430static struct attribute_group group_sampler = {
2431 .name = "8364e2a8-af63-40af-b0d5-42969a255654",
2432 .attrs = attrs_sampler,
2433};
2434
2435static ssize_t
2436show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
2437{
2438 return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
2439}
2440
2441static struct device_attribute dev_attr_tdl_1_id = {
2442 .attr = { .name = "id", .mode = 0444 },
2443 .show = show_tdl_1_id,
2444 .store = NULL,
2445};
2446
2447static struct attribute *attrs_tdl_1[] = {
2448 &dev_attr_tdl_1_id.attr,
2449 NULL,
2450};
2451
2452static struct attribute_group group_tdl_1 = {
2453 .name = "175c8092-cb25-4d1e-8dc7-b4fdd39e2d92",
2454 .attrs = attrs_tdl_1,
2455};
2456
2457static ssize_t
2458show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
2459{
2460 return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
2461}
2462
2463static struct device_attribute dev_attr_tdl_2_id = {
2464 .attr = { .name = "id", .mode = 0444 },
2465 .show = show_tdl_2_id,
2466 .store = NULL,
2467};
2468
2469static struct attribute *attrs_tdl_2[] = {
2470 &dev_attr_tdl_2_id.attr,
2471 NULL,
2472};
2473
2474static struct attribute_group group_tdl_2 = {
2475 .name = "d260f03f-b34d-4b49-a44e-436819117332",
2476 .attrs = attrs_tdl_2,
2477};
2478
2479static ssize_t
2480show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
2481{
2482 return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
2483}
2484
2485static struct device_attribute dev_attr_compute_extra_id = {
2486 .attr = { .name = "id", .mode = 0444 },
2487 .show = show_compute_extra_id,
2488 .store = NULL,
2489};
2490
2491static struct attribute *attrs_compute_extra[] = {
2492 &dev_attr_compute_extra_id.attr,
2493 NULL,
2494};
2495
2496static struct attribute_group group_compute_extra = {
2497 .name = "fa6ecf21-2cb8-4d0b-9308-6e4a7b4ca87a",
2498 .attrs = attrs_compute_extra,
2499};
2500
2501static ssize_t
2502show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
2503{
2504 return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
2505}
2506
2507static struct device_attribute dev_attr_test_oa_id = {
2508 .attr = { .name = "id", .mode = 0444 },
2509 .show = show_test_oa_id,
2510 .store = NULL,
2511};
2512
2513static struct attribute *attrs_test_oa[] = {
2514 &dev_attr_test_oa_id.attr,
2515 NULL,
2516};
2517
2518static struct attribute_group group_test_oa = {
2519 .name = "5ee72f5c-092f-421e-8b70-225f7c3e9612",
2520 .attrs = attrs_test_oa,
2521};
2522
2523int
2524i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv)
2525{
2526 const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
2527 int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
2528 int ret = 0;
2529
2530 if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
2531 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
2532 if (ret)
2533 goto error_render_basic;
2534 }
2535 if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
2536 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
2537 if (ret)
2538 goto error_compute_basic;
2539 }
2540 if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) {
2541 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
2542 if (ret)
2543 goto error_render_pipe_profile;
2544 }
2545 if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) {
2546 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
2547 if (ret)
2548 goto error_memory_reads;
2549 }
2550 if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) {
2551 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
2552 if (ret)
2553 goto error_memory_writes;
2554 }
2555 if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) {
2556 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
2557 if (ret)
2558 goto error_compute_extended;
2559 }
2560 if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) {
2561 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
2562 if (ret)
2563 goto error_compute_l3_cache;
2564 }
2565 if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) {
2566 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
2567 if (ret)
2568 goto error_hdc_and_sf;
2569 }
2570 if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) {
2571 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
2572 if (ret)
2573 goto error_l3_1;
2574 }
2575 if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) {
2576 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
2577 if (ret)
2578 goto error_rasterizer_and_pixel_backend;
2579 }
2580 if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) {
2581 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler);
2582 if (ret)
2583 goto error_sampler;
2584 }
2585 if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) {
2586 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
2587 if (ret)
2588 goto error_tdl_1;
2589 }
2590 if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) {
2591 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
2592 if (ret)
2593 goto error_tdl_2;
2594 }
2595 if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) {
2596 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
2597 if (ret)
2598 goto error_compute_extra;
2599 }
2600 if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) {
2601 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
2602 if (ret)
2603 goto error_test_oa;
2604 }
2605
2606 return 0;
2607
2608error_test_oa:
2609 if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
2610 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
2611error_compute_extra:
2612 if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
2613 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
2614error_tdl_2:
2615 if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
2616 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
2617error_tdl_1:
2618 if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
2619 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
2620error_sampler:
2621 if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
2622 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
2623error_rasterizer_and_pixel_backend:
2624 if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
2625 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
2626error_l3_1:
2627 if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
2628 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
2629error_hdc_and_sf:
2630 if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
2631 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
2632error_compute_l3_cache:
2633 if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
2634 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
2635error_compute_extended:
2636 if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
2637 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
2638error_memory_writes:
2639 if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
2640 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
2641error_memory_reads:
2642 if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
2643 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
2644error_render_pipe_profile:
2645 if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
2646 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
2647error_compute_basic:
2648 if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
2649 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
2650error_render_basic:
2651 return ret;
2652}
2653
2654void
2655i915_perf_unregister_sysfs_bxt(struct drm_i915_private *dev_priv)
2656{
2657 const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
2658 int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
2659
2660 if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
2661 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
2662 if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
2663 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
2664 if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
2665 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
2666 if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
2667 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
2668 if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
2669 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
2670 if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
2671 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
2672 if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
2673 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
2674 if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
2675 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
2676 if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
2677 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
2678 if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
2679 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
2680 if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
2681 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
2682 if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
2683 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
2684 if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
2685 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
2686 if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
2687 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
2688 if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens))
2689 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
2690}