tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef _HWMGR_H_
24#define _HWMGR_H_
25
26#include <linux/seq_file.h>
27#include "amd_powerplay.h"
28#include "pp_instance.h"
29#include "hardwaremanager.h"
30#include "pp_power_source.h"
31#include "hwmgr_ppt.h"
32#include "ppatomctrl.h"
33#include "hwmgr_ppt.h"
34#include "power_state.h"
35
36struct pp_instance;
37struct pp_hwmgr;
38struct phm_fan_speed_info;
39struct pp_atomctrl_voltage_table;
40
41#define VOLTAGE_SCALE 4
42
43uint8_t convert_to_vid(uint16_t vddc);
44
45enum DISPLAY_GAP {
46 DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
47 DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
48 DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
49 DISPLAY_GAP_IGNORE = 3 /* Do not wait. */
50};
51typedef enum DISPLAY_GAP DISPLAY_GAP;
52
53struct vi_dpm_level {
54 bool enabled;
55 uint32_t value;
56 uint32_t param1;
57};
58
59struct vi_dpm_table {
60 uint32_t count;
61 struct vi_dpm_level dpm_level[1];
62};
63
64enum PP_Result {
65 PP_Result_TableImmediateExit = 0x13,
66};
67
68#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
69#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
70#define PCIE_PERF_REQ_GEN1 2
71#define PCIE_PERF_REQ_GEN2 3
72#define PCIE_PERF_REQ_GEN3 4
73
74enum PP_FEATURE_MASK {
75 PP_SCLK_DPM_MASK = 0x1,
76 PP_MCLK_DPM_MASK = 0x2,
77 PP_PCIE_DPM_MASK = 0x4,
78 PP_SCLK_DEEP_SLEEP_MASK = 0x8,
79 PP_POWER_CONTAINMENT_MASK = 0x10,
80 PP_UVD_HANDSHAKE_MASK = 0x20,
81 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
82 PP_VBI_TIME_SUPPORT_MASK = 0x80,
83 PP_ULV_MASK = 0x100,
84 PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
85 PP_CLOCK_STRETCH_MASK = 0x400,
86 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
87 PP_SOCCLK_DPM_MASK = 0x1000,
88 PP_DCEFCLK_DPM_MASK = 0x2000,
89};
90
91enum PHM_BackEnd_Magic {
92 PHM_Dummy_Magic = 0xAA5555AA,
93 PHM_RV770_Magic = 0xDCBAABCD,
94 PHM_Kong_Magic = 0x239478DF,
95 PHM_NIslands_Magic = 0x736C494E,
96 PHM_Sumo_Magic = 0x8339FA11,
97 PHM_SIslands_Magic = 0x369431AC,
98 PHM_Trinity_Magic = 0x96751873,
99 PHM_CIslands_Magic = 0x38AC78B0,
100 PHM_Kv_Magic = 0xDCBBABC0,
101 PHM_VIslands_Magic = 0x20130307,
102 PHM_Cz_Magic = 0x67DCBA25,
103 PHM_Rv_Magic = 0x20161121
104};
105
106
107#define PHM_PCIE_POWERGATING_TARGET_GFX 0
108#define PHM_PCIE_POWERGATING_TARGET_DDI 1
109#define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2
110#define PHM_PCIE_POWERGATING_TARGET_PHY 3
111
112typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
113 void *output, void *storage, int result);
114
115typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
116
117struct phm_set_power_state_input {
118 const struct pp_hw_power_state *pcurrent_state;
119 const struct pp_hw_power_state *pnew_state;
120};
121
122struct phm_acp_arbiter {
123 uint32_t acpclk;
124};
125
126struct phm_uvd_arbiter {
127 uint32_t vclk;
128 uint32_t dclk;
129 uint32_t vclk_ceiling;
130 uint32_t dclk_ceiling;
131};
132
133struct phm_vce_arbiter {
134 uint32_t evclk;
135 uint32_t ecclk;
136};
137
138struct phm_gfx_arbiter {
139 uint32_t sclk;
140 uint32_t sclk_hard_min;
141 uint32_t mclk;
142 uint32_t sclk_over_drive;
143 uint32_t mclk_over_drive;
144 uint32_t sclk_threshold;
145 uint32_t num_cus;
146 uint32_t gfxclk;
147 uint32_t fclk;
148};
149
150/* Entries in the master tables */
151struct phm_master_table_item {
152 phm_check_function isFunctionNeededInRuntimeTable;
153 phm_table_function tableFunction;
154};
155
156enum phm_master_table_flag {
157 PHM_MasterTableFlag_None = 0,
158 PHM_MasterTableFlag_ExitOnError = 1,
159};
160
161/* The header of the master tables */
162struct phm_master_table_header {
163 uint32_t storage_size;
164 uint32_t flags;
165 const struct phm_master_table_item *master_list;
166};
167
168struct phm_runtime_table_header {
169 uint32_t storage_size;
170 bool exit_error;
171 phm_table_function *function_list;
172};
173
174struct phm_clock_array {
175 uint32_t count;
176 uint32_t values[1];
177};
178
179struct phm_clock_voltage_dependency_record {
180 uint32_t clk;
181 uint32_t v;
182};
183
184struct phm_vceclock_voltage_dependency_record {
185 uint32_t ecclk;
186 uint32_t evclk;
187 uint32_t v;
188};
189
190struct phm_uvdclock_voltage_dependency_record {
191 uint32_t vclk;
192 uint32_t dclk;
193 uint32_t v;
194};
195
196struct phm_samuclock_voltage_dependency_record {
197 uint32_t samclk;
198 uint32_t v;
199};
200
201struct phm_acpclock_voltage_dependency_record {
202 uint32_t acpclk;
203 uint32_t v;
204};
205
206struct phm_clock_voltage_dependency_table {
207 uint32_t count; /* Number of entries. */
208 struct phm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
209};
210
211struct phm_phase_shedding_limits_record {
212 uint32_t Voltage;
213 uint32_t Sclk;
214 uint32_t Mclk;
215};
216
217
218extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
219 struct phm_runtime_table_header *rt_table,
220 void *input, void *output);
221
222extern int phm_construct_table(struct pp_hwmgr *hwmgr,
223 const struct phm_master_table_header *master_table,
224 struct phm_runtime_table_header *rt_table);
225
226extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
227 struct phm_runtime_table_header *rt_table);
228
229
230struct phm_uvd_clock_voltage_dependency_record {
231 uint32_t vclk;
232 uint32_t dclk;
233 uint32_t v;
234};
235
236struct phm_uvd_clock_voltage_dependency_table {
237 uint8_t count;
238 struct phm_uvd_clock_voltage_dependency_record entries[1];
239};
240
241struct phm_acp_clock_voltage_dependency_record {
242 uint32_t acpclk;
243 uint32_t v;
244};
245
246struct phm_acp_clock_voltage_dependency_table {
247 uint32_t count;
248 struct phm_acp_clock_voltage_dependency_record entries[1];
249};
250
251struct phm_vce_clock_voltage_dependency_record {
252 uint32_t ecclk;
253 uint32_t evclk;
254 uint32_t v;
255};
256
257struct phm_phase_shedding_limits_table {
258 uint32_t count;
259 struct phm_phase_shedding_limits_record entries[1];
260};
261
262struct phm_vceclock_voltage_dependency_table {
263 uint8_t count; /* Number of entries. */
264 struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
265};
266
267struct phm_uvdclock_voltage_dependency_table {
268 uint8_t count; /* Number of entries. */
269 struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
270};
271
272struct phm_samuclock_voltage_dependency_table {
273 uint8_t count; /* Number of entries. */
274 struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
275};
276
277struct phm_acpclock_voltage_dependency_table {
278 uint32_t count; /* Number of entries. */
279 struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
280};
281
282struct phm_vce_clock_voltage_dependency_table {
283 uint8_t count;
284 struct phm_vce_clock_voltage_dependency_record entries[1];
285};
286
287struct pp_hwmgr_func {
288 int (*backend_init)(struct pp_hwmgr *hw_mgr);
289 int (*backend_fini)(struct pp_hwmgr *hw_mgr);
290 int (*asic_setup)(struct pp_hwmgr *hw_mgr);
291 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
292
293 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
294 struct pp_power_state *prequest_ps,
295 const struct pp_power_state *pcurrent_ps);
296
297 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
298 enum amd_dpm_forced_level level);
299
300 int (*dynamic_state_management_enable)(
301 struct pp_hwmgr *hw_mgr);
302 int (*dynamic_state_management_disable)(
303 struct pp_hwmgr *hw_mgr);
304
305 int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
306 struct pp_hw_power_state *hw_ps);
307
308 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
309 unsigned long, struct pp_power_state *);
310 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
311 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
312 int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
313 int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
314 int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
315 int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
316 int (*power_state_set)(struct pp_hwmgr *hwmgr,
317 const void *state);
318 int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
319 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
320 int (*display_config_changed)(struct pp_hwmgr *hwmgr);
321 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
322 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
323 const uint32_t *msg_id);
324 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
325 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
326 int (*get_temperature)(struct pp_hwmgr *hwmgr);
327 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
328 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
329 int (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
330 int (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
331 int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
332 int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
333 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
334 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
335 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
336 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
337 int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr,
338 const void *thermal_interrupt_info);
339 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
340 int (*check_states_equal)(struct pp_hwmgr *hwmgr,
341 const struct pp_hw_power_state *pstate1,
342 const struct pp_hw_power_state *pstate2,
343 bool *equal);
344 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
345 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
346 bool cc6_disable, bool pstate_disable,
347 bool pstate_switch_disable);
348 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
349 struct amd_pp_simple_clock_info *info);
350 int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
351 PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
352 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
353 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
354 int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
355 int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
356 enum amd_pp_clock_type type,
357 struct pp_clock_levels_with_latency *clocks);
358 int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
359 enum amd_pp_clock_type type,
360 struct pp_clock_levels_with_voltage *clocks);
361 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr,
362 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
363 int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
364 struct pp_display_clock_request *clock);
365 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
366 int (*power_off_asic)(struct pp_hwmgr *hwmgr);
367 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
368 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
369 int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
370 int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
371 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
372 int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
373 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
374 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
375 int (*set_power_profile_state)(struct pp_hwmgr *hwmgr,
376 struct amd_pp_profile *request);
377 int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
378 int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
379};
380
381struct pp_table_func {
382 int (*pptable_init)(struct pp_hwmgr *hw_mgr);
383 int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
384 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
385 int (*pptable_get_vce_state_table_entry)(
386 struct pp_hwmgr *hwmgr,
387 unsigned long i,
388 struct amd_vce_state *vce_state,
389 void **clock_info,
390 unsigned long *flag);
391};
392
393union phm_cac_leakage_record {
394 struct {
395 uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */
396 uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */
397 };
398 struct {
399 uint16_t Vddc1;
400 uint16_t Vddc2;
401 uint16_t Vddc3;
402 };
403};
404
405struct phm_cac_leakage_table {
406 uint32_t count;
407 union phm_cac_leakage_record entries[1];
408};
409
410struct phm_samu_clock_voltage_dependency_record {
411 uint32_t samclk;
412 uint32_t v;
413};
414
415
416struct phm_samu_clock_voltage_dependency_table {
417 uint8_t count;
418 struct phm_samu_clock_voltage_dependency_record entries[1];
419};
420
421struct phm_cac_tdp_table {
422 uint16_t usTDP;
423 uint16_t usConfigurableTDP;
424 uint16_t usTDC;
425 uint16_t usBatteryPowerLimit;
426 uint16_t usSmallPowerLimit;
427 uint16_t usLowCACLeakage;
428 uint16_t usHighCACLeakage;
429 uint16_t usMaximumPowerDeliveryLimit;
430 uint16_t usEDCLimit;
431 uint16_t usOperatingTempMinLimit;
432 uint16_t usOperatingTempMaxLimit;
433 uint16_t usOperatingTempStep;
434 uint16_t usOperatingTempHyst;
435 uint16_t usDefaultTargetOperatingTemp;
436 uint16_t usTargetOperatingTemp;
437 uint16_t usPowerTuneDataSetID;
438 uint16_t usSoftwareShutdownTemp;
439 uint16_t usClockStretchAmount;
440 uint16_t usTemperatureLimitHotspot;
441 uint16_t usTemperatureLimitLiquid1;
442 uint16_t usTemperatureLimitLiquid2;
443 uint16_t usTemperatureLimitVrVddc;
444 uint16_t usTemperatureLimitVrMvdd;
445 uint16_t usTemperatureLimitPlx;
446 uint8_t ucLiquid1_I2C_address;
447 uint8_t ucLiquid2_I2C_address;
448 uint8_t ucLiquid_I2C_Line;
449 uint8_t ucVr_I2C_address;
450 uint8_t ucVr_I2C_Line;
451 uint8_t ucPlx_I2C_address;
452 uint8_t ucPlx_I2C_Line;
453 uint32_t usBoostPowerLimit;
454 uint8_t ucCKS_LDO_REFSEL;
455};
456
457struct phm_tdp_table {
458 uint16_t usTDP;
459 uint16_t usConfigurableTDP;
460 uint16_t usTDC;
461 uint16_t usBatteryPowerLimit;
462 uint16_t usSmallPowerLimit;
463 uint16_t usLowCACLeakage;
464 uint16_t usHighCACLeakage;
465 uint16_t usMaximumPowerDeliveryLimit;
466 uint16_t usEDCLimit;
467 uint16_t usOperatingTempMinLimit;
468 uint16_t usOperatingTempMaxLimit;
469 uint16_t usOperatingTempStep;
470 uint16_t usOperatingTempHyst;
471 uint16_t usDefaultTargetOperatingTemp;
472 uint16_t usTargetOperatingTemp;
473 uint16_t usPowerTuneDataSetID;
474 uint16_t usSoftwareShutdownTemp;
475 uint16_t usClockStretchAmount;
476 uint16_t usTemperatureLimitTedge;
477 uint16_t usTemperatureLimitHotspot;
478 uint16_t usTemperatureLimitLiquid1;
479 uint16_t usTemperatureLimitLiquid2;
480 uint16_t usTemperatureLimitHBM;
481 uint16_t usTemperatureLimitVrVddc;
482 uint16_t usTemperatureLimitVrMvdd;
483 uint16_t usTemperatureLimitPlx;
484 uint8_t ucLiquid1_I2C_address;
485 uint8_t ucLiquid2_I2C_address;
486 uint8_t ucLiquid_I2C_Line;
487 uint8_t ucVr_I2C_address;
488 uint8_t ucVr_I2C_Line;
489 uint8_t ucPlx_I2C_address;
490 uint8_t ucPlx_I2C_Line;
491 uint8_t ucLiquid_I2C_LineSDA;
492 uint8_t ucVr_I2C_LineSDA;
493 uint8_t ucPlx_I2C_LineSDA;
494 uint32_t usBoostPowerLimit;
495 uint16_t usBoostStartTemperature;
496 uint16_t usBoostStopTemperature;
497 uint32_t ulBoostClock;
498};
499
500struct phm_ppm_table {
501 uint8_t ppm_design;
502 uint16_t cpu_core_number;
503 uint32_t platform_tdp;
504 uint32_t small_ac_platform_tdp;
505 uint32_t platform_tdc;
506 uint32_t small_ac_platform_tdc;
507 uint32_t apu_tdp;
508 uint32_t dgpu_tdp;
509 uint32_t dgpu_ulv_power;
510 uint32_t tj_max;
511};
512
513struct phm_vq_budgeting_record {
514 uint32_t ulCUs;
515 uint32_t ulSustainableSOCPowerLimitLow;
516 uint32_t ulSustainableSOCPowerLimitHigh;
517 uint32_t ulMinSclkLow;
518 uint32_t ulMinSclkHigh;
519 uint8_t ucDispConfig;
520 uint32_t ulDClk;
521 uint32_t ulEClk;
522 uint32_t ulSustainableSclk;
523 uint32_t ulSustainableCUs;
524};
525
526struct phm_vq_budgeting_table {
527 uint8_t numEntries;
528 struct phm_vq_budgeting_record entries[1];
529};
530
531struct phm_clock_and_voltage_limits {
532 uint32_t sclk;
533 uint32_t mclk;
534 uint32_t gfxclk;
535 uint16_t vddc;
536 uint16_t vddci;
537 uint16_t vddgfx;
538 uint16_t vddmem;
539};
540
541/* Structure to hold PPTable information */
542
543struct phm_ppt_v1_information {
544 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
545 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
546 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
547 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
548 struct phm_clock_array *valid_sclk_values;
549 struct phm_clock_array *valid_mclk_values;
550 struct phm_clock_array *valid_socclk_values;
551 struct phm_clock_array *valid_dcefclk_values;
552 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
553 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
554 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
555 struct phm_ppm_table *ppm_parameter_table;
556 struct phm_cac_tdp_table *cac_dtp_table;
557 struct phm_tdp_table *tdp_table;
558 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
559 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
560 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
561 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
562 struct phm_ppt_v1_pcie_table *pcie_table;
563 struct phm_ppt_v1_gpio_table *gpio_table;
564 uint16_t us_ulv_voltage_offset;
565 uint16_t us_ulv_smnclk_did;
566 uint16_t us_ulv_mp1clk_did;
567 uint16_t us_ulv_gfxclk_bypass;
568 uint16_t us_gfxclk_slew_rate;
569 uint16_t us_min_gfxclk_freq_limit;
570};
571
572struct phm_ppt_v2_information {
573 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
574 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
575 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
576 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
577 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
578 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
579 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
580 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
581
582 struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
583
584 struct phm_clock_array *valid_sclk_values;
585 struct phm_clock_array *valid_mclk_values;
586 struct phm_clock_array *valid_socclk_values;
587 struct phm_clock_array *valid_dcefclk_values;
588
589 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
590 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
591
592 struct phm_ppm_table *ppm_parameter_table;
593 struct phm_cac_tdp_table *cac_dtp_table;
594 struct phm_tdp_table *tdp_table;
595
596 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
597 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
598 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
599 struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
600
601 struct phm_ppt_v1_pcie_table *pcie_table;
602
603 uint16_t us_ulv_voltage_offset;
604 uint16_t us_ulv_smnclk_did;
605 uint16_t us_ulv_mp1clk_did;
606 uint16_t us_ulv_gfxclk_bypass;
607 uint16_t us_gfxclk_slew_rate;
608 uint16_t us_min_gfxclk_freq_limit;
609
610 uint8_t uc_gfx_dpm_voltage_mode;
611 uint8_t uc_soc_dpm_voltage_mode;
612 uint8_t uc_uclk_dpm_voltage_mode;
613 uint8_t uc_uvd_dpm_voltage_mode;
614 uint8_t uc_vce_dpm_voltage_mode;
615 uint8_t uc_mp0_dpm_voltage_mode;
616 uint8_t uc_dcef_dpm_voltage_mode;
617};
618
619struct phm_dynamic_state_info {
620 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
621 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
622 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
623 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
624 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
625 struct phm_clock_array *valid_sclk_values;
626 struct phm_clock_array *valid_mclk_values;
627 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
628 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
629 uint32_t mclk_sclk_ratio;
630 uint32_t sclk_mclk_delta;
631 uint32_t vddc_vddci_delta;
632 uint32_t min_vddc_for_pcie_gen2;
633 struct phm_cac_leakage_table *cac_leakage_table;
634 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
635
636 struct phm_vce_clock_voltage_dependency_table
637 *vce_clock_voltage_dependency_table;
638 struct phm_uvd_clock_voltage_dependency_table
639 *uvd_clock_voltage_dependency_table;
640 struct phm_acp_clock_voltage_dependency_table
641 *acp_clock_voltage_dependency_table;
642 struct phm_samu_clock_voltage_dependency_table
643 *samu_clock_voltage_dependency_table;
644
645 struct phm_ppm_table *ppm_parameter_table;
646 struct phm_cac_tdp_table *cac_dtp_table;
647 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
648 struct phm_vq_budgeting_table *vq_budgeting_table;
649};
650
651struct pp_fan_info {
652 bool bNoFan;
653 uint8_t ucTachometerPulsesPerRevolution;
654 uint32_t ulMinRPM;
655 uint32_t ulMaxRPM;
656};
657
658struct pp_advance_fan_control_parameters {
659 uint16_t usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
660 uint16_t usTMed; /* The middle temperature where we change slopes. */
661 uint16_t usTHigh; /* The high temperature for setting the second slope. */
662 uint16_t usPWMMin; /* The minimum PWM value in percent (0.01% increments). */
663 uint16_t usPWMMed; /* The PWM value (in percent) at TMed. */
664 uint16_t usPWMHigh; /* The PWM value at THigh. */
665 uint8_t ucTHyst; /* Temperature hysteresis. Integer. */
666 uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */
667 uint16_t usTMax; /* The max temperature */
668 uint8_t ucFanControlMode;
669 uint16_t usFanPWMMinLimit;
670 uint16_t usFanPWMMaxLimit;
671 uint16_t usFanPWMStep;
672 uint16_t usDefaultMaxFanPWM;
673 uint16_t usFanOutputSensitivity;
674 uint16_t usDefaultFanOutputSensitivity;
675 uint16_t usMaxFanPWM; /* The max Fan PWM value for Fuzzy Fan Control feature */
676 uint16_t usFanRPMMinLimit; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
677 uint16_t usFanRPMMaxLimit; /* Maximum limit range in percentage, usually set to 100% by default */
678 uint16_t usFanRPMStep; /* Step increments/decerements, in percent */
679 uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
680 uint16_t usMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
681 uint16_t usFanCurrentLow; /* Low current */
682 uint16_t usFanCurrentHigh; /* High current */
683 uint16_t usFanRPMLow; /* Low RPM */
684 uint16_t usFanRPMHigh; /* High RPM */
685 uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
686 uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */
687 uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */
688 uint16_t usFanGainEdge; /* The following is added for Fiji */
689 uint16_t usFanGainHotspot;
690 uint16_t usFanGainLiquid;
691 uint16_t usFanGainVrVddc;
692 uint16_t usFanGainVrMvdd;
693 uint16_t usFanGainPlx;
694 uint16_t usFanGainHbm;
695 uint8_t ucEnableZeroRPM;
696 uint8_t ucFanStopTemperature;
697 uint8_t ucFanStartTemperature;
698 uint32_t ulMaxFanSCLKAcousticLimit; /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */
699 uint32_t ulTargetGfxClk;
700 uint16_t usZeroRPMStartTemperature;
701 uint16_t usZeroRPMStopTemperature;
702};
703
704struct pp_thermal_controller_info {
705 uint8_t ucType;
706 uint8_t ucI2cLine;
707 uint8_t ucI2cAddress;
708 struct pp_fan_info fanInfo;
709 struct pp_advance_fan_control_parameters advanceFanControlParameters;
710};
711
712struct phm_microcode_version_info {
713 uint32_t SMC;
714 uint32_t DMCU;
715 uint32_t MC;
716 uint32_t NB;
717};
718
719enum PP_TABLE_VERSION {
720 PP_TABLE_V0 = 0,
721 PP_TABLE_V1,
722 PP_TABLE_V2,
723 PP_TABLE_MAX
724};
725
726/**
727 * The main hardware manager structure.
728 */
729struct pp_hwmgr {
730 uint32_t chip_family;
731 uint32_t chip_id;
732
733 uint32_t pp_table_version;
734 void *device;
735 struct pp_smumgr *smumgr;
736 const void *soft_pp_table;
737 uint32_t soft_pp_table_size;
738 void *hardcode_pp_table;
739 bool need_pp_table_upload;
740
741 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
742 uint32_t num_vce_state_tables;
743
744 enum amd_dpm_forced_level dpm_level;
745 enum amd_dpm_forced_level saved_dpm_level;
746 bool block_hw_access;
747 struct phm_gfx_arbiter gfx_arbiter;
748 struct phm_acp_arbiter acp_arbiter;
749 struct phm_uvd_arbiter uvd_arbiter;
750 struct phm_vce_arbiter vce_arbiter;
751 uint32_t usec_timeout;
752 void *pptable;
753 struct phm_platform_descriptor platform_descriptor;
754 void *backend;
755 enum PP_DAL_POWERLEVEL dal_power_level;
756 struct phm_dynamic_state_info dyn_state;
757 struct phm_runtime_table_header setup_asic;
758 struct phm_runtime_table_header power_down_asic;
759 struct phm_runtime_table_header disable_dynamic_state_management;
760 struct phm_runtime_table_header enable_dynamic_state_management;
761 struct phm_runtime_table_header set_power_state;
762 struct phm_runtime_table_header enable_clock_power_gatings;
763 struct phm_runtime_table_header display_configuration_changed;
764 struct phm_runtime_table_header start_thermal_controller;
765 struct phm_runtime_table_header set_temperature_range;
766 const struct pp_hwmgr_func *hwmgr_func;
767 const struct pp_table_func *pptable_func;
768 struct pp_power_state *ps;
769 enum pp_power_source power_source;
770 uint32_t num_ps;
771 struct pp_thermal_controller_info thermal_controller;
772 bool fan_ctrl_is_in_default_mode;
773 uint32_t fan_ctrl_default_mode;
774 bool fan_ctrl_enabled;
775 uint32_t tmin;
776 struct phm_microcode_version_info microcode_version_info;
777 uint32_t ps_size;
778 struct pp_power_state *current_ps;
779 struct pp_power_state *request_ps;
780 struct pp_power_state *boot_ps;
781 struct pp_power_state *uvd_ps;
782 struct amd_pp_display_configuration display_config;
783 uint32_t feature_mask;
784
785 /* power profile */
786 struct amd_pp_profile gfx_power_profile;
787 struct amd_pp_profile compute_power_profile;
788 struct amd_pp_profile default_gfx_power_profile;
789 struct amd_pp_profile default_compute_power_profile;
790 enum amd_pp_profile_type current_power_profile;
791};
792
793extern int hwmgr_early_init(struct pp_instance *handle);
794extern int hwmgr_hw_init(struct pp_instance *handle);
795extern int hwmgr_hw_fini(struct pp_instance *handle);
796extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
797 uint32_t value, uint32_t mask);
798
799extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
800 uint32_t indirect_port,
801 uint32_t index,
802 uint32_t value,
803 uint32_t mask);
804
805
806
807extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
808extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
809extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
810
811extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
812extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
813extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
814extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
815extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
816extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
817extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
818extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
819extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
820 uint32_t voltage);
821extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
822extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
823extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
824extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
825 uint16_t virtual_voltage_id, int32_t *sclk);
826extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
827extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
828extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
829
830extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
831extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
832extern int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
833
834extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
835 uint32_t sclk, uint16_t id, uint16_t *voltage);
836
837#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
838
839#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
840#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
841
842#define PHM_SET_FIELD(origval, reg, field, fieldval) \
843 (((origval) & ~PHM_FIELD_MASK(reg, field)) | \
844 (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
845
846#define PHM_GET_FIELD(value, reg, field) \
847 (((value) & PHM_FIELD_MASK(reg, field)) >> \
848 PHM_FIELD_SHIFT(reg, field))
849
850
851/* Operations on named fields. */
852
853#define PHM_READ_FIELD(device, reg, field) \
854 PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
855
856#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
857 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
858 reg, field)
859
860#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
861 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
862 reg, field)
863
864#define PHM_WRITE_FIELD(device, reg, field, fieldval) \
865 cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
866 cgs_read_register(device, mm##reg), reg, field, fieldval))
867
868#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
869 cgs_write_ind_register(device, port, ix##reg, \
870 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
871 reg, field, fieldval))
872
873#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
874 cgs_write_ind_register(device, port, ix##reg, \
875 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
876 reg, field, fieldval))
877
878#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
879 phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
880
881
882#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
883 PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
884
885#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
886 PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
887 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
888
889
890#endif /* _HWMGR_H_ */