tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1mt65xx USB3.0 PHY binding
2--------------------------
3
4This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
5
6Required properties (controller (parent) node):
7 - compatible : should be one of
8 "mediatek,mt2701-u3phy"
9 "mediatek,mt2712-u3phy"
10 "mediatek,mt8173-u3phy"
11 - clocks : (deprecated, use port's clocks instead) a list of phandle +
12 clock-specifier pairs, one for each entry in clock-names
13 - clock-names : (deprecated, use port's one instead) must contain
14 "u3phya_ref": for reference clock of usb3.0 analog phy.
15
16Required nodes : a sub-node is required for each port the controller
17 provides. Address range information including the usual
18 'reg' property is used inside these nodes to describe
19 the controller's topology.
20
21Optional properties (controller (parent) node):
22 - reg : offset and length of register shared by multiple ports,
23 exclude port's private register. It is needed on mt2701
24 and mt8173, but not on mt2712.
25
26Required properties (port (child) node):
27- reg : address and length of the register set for the port.
28- clocks : a list of phandle + clock-specifier pairs, one for each
29 entry in clock-names
30- clock-names : must contain
31 "ref": 48M reference clock for HighSpeed analog phy; and 26M
32 reference clock for SuperSpeed analog phy, sometimes is
33 24M, 25M or 27M, depended on platform.
34- #phy-cells : should be 1 (See second example)
35 cell after port phandle is phy type from:
36 - PHY_TYPE_USB2
37 - PHY_TYPE_USB3
38
39Example:
40
41u3phy: usb-phy@11290000 {
42 compatible = "mediatek,mt8173-u3phy";
43 reg = <0 0x11290000 0 0x800>;
44 #address-cells = <2>;
45 #size-cells = <2>;
46 ranges;
47 status = "okay";
48
49 u2port0: usb-phy@11290800 {
50 reg = <0 0x11290800 0 0x100>;
51 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
52 clock-names = "ref";
53 #phy-cells = <1>;
54 status = "okay";
55 };
56
57 u3port0: usb-phy@11290900 {
58 reg = <0 0x11290800 0 0x700>;
59 clocks = <&clk26m>;
60 clock-names = "ref";
61 #phy-cells = <1>;
62 status = "okay";
63 };
64
65 u2port1: usb-phy@11291000 {
66 reg = <0 0x11291000 0 0x100>;
67 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
68 clock-names = "ref";
69 #phy-cells = <1>;
70 status = "okay";
71 };
72};
73
74Specifying phy control of devices
75---------------------------------
76
77Device nodes should specify the configuration required in their "phys"
78property, containing a phandle to the phy port node and a device type;
79phy-names for each port are optional.
80
81Example:
82
83#include <dt-bindings/phy/phy.h>
84
85usb30: usb@11270000 {
86 ...
87 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
88 phy-names = "usb2-0", "usb3-0";
89 ...
90};
91
92
93Layout differences of banks between mt8173/mt2701 and mt2712
94-------------------------------------------------------------
95mt8173 and mt2701:
96port offset bank
97shared 0x0000 SPLLC
98 0x0100 FMREG
99u2 port0 0x0800 U2PHY_COM
100u3 port0 0x0900 U3PHYD
101 0x0a00 U3PHYD_BANK2
102 0x0b00 U3PHYA
103 0x0c00 U3PHYA_DA
104u2 port1 0x1000 U2PHY_COM
105u3 port1 0x1100 U3PHYD
106 0x1200 U3PHYD_BANK2
107 0x1300 U3PHYA
108 0x1400 U3PHYA_DA
109u2 port2 0x1800 U2PHY_COM
110 ...
111
112mt2712:
113port offset bank
114u2 port0 0x0000 MISC
115 0x0100 FMREG
116 0x0300 U2PHY_COM
117u3 port0 0x0700 SPLLC
118 0x0800 CHIP
119 0x0900 U3PHYD
120 0x0a00 U3PHYD_BANK2
121 0x0b00 U3PHYA
122 0x0c00 U3PHYA_DA
123u2 port1 0x1000 MISC
124 0x1100 FMREG
125 0x1300 U2PHY_COM
126u3 port1 0x1700 SPLLC
127 0x1800 CHIP
128 0x1900 U3PHYD
129 0x1a00 U3PHYD_BANK2
130 0x1b00 U3PHYA
131 0x1c00 U3PHYA_DA
132u2 port2 0x2000 MISC
133 ...
134
135 SPLLC shared by u3 ports and FMREG shared by u2 ports on
136mt8173/mt2701 are put back into each port; a new bank MISC for
137u2 ports and CHIP for u3 ports are added on mt2712.