tjh.dev
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1Binding for Texas Instruments gate clock.
2
3Binding status: Unstable - ABI compatibility may be broken in the future
4
5This binding uses the common clock binding[1]. This clock is
6quite much similar to the basic gate-clock [2], however,
7it supports a number of additional features. If no register
8is provided for this clock, the code assumes that a clockdomain
9will be controlled instead and the corresponding hw-ops for
10that is used.
11
12[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13[2] Documentation/devicetree/bindings/clock/gate-clock.txt
14[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
15
16Required properties:
17- compatible : shall be one of:
18 "ti,gate-clock" - basic gate clock
19 "ti,wait-gate-clock" - gate clock which waits until clock is active before
20 returning from clk_enable()
21 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
22 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
23 "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
24 clock directly from a clockdomain, see [3] how
25 to map clockdomains properly
26 "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
27 required for a hardware errata
28 "ti,composite-gate-clock" - composite gate clock, to be part of composite
29 clock
30 "ti,composite-no-wait-gate-clock" - composite gate clock that does not wait
31 for clock to be active before returning
32 from clk_enable()
33- #clock-cells : from common clock binding; shall be set to 0
34- clocks : link to phandle of parent clock
35- reg : offset for register controlling adjustable gate, not needed for
36 ti,clkdm-gate-clock type
37
38Optional properties:
39- ti,bit-shift : bit shift for programming the clock gate, invalid for
40 ti,clkdm-gate-clock type
41- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
42 gates the clock and clearing the bit ungates the clock.
43
44Examples:
45 mmchs2_fck: mmchs2_fck@48004a00 {
46 #clock-cells = <0>;
47 compatible = "ti,gate-clock";
48 clocks = <&core_96m_fck>;
49 reg = <0x0a00>;
50 ti,bit-shift = <25>;
51 };
52
53 uart4_fck_am35xx: uart4_fck_am35xx {
54 #clock-cells = <0>;
55 compatible = "ti,wait-gate-clock";
56 clocks = <&core_48m_fck>;
57 reg = <0x0a00>;
58 ti,bit-shift = <23>;
59 };
60
61 dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
62 #clock-cells = <0>;
63 compatible = "ti,dss-gate-clock";
64 clocks = <&dpll4_m4x2_ck>;
65 reg = <0x0e00>;
66 ti,bit-shift = <0>;
67 };
68
69 emac_ick: emac_ick@4800259c {
70 #clock-cells = <0>;
71 compatible = "ti,am35xx-gate-clock";
72 clocks = <&ipss_ick>;
73 reg = <0x059c>;
74 ti,bit-shift = <1>;
75 };
76
77 emu_src_ck: emu_src_ck {
78 #clock-cells = <0>;
79 compatible = "ti,clkdm-gate-clock";
80 clocks = <&emu_src_mux_ck>;
81 };
82
83 dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
84 #clock-cells = <0>;
85 compatible = "ti,hsdiv-gate-clock";
86 clocks = <&dpll4_m2x2_mul_ck>;
87 ti,bit-shift = <0x1b>;
88 reg = <0x0d00>;
89 ti,set-bit-to-disable;
90 };
91
92 vlynq_gate_fck: vlynq_gate_fck {
93 #clock-cells = <0>;
94 compatible = "ti,composite-gate-clock";
95 clocks = <&core_ck>;
96 ti,bit-shift = <3>;
97 reg = <0x0200>;
98 };
99
100 sys_clkout2_src_gate: sys_clkout2_src_gate {
101 #clock-cells = <0>;
102 compatible = "ti,composite-no-wait-gate-clock";
103 clocks = <&core_ck>;
104 ti,bit-shift = <15>;
105 reg = <0x0070>;
106 };