tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "nbio_v7_0.h"
26
27#include "vega10/soc15ip.h"
28#include "raven1/NBIO/nbio_7_0_default.h"
29#include "raven1/NBIO/nbio_7_0_offset.h"
30#include "raven1/NBIO/nbio_7_0_sh_mask.h"
31#include "vega10/vega10_enum.h"
32
33#define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c
34
35u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
36{
37 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
38
39 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
40 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
41
42 return tmp;
43}
44
45u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev,
46 uint32_t idx)
47{
48 return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx);
49}
50
51void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev,
52 uint32_t idx, uint32_t val)
53{
54 WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val);
55}
56
57void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
58{
59 if (enable)
60 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
61 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
62 else
63 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
64}
65
66void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)
67{
68 WREG32_SOC15(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
69}
70
71u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
72{
73 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
74}
75
76static const u32 nbio_sdma_doorbell_range_reg[] =
77{
78 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE),
79 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE)
80};
81
82void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
83 bool use_doorbell, int doorbell_index)
84{
85 u32 doorbell_range = RREG32(nbio_sdma_doorbell_range_reg[instance]);
86
87 if (use_doorbell) {
88 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
89 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
90 } else
91 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
92
93 WREG32(nbio_sdma_doorbell_range_reg[instance], doorbell_range);
94}
95
96void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
97 bool enable)
98{
99 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
100}
101
102void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
103 bool use_doorbell, int doorbell_index)
104{
105 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
106
107 if (use_doorbell) {
108 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
109 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
110 } else
111 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
112
113 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
114}
115
116static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset)
117{
118 uint32_t data;
119
120 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
121 data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA);
122
123 return data;
124}
125
126static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset,
127 uint32_t data)
128{
129 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
130 WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data);
131}
132
133void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
134 bool enable)
135{
136 uint32_t def, data;
137
138 /* NBIF_MGCG_CTRL_LCLK */
139 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
140
141 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
142 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
143 else
144 data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
145
146 if (def != data)
147 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
148
149 /* SYSHUB_MGCG_CTRL_SOCCLK */
150 def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK);
151
152 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
153 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
154 else
155 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
156
157 if (def != data)
158 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data);
159
160 /* SYSHUB_MGCG_CTRL_SHUBCLK */
161 def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK);
162
163 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
164 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
165 else
166 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
167
168 if (def != data)
169 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data);
170}
171
172void nbio_v7_0_ih_control(struct amdgpu_device *adev)
173{
174 u32 interrupt_cntl;
175
176 /* setup interrupt control */
177 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
178 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
179 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
180 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
181 */
182 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
183 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
184 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
185 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
186}
187
188struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
189struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
190
191int nbio_v7_0_init(struct amdgpu_device *adev)
192{
193 nbio_v7_0_hdp_flush_reg.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
194 nbio_v7_0_hdp_flush_reg.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
195 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK;
196 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK;
197 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK;
198 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK;
199 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK;
200 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK;
201 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK;
202 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK;
203 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK;
204 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK;
205 nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
206 nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
207
208 nbio_v7_0_pcie_index_data.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
209 nbio_v7_0_pcie_index_data.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
210
211 return 0;
212}