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1/* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef __ETH_COMMON__
34#define __ETH_COMMON__
35
36/********************/
37/* ETH FW CONSTANTS */
38/********************/
39#define ETH_HSI_VER_MAJOR 3
40#define ETH_HSI_VER_MINOR 10
41
42#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
43
44#define ETH_CACHE_LINE_SIZE 64
45#define ETH_RX_CQE_GAP 32
46#define ETH_MAX_RAMROD_PER_CON 8
47#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
48#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
49#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
50#define ETH_RX_NUM_NEXT_PAGE_BDS 2
51
52#define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253
53#define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251
54
55#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
56#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
57#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
58#define ETH_TX_MAX_LSO_HDR_NBD 4
59#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
60#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
61#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
62#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
63#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
64#define ETH_TX_MAX_LSO_HDR_BYTES 510
65#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
66#define ETH_TX_LSO_WINDOW_MIN_LEN 9700
67#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
68#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
69#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
70
71#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
72#define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \
73 (ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2)
74#define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \
75 (ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
76
77/* Maximum number of buffers, used for RX packet placement */
78#define ETH_RX_MAX_BUFF_PER_PKT 5
79
80/* num of MAC/VLAN filters */
81#define ETH_NUM_MAC_FILTERS 512
82#define ETH_NUM_VLAN_FILTERS 512
83
84/* approx. multicast constants */
85#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
86#define ETH_MULTICAST_MAC_BINS 256
87#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
88
89/* ethernet vport update constants */
90#define ETH_FILTER_RULES_COUNT 10
91#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
92#define ETH_RSS_KEY_SIZE_REGS 10
93#define ETH_RSS_ENGINE_NUM_K2 207
94#define ETH_RSS_ENGINE_NUM_BB 127
95
96/* TPA constants */
97#define ETH_TPA_MAX_AGGS_NUM 64
98#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
99#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
100#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
101
102/* Control frame check constants */
103#define ETH_CTL_FRAME_ETH_TYPE_NUM 4
104
105struct eth_tx_1st_bd_flags {
106 u8 bitfields;
107#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
108#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
109#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
110#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
111#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
112#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
113#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
114#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
115#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
116#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
117#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
118#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
119#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
120#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
121#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
122#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
123};
124
125/* The parsing information data fo rthe first tx bd of a given packet. */
126struct eth_tx_data_1st_bd {
127 __le16 vlan;
128 u8 nbds;
129 struct eth_tx_1st_bd_flags bd_flags;
130 __le16 bitfields;
131#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
132#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
133#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
134#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
135#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
136#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
137};
138
139/* The parsing information data for the second tx bd of a given packet. */
140struct eth_tx_data_2nd_bd {
141 __le16 tunn_ip_size;
142 __le16 bitfields1;
143#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
144#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
145#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
146#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
147#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
148#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
149#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
150#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
151#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
152#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
153#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
154#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
155#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
156#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
157#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
158#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
159#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
160#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
161#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
162#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
163 __le16 bitfields2;
164#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
165#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
166#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
167#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
168};
169
170/* Firmware data for L2-EDPM packet. */
171struct eth_edpm_fw_data {
172 struct eth_tx_data_1st_bd data_1st_bd;
173 struct eth_tx_data_2nd_bd data_2nd_bd;
174 __le32 reserved;
175};
176
177struct eth_fast_path_cqe_fw_debug {
178 __le16 reserved2;
179};
180
181/* tunneling parsing flags */
182struct eth_tunnel_parsing_flags {
183 u8 flags;
184#define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
185#define ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0
186#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1
187#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
188#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3
189#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3
190#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1
191#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5
192#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1
193#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6
194#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1
195#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
196};
197
198/* PMD flow control bits */
199struct eth_pmd_flow_flags {
200 u8 flags;
201#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1
202#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
203#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1
204#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
205#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
206#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
207};
208
209/* Regular ETH Rx FP CQE. */
210struct eth_fast_path_rx_reg_cqe {
211 u8 type;
212 u8 bitfields;
213#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
214#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
215#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
216#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
217#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
218#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
219 __le16 pkt_len;
220 struct parsing_and_err_flags pars_flags;
221 __le16 vlan_tag;
222 __le32 rss_hash;
223 __le16 len_on_first_bd;
224 u8 placement_offset;
225 struct eth_tunnel_parsing_flags tunnel_pars_flags;
226 u8 bd_num;
227 u8 reserved[9];
228 struct eth_fast_path_cqe_fw_debug fw_debug;
229 u8 reserved1[3];
230 struct eth_pmd_flow_flags pmd_flags;
231};
232
233/* TPA-continue ETH Rx FP CQE. */
234struct eth_fast_path_rx_tpa_cont_cqe {
235 u8 type;
236 u8 tpa_agg_index;
237 __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
238 u8 reserved;
239 u8 reserved1;
240 __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
241 u8 reserved3[3];
242 struct eth_pmd_flow_flags pmd_flags;
243};
244
245/* TPA-end ETH Rx FP CQE. */
246struct eth_fast_path_rx_tpa_end_cqe {
247 u8 type;
248 u8 tpa_agg_index;
249 __le16 total_packet_len;
250 u8 num_of_bds;
251 u8 end_reason;
252 __le16 num_of_coalesced_segs;
253 __le32 ts_delta;
254 __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
255 __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE];
256 __le16 reserved1;
257 u8 reserved2;
258 struct eth_pmd_flow_flags pmd_flags;
259};
260
261/* TPA-start ETH Rx FP CQE. */
262struct eth_fast_path_rx_tpa_start_cqe {
263 u8 type;
264 u8 bitfields;
265#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
266#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
267#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
268#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
269#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
270#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
271 __le16 seg_len;
272 struct parsing_and_err_flags pars_flags;
273 __le16 vlan_tag;
274 __le32 rss_hash;
275 __le16 len_on_first_bd;
276 u8 placement_offset;
277 struct eth_tunnel_parsing_flags tunnel_pars_flags;
278 u8 tpa_agg_index;
279 u8 header_len;
280 __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
281 struct eth_fast_path_cqe_fw_debug fw_debug;
282 u8 reserved;
283 struct eth_pmd_flow_flags pmd_flags;
284};
285
286/* The L4 pseudo checksum mode for Ethernet */
287enum eth_l4_pseudo_checksum_mode {
288 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH,
289 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH,
290 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
291};
292
293struct eth_rx_bd {
294 struct regpair addr;
295};
296
297/* regular ETH Rx SP CQE */
298struct eth_slow_path_rx_cqe {
299 u8 type;
300 u8 ramrod_cmd_id;
301 u8 error_flag;
302 u8 reserved[25];
303 __le16 echo;
304 u8 reserved1;
305 struct eth_pmd_flow_flags pmd_flags;
306};
307
308/* union for all ETH Rx CQE types */
309union eth_rx_cqe {
310 struct eth_fast_path_rx_reg_cqe fast_path_regular;
311 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
312 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
313 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
314 struct eth_slow_path_rx_cqe slow_path;
315};
316
317/* ETH Rx CQE type */
318enum eth_rx_cqe_type {
319 ETH_RX_CQE_TYPE_UNUSED,
320 ETH_RX_CQE_TYPE_REGULAR,
321 ETH_RX_CQE_TYPE_SLOW_PATH,
322 ETH_RX_CQE_TYPE_TPA_START,
323 ETH_RX_CQE_TYPE_TPA_CONT,
324 ETH_RX_CQE_TYPE_TPA_END,
325 MAX_ETH_RX_CQE_TYPE
326};
327
328struct eth_rx_pmd_cqe {
329 union eth_rx_cqe cqe;
330 u8 reserved[ETH_RX_CQE_GAP];
331};
332
333enum eth_rx_tunn_type {
334 ETH_RX_NO_TUNN,
335 ETH_RX_TUNN_GENEVE,
336 ETH_RX_TUNN_GRE,
337 ETH_RX_TUNN_VXLAN,
338 MAX_ETH_RX_TUNN_TYPE
339};
340
341/* Aggregation end reason. */
342enum eth_tpa_end_reason {
343 ETH_AGG_END_UNUSED,
344 ETH_AGG_END_SP_UPDATE,
345 ETH_AGG_END_MAX_LEN,
346 ETH_AGG_END_LAST_SEG,
347 ETH_AGG_END_TIMEOUT,
348 ETH_AGG_END_NOT_CONSISTENT,
349 ETH_AGG_END_OUT_OF_ORDER,
350 ETH_AGG_END_NON_TPA_SEG,
351 MAX_ETH_TPA_END_REASON
352};
353
354/* The first tx bd of a given packet */
355struct eth_tx_1st_bd {
356 struct regpair addr;
357 __le16 nbytes;
358 struct eth_tx_data_1st_bd data;
359};
360
361/* The second tx bd of a given packet */
362struct eth_tx_2nd_bd {
363 struct regpair addr;
364 __le16 nbytes;
365 struct eth_tx_data_2nd_bd data;
366};
367
368/* The parsing information data for the third tx bd of a given packet. */
369struct eth_tx_data_3rd_bd {
370 __le16 lso_mss;
371 __le16 bitfields;
372#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
373#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
374#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
375#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
376#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
377#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
378#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
379#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
380 u8 tunn_l4_hdr_start_offset_w;
381 u8 tunn_hdr_size_w;
382};
383
384/* The third tx bd of a given packet */
385struct eth_tx_3rd_bd {
386 struct regpair addr;
387 __le16 nbytes;
388 struct eth_tx_data_3rd_bd data;
389};
390
391/* Complementary information for the regular tx bd of a given packet. */
392struct eth_tx_data_bd {
393 __le16 reserved0;
394 __le16 bitfields;
395#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
396#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
397#define ETH_TX_DATA_BD_START_BD_MASK 0x1
398#define ETH_TX_DATA_BD_START_BD_SHIFT 8
399#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
400#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
401 __le16 reserved3;
402};
403
404/* The common non-special TX BD ring element */
405struct eth_tx_bd {
406 struct regpair addr;
407 __le16 nbytes;
408 struct eth_tx_data_bd data;
409};
410
411union eth_tx_bd_types {
412 struct eth_tx_1st_bd first_bd;
413 struct eth_tx_2nd_bd second_bd;
414 struct eth_tx_3rd_bd third_bd;
415 struct eth_tx_bd reg_bd;
416};
417
418/* Mstorm Queue Zone */
419enum eth_tx_tunn_type {
420 ETH_TX_TUNN_GENEVE,
421 ETH_TX_TUNN_TTAG,
422 ETH_TX_TUNN_GRE,
423 ETH_TX_TUNN_VXLAN,
424 MAX_ETH_TX_TUNN_TYPE
425};
426
427/* Ystorm Queue Zone */
428struct xstorm_eth_queue_zone {
429 struct coalescing_timeset int_coalescing_timeset;
430 u8 reserved[7];
431};
432
433/* ETH doorbell data */
434struct eth_db_data {
435 u8 params;
436#define ETH_DB_DATA_DEST_MASK 0x3
437#define ETH_DB_DATA_DEST_SHIFT 0
438#define ETH_DB_DATA_AGG_CMD_MASK 0x3
439#define ETH_DB_DATA_AGG_CMD_SHIFT 2
440#define ETH_DB_DATA_BYPASS_EN_MASK 0x1
441#define ETH_DB_DATA_BYPASS_EN_SHIFT 4
442#define ETH_DB_DATA_RESERVED_MASK 0x1
443#define ETH_DB_DATA_RESERVED_SHIFT 5
444#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
445#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
446 u8 agg_flags;
447 __le16 bd_prod;
448};
449
450#endif /* __ETH_COMMON__ */