Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1#ifndef _ASM_X86_HYPERV_H
2#define _ASM_X86_HYPERV_H
3
4#include <linux/types.h>
5
6/*
7 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
8 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
9 */
10#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000
11#define HYPERV_CPUID_INTERFACE 0x40000001
12#define HYPERV_CPUID_VERSION 0x40000002
13#define HYPERV_CPUID_FEATURES 0x40000003
14#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004
15#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005
16
17#define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000
18#define HYPERV_CPUID_MIN 0x40000005
19#define HYPERV_CPUID_MAX 0x4000ffff
20
21/*
22 * Feature identification. EAX indicates which features are available
23 * to the partition based upon the current partition privileges.
24 */
25
26/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
27#define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0)
28/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
29#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1)
30/* Partition reference TSC MSR is available */
31#define HV_X64_MSR_REFERENCE_TSC_AVAILABLE (1 << 9)
32
33/* A partition's reference time stamp counter (TSC) page */
34#define HV_X64_MSR_REFERENCE_TSC 0x40000021
35
36/*
37 * There is a single feature flag that signifies the presence of the MSR
38 * that can be used to retrieve both the local APIC Timer frequency as
39 * well as the TSC frequency.
40 */
41
42/* Local APIC timer frequency MSR (HV_X64_MSR_APIC_FREQUENCY) is available */
43#define HV_X64_MSR_APIC_FREQUENCY_AVAILABLE (1 << 11)
44
45/* TSC frequency MSR (HV_X64_MSR_TSC_FREQUENCY) is available */
46#define HV_X64_MSR_TSC_FREQUENCY_AVAILABLE (1 << 11)
47
48/*
49 * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
50 * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
51 */
52#define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2)
53/*
54 * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
55 * HV_X64_MSR_STIMER3_COUNT) available
56 */
57#define HV_X64_MSR_SYNTIMER_AVAILABLE (1 << 3)
58/*
59 * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
60 * are available
61 */
62#define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4)
63/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
64#define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5)
65/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
66#define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6)
67/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
68#define HV_X64_MSR_RESET_AVAILABLE (1 << 7)
69 /*
70 * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
71 * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
72 * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
73 */
74#define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8)
75
76/* Crash MSR available */
77#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
78
79/*
80 * Feature identification: EBX indicates which flags were specified at
81 * partition creation. The format is the same as the partition creation
82 * flag structure defined in section Partition Creation Flags.
83 */
84#define HV_X64_CREATE_PARTITIONS (1 << 0)
85#define HV_X64_ACCESS_PARTITION_ID (1 << 1)
86#define HV_X64_ACCESS_MEMORY_POOL (1 << 2)
87#define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3)
88#define HV_X64_POST_MESSAGES (1 << 4)
89#define HV_X64_SIGNAL_EVENTS (1 << 5)
90#define HV_X64_CREATE_PORT (1 << 6)
91#define HV_X64_CONNECT_PORT (1 << 7)
92#define HV_X64_ACCESS_STATS (1 << 8)
93#define HV_X64_DEBUGGING (1 << 11)
94#define HV_X64_CPU_POWER_MANAGEMENT (1 << 12)
95#define HV_X64_CONFIGURE_PROFILER (1 << 13)
96
97/*
98 * Feature identification. EDX indicates which miscellaneous features
99 * are available to the partition.
100 */
101/* The MWAIT instruction is available (per section MONITOR / MWAIT) */
102#define HV_X64_MWAIT_AVAILABLE (1 << 0)
103/* Guest debugging support is available */
104#define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1)
105/* Performance Monitor support is available*/
106#define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2)
107/* Support for physical CPU dynamic partitioning events is available*/
108#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3)
109/*
110 * Support for passing hypercall input parameter block via XMM
111 * registers is available
112 */
113#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4)
114/* Support for a virtual guest idle state is available */
115#define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5)
116/* Guest crash data handler available */
117#define HV_X64_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
118
119/*
120 * Implementation recommendations. Indicates which behaviors the hypervisor
121 * recommends the OS implement for optimal performance.
122 */
123 /*
124 * Recommend using hypercall for address space switches rather
125 * than MOV to CR3 instruction
126 */
127#define HV_X64_AS_SWITCH_RECOMMENDED (1 << 0)
128/* Recommend using hypercall for local TLB flushes rather
129 * than INVLPG or MOV to CR3 instructions */
130#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1)
131/*
132 * Recommend using hypercall for remote TLB flushes rather
133 * than inter-processor interrupts
134 */
135#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2)
136/*
137 * Recommend using MSRs for accessing APIC registers
138 * EOI, ICR and TPR rather than their memory-mapped counterparts
139 */
140#define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3)
141/* Recommend using the hypervisor-provided MSR to initiate a system RESET */
142#define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4)
143/*
144 * Recommend using relaxed timing for this partition. If used,
145 * the VM should disable any watchdog timeouts that rely on the
146 * timely delivery of external interrupts
147 */
148#define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5)
149
150/*
151 * Virtual APIC support
152 */
153#define HV_X64_DEPRECATING_AEOI_RECOMMENDED (1 << 9)
154
155/*
156 * Crash notification flag.
157 */
158#define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63)
159
160/* MSR used to identify the guest OS. */
161#define HV_X64_MSR_GUEST_OS_ID 0x40000000
162
163/* MSR used to setup pages used to communicate with the hypervisor. */
164#define HV_X64_MSR_HYPERCALL 0x40000001
165
166/* MSR used to provide vcpu index */
167#define HV_X64_MSR_VP_INDEX 0x40000002
168
169/* MSR used to reset the guest OS. */
170#define HV_X64_MSR_RESET 0x40000003
171
172/* MSR used to provide vcpu runtime in 100ns units */
173#define HV_X64_MSR_VP_RUNTIME 0x40000010
174
175/* MSR used to read the per-partition time reference counter */
176#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
177
178/* MSR used to retrieve the TSC frequency */
179#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
180
181/* MSR used to retrieve the local APIC timer frequency */
182#define HV_X64_MSR_APIC_FREQUENCY 0x40000023
183
184/* Define the virtual APIC registers */
185#define HV_X64_MSR_EOI 0x40000070
186#define HV_X64_MSR_ICR 0x40000071
187#define HV_X64_MSR_TPR 0x40000072
188#define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073
189
190/* Define synthetic interrupt controller model specific registers. */
191#define HV_X64_MSR_SCONTROL 0x40000080
192#define HV_X64_MSR_SVERSION 0x40000081
193#define HV_X64_MSR_SIEFP 0x40000082
194#define HV_X64_MSR_SIMP 0x40000083
195#define HV_X64_MSR_EOM 0x40000084
196#define HV_X64_MSR_SINT0 0x40000090
197#define HV_X64_MSR_SINT1 0x40000091
198#define HV_X64_MSR_SINT2 0x40000092
199#define HV_X64_MSR_SINT3 0x40000093
200#define HV_X64_MSR_SINT4 0x40000094
201#define HV_X64_MSR_SINT5 0x40000095
202#define HV_X64_MSR_SINT6 0x40000096
203#define HV_X64_MSR_SINT7 0x40000097
204#define HV_X64_MSR_SINT8 0x40000098
205#define HV_X64_MSR_SINT9 0x40000099
206#define HV_X64_MSR_SINT10 0x4000009A
207#define HV_X64_MSR_SINT11 0x4000009B
208#define HV_X64_MSR_SINT12 0x4000009C
209#define HV_X64_MSR_SINT13 0x4000009D
210#define HV_X64_MSR_SINT14 0x4000009E
211#define HV_X64_MSR_SINT15 0x4000009F
212
213/*
214 * Synthetic Timer MSRs. Four timers per vcpu.
215 */
216#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0
217#define HV_X64_MSR_STIMER0_COUNT 0x400000B1
218#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2
219#define HV_X64_MSR_STIMER1_COUNT 0x400000B3
220#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4
221#define HV_X64_MSR_STIMER2_COUNT 0x400000B5
222#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6
223#define HV_X64_MSR_STIMER3_COUNT 0x400000B7
224
225/* Hyper-V guest crash notification MSR's */
226#define HV_X64_MSR_CRASH_P0 0x40000100
227#define HV_X64_MSR_CRASH_P1 0x40000101
228#define HV_X64_MSR_CRASH_P2 0x40000102
229#define HV_X64_MSR_CRASH_P3 0x40000103
230#define HV_X64_MSR_CRASH_P4 0x40000104
231#define HV_X64_MSR_CRASH_CTL 0x40000105
232#define HV_X64_MSR_CRASH_CTL_NOTIFY (1ULL << 63)
233#define HV_X64_MSR_CRASH_PARAMS \
234 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
235
236#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001
237#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
238#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \
239 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
240
241/* Declare the various hypercall operations. */
242#define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008
243#define HVCALL_POST_MESSAGE 0x005c
244#define HVCALL_SIGNAL_EVENT 0x005d
245
246#define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE 0x00000001
247#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT 12
248#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \
249 (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
250
251#define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001
252#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12
253
254#define HV_PROCESSOR_POWER_STATE_C0 0
255#define HV_PROCESSOR_POWER_STATE_C1 1
256#define HV_PROCESSOR_POWER_STATE_C2 2
257#define HV_PROCESSOR_POWER_STATE_C3 3
258
259/* hypercall status code */
260#define HV_STATUS_SUCCESS 0
261#define HV_STATUS_INVALID_HYPERCALL_CODE 2
262#define HV_STATUS_INVALID_HYPERCALL_INPUT 3
263#define HV_STATUS_INVALID_ALIGNMENT 4
264#define HV_STATUS_INSUFFICIENT_MEMORY 11
265#define HV_STATUS_INVALID_CONNECTION_ID 18
266#define HV_STATUS_INSUFFICIENT_BUFFERS 19
267
268typedef struct _HV_REFERENCE_TSC_PAGE {
269 __u32 tsc_sequence;
270 __u32 res1;
271 __u64 tsc_scale;
272 __s64 tsc_offset;
273} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
274
275/* Define the number of synthetic interrupt sources. */
276#define HV_SYNIC_SINT_COUNT (16)
277/* Define the expected SynIC version. */
278#define HV_SYNIC_VERSION_1 (0x1)
279
280#define HV_SYNIC_CONTROL_ENABLE (1ULL << 0)
281#define HV_SYNIC_SIMP_ENABLE (1ULL << 0)
282#define HV_SYNIC_SIEFP_ENABLE (1ULL << 0)
283#define HV_SYNIC_SINT_MASKED (1ULL << 16)
284#define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17)
285#define HV_SYNIC_SINT_VECTOR_MASK (0xFF)
286
287#define HV_SYNIC_STIMER_COUNT (4)
288
289/* Define synthetic interrupt controller message constants. */
290#define HV_MESSAGE_SIZE (256)
291#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240)
292#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30)
293
294/* Define hypervisor message types. */
295enum hv_message_type {
296 HVMSG_NONE = 0x00000000,
297
298 /* Memory access messages. */
299 HVMSG_UNMAPPED_GPA = 0x80000000,
300 HVMSG_GPA_INTERCEPT = 0x80000001,
301
302 /* Timer notification messages. */
303 HVMSG_TIMER_EXPIRED = 0x80000010,
304
305 /* Error messages. */
306 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
307 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021,
308 HVMSG_UNSUPPORTED_FEATURE = 0x80000022,
309
310 /* Trace buffer complete messages. */
311 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040,
312
313 /* Platform-specific processor intercept messages. */
314 HVMSG_X64_IOPORT_INTERCEPT = 0x80010000,
315 HVMSG_X64_MSR_INTERCEPT = 0x80010001,
316 HVMSG_X64_CPUID_INTERCEPT = 0x80010002,
317 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003,
318 HVMSG_X64_APIC_EOI = 0x80010004,
319 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005
320};
321
322/* Define synthetic interrupt controller message flags. */
323union hv_message_flags {
324 __u8 asu8;
325 struct {
326 __u8 msg_pending:1;
327 __u8 reserved:7;
328 };
329};
330
331/* Define port identifier type. */
332union hv_port_id {
333 __u32 asu32;
334 struct {
335 __u32 id:24;
336 __u32 reserved:8;
337 } u;
338};
339
340/* Define synthetic interrupt controller message header. */
341struct hv_message_header {
342 __u32 message_type;
343 __u8 payload_size;
344 union hv_message_flags message_flags;
345 __u8 reserved[2];
346 union {
347 __u64 sender;
348 union hv_port_id port;
349 };
350};
351
352/* Define synthetic interrupt controller message format. */
353struct hv_message {
354 struct hv_message_header header;
355 union {
356 __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
357 } u;
358};
359
360/* Define the synthetic interrupt message page layout. */
361struct hv_message_page {
362 struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
363};
364
365/* Define timer message payload structure. */
366struct hv_timer_message_payload {
367 __u32 timer_index;
368 __u32 reserved;
369 __u64 expiration_time; /* When the timer expired */
370 __u64 delivery_time; /* When the message was delivered */
371};
372
373#define HV_STIMER_ENABLE (1ULL << 0)
374#define HV_STIMER_PERIODIC (1ULL << 1)
375#define HV_STIMER_LAZY (1ULL << 2)
376#define HV_STIMER_AUTOENABLE (1ULL << 3)
377#define HV_STIMER_SINT(config) (__u8)(((config) >> 16) & 0x0F)
378
379#endif