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1One-register-per-pin type device tree based pinctrl driver
2
3Required properties:
4- compatible : "pinctrl-single" or "pinconf-single".
5 "pinctrl-single" means that pinconf isn't supported.
6 "pinconf-single" means that generic pinconf is supported.
7
8- reg : offset and length of the register set for the mux registers
9
10- #pinctrl-cells : number of cells in addition to the index, set to 1
11 for pinctrl-single,pins and 2 for pinctrl-single,bits
12
13- pinctrl-single,register-width : pinmux register access width in bits
14
15- pinctrl-single,function-mask : mask of allowed pinmux function bits
16 in the pinmux register
17
18Optional properties:
19- pinctrl-single,function-off : function off mode for disabled state if
20 available and same for all registers; if not specified, disabling of
21 pin functions is ignored
22
23- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
24 more than one pin, for which "pinctrl-single,function-mask" property specifies
25 position mask of pin.
26
27- pinctrl-single,drive-strength : array of value that are used to configure
28 drive strength in the pinmux register. They're value of drive strength
29 current and drive strength mask.
30
31 /* drive strength current, mask */
32 pinctrl-single,power-source = <0x30 0xf0>;
33
34- pinctrl-single,bias-pullup : array of value that are used to configure the
35 input bias pullup in the pinmux register.
36
37 /* input, enabled pullup bits, disabled pullup bits, mask */
38 pinctrl-single,bias-pullup = <0 1 0 1>;
39
40- pinctrl-single,bias-pulldown : array of value that are used to configure the
41 input bias pulldown in the pinmux register.
42
43 /* input, enabled pulldown bits, disabled pulldown bits, mask */
44 pinctrl-single,bias-pulldown = <2 2 0 2>;
45
46 * Two bits to control input bias pullup and pulldown: User should use
47 pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
48 pullup, and the other one bit means pulldown.
49 * Three bits to control input bias enable, pullup and pulldown. User should
50 use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
51 enable bit should be included in pullup or pulldown bits.
52 * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
53 pinctrl-single,bias-disable. Because pinctrl single driver could implement
54 it by calling pulldown, pullup disabled.
55
56- pinctrl-single,input-schmitt : array of value that are used to configure
57 input schmitt in the pinmux register. In some silicons, there're two input
58 schmitt value (rising-edge & falling-edge) in the pinmux register.
59
60 /* input schmitt value, mask */
61 pinctrl-single,input-schmitt = <0x30 0x70>;
62
63- pinctrl-single,input-schmitt-enable : array of value that are used to
64 configure input schmitt enable or disable in the pinmux register.
65
66 /* input, enable bits, disable bits, mask */
67 pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
68
69- pinctrl-single,low-power-mode : array of value that are used to configure
70 low power mode of this pin. For some silicons, the low power mode will
71 control the output of the pin when the pad including the pin enter low
72 power mode.
73 /* low power mode value, mask */
74 pinctrl-single,low-power-mode = <0x288 0x388>;
75
76- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
77 range. They're value of subnode phandle, pin base in pinctrl device, pin
78 number in this range, GPIO function value of this GPIO range.
79 The number of parameters is depend on #pinctrl-single,gpio-range-cells
80 property.
81
82 /* pin base, nr pins & gpio function */
83 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
84
85- interrupt-controller : standard interrupt controller binding if using
86 interrupts for wake-up events for example. In this case pinctrl-single
87 is set up as a chained interrupt controller and the wake-up interrupts
88 can be requested by the drivers using request_irq().
89
90- #interrupt-cells : standard interrupt binding if using interrupts
91
92This driver assumes that there is only one register for each pin (unless the
93pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
94specified in the pinctrl-bindings.txt document in this directory.
95
96The pin configuration nodes for pinctrl-single are specified as pinctrl
97register offset and value pairs using pinctrl-single,pins. Only the bits
98specified in pinctrl-single,function-mask are updated. For example, setting
99a pin for a device could be done with:
100
101 pinctrl-single,pins = <0xdc 0x118>;
102
103Where 0xdc is the offset from the pinctrl register base address for the
104device pinctrl register, and 0x118 contains the desired value of the
105pinctrl register. See the device example and static board pins example
106below for more information.
107
108In case when one register changes more than one pin's mux the
109pinctrl-single,bits need to be used which takes three parameters:
110
111 pinctrl-single,bits = <0xdc 0x18 0xff>;
112
113Where 0xdc is the offset from the pinctrl register base address for the
114device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
115be used when applying this change to the register.
116
117
118Optional sub-node: In case some pins could be configured as GPIO in the pinmux
119register, those pins could be defined as a GPIO range. This sub-node is required
120by pinctrl-single,gpio-range property.
121
122Required properties in sub-node:
123- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
124 pinctrl-single,gpio-range property.
125
126 range: gpio-range {
127 #pinctrl-single,gpio-range-cells = <3>;
128 };
129
130
131Example:
132
133/* SoC common file */
134
135/* first controller instance for pins in core domain */
136pmx_core: pinmux@4a100040 {
137 compatible = "pinctrl-single";
138 reg = <0x4a100040 0x0196>;
139 #address-cells = <1>;
140 #size-cells = <0>;
141 #interrupt-cells = <1>;
142 interrupt-controller;
143 pinctrl-single,register-width = <16>;
144 pinctrl-single,function-mask = <0xffff>;
145};
146
147/* second controller instance for pins in wkup domain */
148pmx_wkup: pinmux@4a31e040 {
149 compatible = "pinctrl-single";
150 reg = <0x4a31e040 0x0038>;
151 #address-cells = <1>;
152 #size-cells = <0>;
153 #interrupt-cells = <1>;
154 interrupt-controller;
155 pinctrl-single,register-width = <16>;
156 pinctrl-single,function-mask = <0xffff>;
157};
158
159control_devconf0: pinmux@48002274 {
160 compatible = "pinctrl-single";
161 reg = <0x48002274 4>; /* Single register */
162 #address-cells = <1>;
163 #size-cells = <0>;
164 pinctrl-single,bit-per-mux;
165 pinctrl-single,register-width = <32>;
166 pinctrl-single,function-mask = <0x5F>;
167};
168
169/* third controller instance for pins in gpio domain */
170pmx_gpio: pinmux@d401e000 {
171 compatible = "pinconf-single";
172 reg = <0xd401e000 0x0330>;
173 #address-cells = <1>;
174 #size-cells = <1>;
175 ranges;
176
177 pinctrl-single,register-width = <32>;
178 pinctrl-single,function-mask = <7>;
179
180 /* sparse GPIO range could be supported */
181 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
182 &range 12 1 0 &range 13 29 1
183 &range 43 1 0 &range 44 49 1
184 &range 94 1 1 &range 96 2 1>;
185
186 range: gpio-range {
187 #pinctrl-single,gpio-range-cells = <3>;
188 };
189};
190
191
192/* board specific .dts file */
193
194&pmx_core {
195
196 /*
197 * map all board specific static pins enabled by the pinctrl driver
198 * itself during the boot (or just set them up in the bootloader)
199 */
200 pinctrl-names = "default";
201 pinctrl-0 = <&board_pins>;
202
203 board_pins: pinmux_board_pins {
204 pinctrl-single,pins = <
205 0x6c 0xf
206 0x6e 0xf
207 0x70 0xf
208 0x72 0xf
209 >;
210 };
211
212 uart0_pins: pinmux_uart0_pins {
213 pinctrl-single,pins = <
214 0x208 0 /* UART0_RXD (IOCFG138) */
215 0x20c 0 /* UART0_TXD (IOCFG139) */
216 >;
217 pinctrl-single,bias-pulldown = <0 2 2>;
218 pinctrl-single,bias-pullup = <0 1 1>;
219 };
220
221 /* map uart2 pins */
222 uart2_pins: pinmux_uart2_pins {
223 pinctrl-single,pins = <
224 0xd8 0x118
225 0xda 0
226 0xdc 0x118
227 0xde 0
228 >;
229 };
230};
231
232&control_devconf0 {
233 mcbsp1_pins: pinmux_mcbsp1_pins {
234 pinctrl-single,bits = <
235 0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
236 >;
237 };
238
239 mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
240 pinctrl-single,bits = <
241 0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
242 >;
243 };
244
245};
246
247&uart1 {
248 pinctrl-names = "default";
249 pinctrl-0 = <&uart0_pins>;
250};
251
252&uart2 {
253 pinctrl-names = "default";
254 pinctrl-0 = <&uart2_pins>;
255};