tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#ifndef _CGS_COMMON_H
25#define _CGS_COMMON_H
26
27#include "amd_shared.h"
28
29struct cgs_device;
30
31/**
32 * enum cgs_gpu_mem_type - GPU memory types
33 */
34enum cgs_gpu_mem_type {
35 CGS_GPU_MEM_TYPE__VISIBLE_FB,
36 CGS_GPU_MEM_TYPE__INVISIBLE_FB,
37 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
38 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB,
39 CGS_GPU_MEM_TYPE__GART_CACHEABLE,
40 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
41};
42
43/**
44 * enum cgs_ind_reg - Indirect register spaces
45 */
46enum cgs_ind_reg {
47 CGS_IND_REG__MMIO,
48 CGS_IND_REG__PCIE,
49 CGS_IND_REG__SMC,
50 CGS_IND_REG__UVD_CTX,
51 CGS_IND_REG__DIDT,
52 CGS_IND_REG_GC_CAC,
53 CGS_IND_REG__AUDIO_ENDPT
54};
55
56/**
57 * enum cgs_engine - Engines that can be statically power-gated
58 */
59enum cgs_engine {
60 CGS_ENGINE__UVD,
61 CGS_ENGINE__VCE,
62 CGS_ENGINE__VP8,
63 CGS_ENGINE__ACP_DMA,
64 CGS_ENGINE__ACP_DSP0,
65 CGS_ENGINE__ACP_DSP1,
66 CGS_ENGINE__ISP,
67 /* ... */
68};
69
70/*
71 * enum cgs_ucode_id - Firmware types for different IPs
72 */
73enum cgs_ucode_id {
74 CGS_UCODE_ID_SMU = 0,
75 CGS_UCODE_ID_SMU_SK,
76 CGS_UCODE_ID_SDMA0,
77 CGS_UCODE_ID_SDMA1,
78 CGS_UCODE_ID_CP_CE,
79 CGS_UCODE_ID_CP_PFP,
80 CGS_UCODE_ID_CP_ME,
81 CGS_UCODE_ID_CP_MEC,
82 CGS_UCODE_ID_CP_MEC_JT1,
83 CGS_UCODE_ID_CP_MEC_JT2,
84 CGS_UCODE_ID_GMCON_RENG,
85 CGS_UCODE_ID_RLC_G,
86 CGS_UCODE_ID_STORAGE,
87 CGS_UCODE_ID_MAXIMUM,
88};
89
90enum cgs_system_info_id {
91 CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
92 CGS_SYSTEM_INFO_PCIE_GEN_INFO,
93 CGS_SYSTEM_INFO_PCIE_MLW,
94 CGS_SYSTEM_INFO_PCIE_DEV,
95 CGS_SYSTEM_INFO_PCIE_REV,
96 CGS_SYSTEM_INFO_CG_FLAGS,
97 CGS_SYSTEM_INFO_PG_FLAGS,
98 CGS_SYSTEM_INFO_GFX_CU_INFO,
99 CGS_SYSTEM_INFO_GFX_SE_INFO,
100 CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID,
101 CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID,
102 CGS_SYSTEM_INFO_ID_MAXIMUM,
103};
104
105struct cgs_system_info {
106 uint64_t size;
107 enum cgs_system_info_id info_id;
108 union {
109 void *ptr;
110 uint64_t value;
111 };
112 uint64_t padding[13];
113};
114
115/*
116 * enum cgs_resource_type - GPU resource type
117 */
118enum cgs_resource_type {
119 CGS_RESOURCE_TYPE_MMIO = 0,
120 CGS_RESOURCE_TYPE_FB,
121 CGS_RESOURCE_TYPE_IO,
122 CGS_RESOURCE_TYPE_DOORBELL,
123 CGS_RESOURCE_TYPE_ROM,
124};
125
126/**
127 * struct cgs_firmware_info - Firmware information
128 */
129struct cgs_firmware_info {
130 uint16_t version;
131 uint16_t fw_version;
132 uint16_t feature_version;
133 uint32_t image_size;
134 uint64_t mc_addr;
135
136 /* only for smc firmware */
137 uint32_t ucode_start_address;
138
139 void *kptr;
140 bool is_kicker;
141};
142
143struct cgs_mode_info {
144 uint32_t refresh_rate;
145 uint32_t ref_clock;
146 uint32_t vblank_time_us;
147};
148
149struct cgs_display_info {
150 uint32_t display_count;
151 uint32_t active_display_mask;
152 struct cgs_mode_info *mode_info;
153};
154
155typedef unsigned long cgs_handle_t;
156
157#define CGS_ACPI_METHOD_ATCS 0x53435441
158#define CGS_ACPI_METHOD_ATIF 0x46495441
159#define CGS_ACPI_METHOD_ATPX 0x58505441
160#define CGS_ACPI_FIELD_METHOD_NAME 0x00000001
161#define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002
162#define CGS_ACPI_MAX_BUFFER_SIZE 256
163#define CGS_ACPI_TYPE_ANY 0x00
164#define CGS_ACPI_TYPE_INTEGER 0x01
165#define CGS_ACPI_TYPE_STRING 0x02
166#define CGS_ACPI_TYPE_BUFFER 0x03
167#define CGS_ACPI_TYPE_PACKAGE 0x04
168
169struct cgs_acpi_method_argument {
170 uint32_t type;
171 uint32_t data_length;
172 union{
173 uint32_t value;
174 void *pointer;
175 };
176};
177
178struct cgs_acpi_method_info {
179 uint32_t size;
180 uint32_t field;
181 uint32_t input_count;
182 uint32_t name;
183 struct cgs_acpi_method_argument *pinput_argument;
184 uint32_t output_count;
185 struct cgs_acpi_method_argument *poutput_argument;
186 uint32_t padding[9];
187};
188
189/**
190 * cgs_alloc_gpu_mem() - Allocate GPU memory
191 * @cgs_device: opaque device handle
192 * @type: memory type
193 * @size: size in bytes
194 * @align: alignment in bytes
195 * @min_offset: minimum offset from start of heap
196 * @max_offset: maximum offset from start of heap
197 * @handle: memory handle (output)
198 *
199 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
200 * memory allocation. This guarantees that the MC address returned by
201 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous
202 * FB memory types may be GART mapped depending on memory
203 * fragmentation and memory allocator policies.
204 *
205 * If min/max_offset are non-0, the allocation will be forced to
206 * reside between these offsets in its respective memory heap. The
207 * base address that the offset relates to, depends on the memory
208 * type.
209 *
210 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address
211 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address
212 * - others: undefined, don't use with max_offset
213 *
214 * Return: 0 on success, -errno otherwise
215 */
216typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
217 uint64_t size, uint64_t align,
218 uint64_t min_offset, uint64_t max_offset,
219 cgs_handle_t *handle);
220
221/**
222 * cgs_free_gpu_mem() - Free GPU memory
223 * @cgs_device: opaque device handle
224 * @handle: memory handle returned by alloc or import
225 *
226 * Return: 0 on success, -errno otherwise
227 */
228typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
229
230/**
231 * cgs_gmap_gpu_mem() - GPU-map GPU memory
232 * @cgs_device: opaque device handle
233 * @handle: memory handle returned by alloc or import
234 * @mcaddr: MC address (output)
235 *
236 * Ensures that a buffer is GPU accessible and returns its MC address.
237 *
238 * Return: 0 on success, -errno otherwise
239 */
240typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
241 uint64_t *mcaddr);
242
243/**
244 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory
245 * @cgs_device: opaque device handle
246 * @handle: memory handle returned by alloc or import
247 *
248 * Allows the buffer to be migrated while it's not used by the GPU.
249 *
250 * Return: 0 on success, -errno otherwise
251 */
252typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
253
254/**
255 * cgs_kmap_gpu_mem() - Kernel-map GPU memory
256 *
257 * @cgs_device: opaque device handle
258 * @handle: memory handle returned by alloc or import
259 * @map: Kernel virtual address the memory was mapped to (output)
260 *
261 * Return: 0 on success, -errno otherwise
262 */
263typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
264 void **map);
265
266/**
267 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory
268 * @cgs_device: opaque device handle
269 * @handle: memory handle returned by alloc or import
270 *
271 * Return: 0 on success, -errno otherwise
272 */
273typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
274
275/**
276 * cgs_read_register() - Read an MMIO register
277 * @cgs_device: opaque device handle
278 * @offset: register offset
279 *
280 * Return: register value
281 */
282typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
283
284/**
285 * cgs_write_register() - Write an MMIO register
286 * @cgs_device: opaque device handle
287 * @offset: register offset
288 * @value: register value
289 */
290typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
291 uint32_t value);
292
293/**
294 * cgs_read_ind_register() - Read an indirect register
295 * @cgs_device: opaque device handle
296 * @offset: register offset
297 *
298 * Return: register value
299 */
300typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
301 unsigned index);
302
303/**
304 * cgs_write_ind_register() - Write an indirect register
305 * @cgs_device: opaque device handle
306 * @offset: register offset
307 * @value: register value
308 */
309typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
310 unsigned index, uint32_t value);
311
312/**
313 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
314 * @cgs_device: opaque device handle
315 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL)
316 * @size: size of the region
317 * @offset: offset from the start of the region
318 * @resource_base: base address (not including offset) returned
319 *
320 * Return: 0 on success, -errno otherwise
321 */
322typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device,
323 enum cgs_resource_type resource_type,
324 uint64_t size,
325 uint64_t offset,
326 uint64_t *resource_base);
327
328/**
329 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
330 * @cgs_device: opaque device handle
331 * @table: data table index
332 * @size: size of the table (output, may be NULL)
333 * @frev: table format revision (output, may be NULL)
334 * @crev: table content revision (output, may be NULL)
335 *
336 * Return: Pointer to start of the table, or NULL on failure
337 */
338typedef const void *(*cgs_atom_get_data_table_t)(
339 struct cgs_device *cgs_device, unsigned table,
340 uint16_t *size, uint8_t *frev, uint8_t *crev);
341
342/**
343 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
344 * @cgs_device: opaque device handle
345 * @table: data table index
346 * @frev: table format revision (output, may be NULL)
347 * @crev: table content revision (output, may be NULL)
348 *
349 * Return: 0 on success, -errno otherwise
350 */
351typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table,
352 uint8_t *frev, uint8_t *crev);
353
354/**
355 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
356 * @cgs_device: opaque device handle
357 * @table: command table index
358 * @args: arguments
359 *
360 * Return: 0 on success, -errno otherwise
361 */
362typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device,
363 unsigned table, void *args);
364
365/**
366 * cgs_get_firmware_info - Get the firmware information from core driver
367 * @cgs_device: opaque device handle
368 * @type: the firmware type
369 * @info: returend firmware information
370 *
371 * Return: 0 on success, -errno otherwise
372 */
373typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
374 enum cgs_ucode_id type,
375 struct cgs_firmware_info *info);
376
377typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device,
378 enum cgs_ucode_id type);
379
380typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
381 enum amd_ip_block_type block_type,
382 enum amd_powergating_state state);
383
384typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device,
385 enum amd_ip_block_type block_type,
386 enum amd_clockgating_state state);
387
388typedef int(*cgs_get_active_displays_info)(
389 struct cgs_device *cgs_device,
390 struct cgs_display_info *info);
391
392typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
393
394typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device,
395 uint32_t acpi_method,
396 uint32_t acpi_function,
397 void *pinput, void *poutput,
398 uint32_t output_count,
399 uint32_t input_size,
400 uint32_t output_size);
401
402typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device,
403 struct cgs_system_info *sys_info);
404
405typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device);
406
407typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en);
408
409struct cgs_ops {
410 /* memory management calls (similar to KFD interface) */
411 cgs_alloc_gpu_mem_t alloc_gpu_mem;
412 cgs_free_gpu_mem_t free_gpu_mem;
413 cgs_gmap_gpu_mem_t gmap_gpu_mem;
414 cgs_gunmap_gpu_mem_t gunmap_gpu_mem;
415 cgs_kmap_gpu_mem_t kmap_gpu_mem;
416 cgs_kunmap_gpu_mem_t kunmap_gpu_mem;
417 /* MMIO access */
418 cgs_read_register_t read_register;
419 cgs_write_register_t write_register;
420 cgs_read_ind_register_t read_ind_register;
421 cgs_write_ind_register_t write_ind_register;
422 /* PCI resources */
423 cgs_get_pci_resource_t get_pci_resource;
424 /* ATOM BIOS */
425 cgs_atom_get_data_table_t atom_get_data_table;
426 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
427 cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
428 /* Firmware Info */
429 cgs_get_firmware_info get_firmware_info;
430 cgs_rel_firmware rel_firmware;
431 /* cg pg interface*/
432 cgs_set_powergating_state set_powergating_state;
433 cgs_set_clockgating_state set_clockgating_state;
434 /* display manager */
435 cgs_get_active_displays_info get_active_displays_info;
436 /* notify dpm enabled */
437 cgs_notify_dpm_enabled notify_dpm_enabled;
438 /* ACPI */
439 cgs_call_acpi_method call_acpi_method;
440 /* get system info */
441 cgs_query_system_info query_system_info;
442 cgs_is_virtualization_enabled_t is_virtualization_enabled;
443 cgs_enter_safe_mode enter_safe_mode;
444};
445
446struct cgs_os_ops; /* To be define in OS-specific CGS header */
447
448struct cgs_device
449{
450 const struct cgs_ops *ops;
451 const struct cgs_os_ops *os_ops;
452 /* to be embedded at the start of driver private structure */
453};
454
455/* Convenience macros that make CGS indirect function calls look like
456 * normal function calls */
457#define CGS_CALL(func,dev,...) \
458 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
459#define CGS_OS_CALL(func,dev,...) \
460 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
461
462#define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \
463 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
464#define cgs_free_gpu_mem(dev,handle) \
465 CGS_CALL(free_gpu_mem,dev,handle)
466#define cgs_gmap_gpu_mem(dev,handle,mcaddr) \
467 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr)
468#define cgs_gunmap_gpu_mem(dev,handle) \
469 CGS_CALL(gunmap_gpu_mem,dev,handle)
470#define cgs_kmap_gpu_mem(dev,handle,map) \
471 CGS_CALL(kmap_gpu_mem,dev,handle,map)
472#define cgs_kunmap_gpu_mem(dev,handle) \
473 CGS_CALL(kunmap_gpu_mem,dev,handle)
474
475#define cgs_read_register(dev,offset) \
476 CGS_CALL(read_register,dev,offset)
477#define cgs_write_register(dev,offset,value) \
478 CGS_CALL(write_register,dev,offset,value)
479#define cgs_read_ind_register(dev,space,index) \
480 CGS_CALL(read_ind_register,dev,space,index)
481#define cgs_write_ind_register(dev,space,index,value) \
482 CGS_CALL(write_ind_register,dev,space,index,value)
483
484#define cgs_atom_get_data_table(dev,table,size,frev,crev) \
485 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
486#define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \
487 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
488#define cgs_atom_exec_cmd_table(dev,table,args) \
489 CGS_CALL(atom_exec_cmd_table,dev,table,args)
490
491#define cgs_get_firmware_info(dev, type, info) \
492 CGS_CALL(get_firmware_info, dev, type, info)
493#define cgs_rel_firmware(dev, type) \
494 CGS_CALL(rel_firmware, dev, type)
495#define cgs_set_powergating_state(dev, block_type, state) \
496 CGS_CALL(set_powergating_state, dev, block_type, state)
497#define cgs_set_clockgating_state(dev, block_type, state) \
498 CGS_CALL(set_clockgating_state, dev, block_type, state)
499#define cgs_notify_dpm_enabled(dev, enabled) \
500 CGS_CALL(notify_dpm_enabled, dev, enabled)
501
502#define cgs_get_active_displays_info(dev, info) \
503 CGS_CALL(get_active_displays_info, dev, info)
504
505#define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \
506 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
507#define cgs_query_system_info(dev, sys_info) \
508 CGS_CALL(query_system_info, dev, sys_info)
509#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
510 resource_base) \
511 CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
512 resource_base)
513
514#define cgs_is_virtualization_enabled(cgs_device) \
515 CGS_CALL(is_virtualization_enabled, cgs_device)
516
517#define cgs_enter_safe_mode(cgs_device, en) \
518 CGS_CALL(enter_safe_mode, cgs_device, en)
519
520#endif /* _CGS_COMMON_H */