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1Binding for IDT VersaClock5 programmable i2c clock generator.
2
3The IDT VersaClock5 are programmable i2c clock generators providing
4from 3 to 12 output clocks.
5
6==I2C device node==
7
8Required properties:
9- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933" ,
10 "idt,5p49v5935".
11- reg: i2c device address, shall be 0x68 or 0x6a.
12- #clock-cells: from common clock binding; shall be set to 1.
13- clocks: from common clock binding; list of parent clock handles,
14 - 5p49v5923: (required) either or both of XTAL or CLKIN
15 reference clock.
16 - 5p49v5933 and
17 - 5p49v5935: (optional) property not present (internal
18 Xtal used) or CLKIN reference
19 clock.
20- clock-names: from common clock binding; clock input names, can be
21 - 5p49v5923: (required) either or both of "xin", "clkin".
22 - 5p49v5933 and
23 - 5p49v5935: (optional) property not present or "clkin".
24
25==Mapping between clock specifier and physical pins==
26
27When referencing the provided clock in the DT using phandle and
28clock specifier, the following mapping applies:
29
305P49V5923:
31 0 -- OUT0_SEL_I2CB
32 1 -- OUT1
33 2 -- OUT2
34
355P49V5933:
36 0 -- OUT0_SEL_I2CB
37 1 -- OUT1
38 2 -- OUT4
39
405P49V5935:
41 0 -- OUT0_SEL_I2CB
42 1 -- OUT1
43 2 -- OUT2
44 3 -- OUT3
45 4 -- OUT4
46
47==Example==
48
49/* 25MHz reference crystal */
50ref25: ref25m {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <25000000>;
54};
55
56i2c-master-node {
57
58 /* IDT 5P49V5923 i2c clock generator */
59 vc5: clock-generator@6a {
60 compatible = "idt,5p49v5923";
61 reg = <0x6a>;
62 #clock-cells = <1>;
63
64 /* Connect XIN input to 25MHz reference */
65 clocks = <&ref25m>;
66 clock-names = "xin";
67 };
68};
69
70/* Consumer referencing the 5P49V5923 pin OUT1 */
71consumer {
72 ...
73 clocks = <&vc5 1>;
74 ...
75}