tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31*/
32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
69enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72};
73
74enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
86 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
87 MLX5_CMD_OP_CREATE_MKEY = 0x200,
88 MLX5_CMD_OP_QUERY_MKEY = 0x201,
89 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
90 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
91 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
92 MLX5_CMD_OP_CREATE_EQ = 0x301,
93 MLX5_CMD_OP_DESTROY_EQ = 0x302,
94 MLX5_CMD_OP_QUERY_EQ = 0x303,
95 MLX5_CMD_OP_GEN_EQE = 0x304,
96 MLX5_CMD_OP_CREATE_CQ = 0x400,
97 MLX5_CMD_OP_DESTROY_CQ = 0x401,
98 MLX5_CMD_OP_QUERY_CQ = 0x402,
99 MLX5_CMD_OP_MODIFY_CQ = 0x403,
100 MLX5_CMD_OP_CREATE_QP = 0x500,
101 MLX5_CMD_OP_DESTROY_QP = 0x501,
102 MLX5_CMD_OP_RST2INIT_QP = 0x502,
103 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
104 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
105 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
106 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
107 MLX5_CMD_OP_2ERR_QP = 0x507,
108 MLX5_CMD_OP_2RST_QP = 0x50a,
109 MLX5_CMD_OP_QUERY_QP = 0x50b,
110 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
111 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
112 MLX5_CMD_OP_CREATE_PSV = 0x600,
113 MLX5_CMD_OP_DESTROY_PSV = 0x601,
114 MLX5_CMD_OP_CREATE_SRQ = 0x700,
115 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
116 MLX5_CMD_OP_QUERY_SRQ = 0x702,
117 MLX5_CMD_OP_ARM_RQ = 0x703,
118 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
119 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
120 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
121 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
122 MLX5_CMD_OP_CREATE_DCT = 0x710,
123 MLX5_CMD_OP_DESTROY_DCT = 0x711,
124 MLX5_CMD_OP_DRAIN_DCT = 0x712,
125 MLX5_CMD_OP_QUERY_DCT = 0x713,
126 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
127 MLX5_CMD_OP_CREATE_XRQ = 0x717,
128 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
129 MLX5_CMD_OP_QUERY_XRQ = 0x719,
130 MLX5_CMD_OP_ARM_XRQ = 0x71a,
131 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
132 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
133 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
134 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
135 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
136 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
137 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
138 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
139 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
140 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
143 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
144 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
145 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
146 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
147 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
148 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
149 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
150 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
151 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
152 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
153 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
154 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
155 MLX5_CMD_OP_ALLOC_PD = 0x800,
156 MLX5_CMD_OP_DEALLOC_PD = 0x801,
157 MLX5_CMD_OP_ALLOC_UAR = 0x802,
158 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
159 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
160 MLX5_CMD_OP_ACCESS_REG = 0x805,
161 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
162 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
163 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
164 MLX5_CMD_OP_MAD_IFC = 0x50d,
165 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
166 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
167 MLX5_CMD_OP_NOP = 0x80d,
168 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
169 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
170 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
171 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
172 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
173 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
174 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
175 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
176 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
177 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
178 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
179 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
180 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
181 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
182 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
183 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
184 MLX5_CMD_OP_CREATE_LAG = 0x840,
185 MLX5_CMD_OP_MODIFY_LAG = 0x841,
186 MLX5_CMD_OP_QUERY_LAG = 0x842,
187 MLX5_CMD_OP_DESTROY_LAG = 0x843,
188 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
189 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
190 MLX5_CMD_OP_CREATE_TIR = 0x900,
191 MLX5_CMD_OP_MODIFY_TIR = 0x901,
192 MLX5_CMD_OP_DESTROY_TIR = 0x902,
193 MLX5_CMD_OP_QUERY_TIR = 0x903,
194 MLX5_CMD_OP_CREATE_SQ = 0x904,
195 MLX5_CMD_OP_MODIFY_SQ = 0x905,
196 MLX5_CMD_OP_DESTROY_SQ = 0x906,
197 MLX5_CMD_OP_QUERY_SQ = 0x907,
198 MLX5_CMD_OP_CREATE_RQ = 0x908,
199 MLX5_CMD_OP_MODIFY_RQ = 0x909,
200 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
201 MLX5_CMD_OP_QUERY_RQ = 0x90b,
202 MLX5_CMD_OP_CREATE_RMP = 0x90c,
203 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
204 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
205 MLX5_CMD_OP_QUERY_RMP = 0x90f,
206 MLX5_CMD_OP_CREATE_TIS = 0x912,
207 MLX5_CMD_OP_MODIFY_TIS = 0x913,
208 MLX5_CMD_OP_DESTROY_TIS = 0x914,
209 MLX5_CMD_OP_QUERY_TIS = 0x915,
210 MLX5_CMD_OP_CREATE_RQT = 0x916,
211 MLX5_CMD_OP_MODIFY_RQT = 0x917,
212 MLX5_CMD_OP_DESTROY_RQT = 0x918,
213 MLX5_CMD_OP_QUERY_RQT = 0x919,
214 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
215 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
216 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
217 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
218 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
219 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
220 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
221 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
222 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
223 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
224 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
225 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
226 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
227 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
228 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
229 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
230 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
231 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
232 MLX5_CMD_OP_MAX
233};
234
235struct mlx5_ifc_flow_table_fields_supported_bits {
236 u8 outer_dmac[0x1];
237 u8 outer_smac[0x1];
238 u8 outer_ether_type[0x1];
239 u8 outer_ip_version[0x1];
240 u8 outer_first_prio[0x1];
241 u8 outer_first_cfi[0x1];
242 u8 outer_first_vid[0x1];
243 u8 reserved_at_7[0x1];
244 u8 outer_second_prio[0x1];
245 u8 outer_second_cfi[0x1];
246 u8 outer_second_vid[0x1];
247 u8 reserved_at_b[0x1];
248 u8 outer_sip[0x1];
249 u8 outer_dip[0x1];
250 u8 outer_frag[0x1];
251 u8 outer_ip_protocol[0x1];
252 u8 outer_ip_ecn[0x1];
253 u8 outer_ip_dscp[0x1];
254 u8 outer_udp_sport[0x1];
255 u8 outer_udp_dport[0x1];
256 u8 outer_tcp_sport[0x1];
257 u8 outer_tcp_dport[0x1];
258 u8 outer_tcp_flags[0x1];
259 u8 outer_gre_protocol[0x1];
260 u8 outer_gre_key[0x1];
261 u8 outer_vxlan_vni[0x1];
262 u8 reserved_at_1a[0x5];
263 u8 source_eswitch_port[0x1];
264
265 u8 inner_dmac[0x1];
266 u8 inner_smac[0x1];
267 u8 inner_ether_type[0x1];
268 u8 inner_ip_version[0x1];
269 u8 inner_first_prio[0x1];
270 u8 inner_first_cfi[0x1];
271 u8 inner_first_vid[0x1];
272 u8 reserved_at_27[0x1];
273 u8 inner_second_prio[0x1];
274 u8 inner_second_cfi[0x1];
275 u8 inner_second_vid[0x1];
276 u8 reserved_at_2b[0x1];
277 u8 inner_sip[0x1];
278 u8 inner_dip[0x1];
279 u8 inner_frag[0x1];
280 u8 inner_ip_protocol[0x1];
281 u8 inner_ip_ecn[0x1];
282 u8 inner_ip_dscp[0x1];
283 u8 inner_udp_sport[0x1];
284 u8 inner_udp_dport[0x1];
285 u8 inner_tcp_sport[0x1];
286 u8 inner_tcp_dport[0x1];
287 u8 inner_tcp_flags[0x1];
288 u8 reserved_at_37[0x9];
289
290 u8 reserved_at_40[0x40];
291};
292
293struct mlx5_ifc_flow_table_prop_layout_bits {
294 u8 ft_support[0x1];
295 u8 reserved_at_1[0x1];
296 u8 flow_counter[0x1];
297 u8 flow_modify_en[0x1];
298 u8 modify_root[0x1];
299 u8 identified_miss_table_mode[0x1];
300 u8 flow_table_modify[0x1];
301 u8 encap[0x1];
302 u8 decap[0x1];
303 u8 reserved_at_9[0x17];
304
305 u8 reserved_at_20[0x2];
306 u8 log_max_ft_size[0x6];
307 u8 log_max_modify_header_context[0x8];
308 u8 max_modify_header_actions[0x8];
309 u8 max_ft_level[0x8];
310
311 u8 reserved_at_40[0x20];
312
313 u8 reserved_at_60[0x18];
314 u8 log_max_ft_num[0x8];
315
316 u8 reserved_at_80[0x18];
317 u8 log_max_destination[0x8];
318
319 u8 reserved_at_a0[0x18];
320 u8 log_max_flow[0x8];
321
322 u8 reserved_at_c0[0x40];
323
324 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
325
326 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
327};
328
329struct mlx5_ifc_odp_per_transport_service_cap_bits {
330 u8 send[0x1];
331 u8 receive[0x1];
332 u8 write[0x1];
333 u8 read[0x1];
334 u8 atomic[0x1];
335 u8 srq_receive[0x1];
336 u8 reserved_at_6[0x1a];
337};
338
339struct mlx5_ifc_ipv4_layout_bits {
340 u8 reserved_at_0[0x60];
341
342 u8 ipv4[0x20];
343};
344
345struct mlx5_ifc_ipv6_layout_bits {
346 u8 ipv6[16][0x8];
347};
348
349union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
350 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
351 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
352 u8 reserved_at_0[0x80];
353};
354
355struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
356 u8 smac_47_16[0x20];
357
358 u8 smac_15_0[0x10];
359 u8 ethertype[0x10];
360
361 u8 dmac_47_16[0x20];
362
363 u8 dmac_15_0[0x10];
364 u8 first_prio[0x3];
365 u8 first_cfi[0x1];
366 u8 first_vid[0xc];
367
368 u8 ip_protocol[0x8];
369 u8 ip_dscp[0x6];
370 u8 ip_ecn[0x2];
371 u8 cvlan_tag[0x1];
372 u8 svlan_tag[0x1];
373 u8 frag[0x1];
374 u8 ip_version[0x4];
375 u8 tcp_flags[0x9];
376
377 u8 tcp_sport[0x10];
378 u8 tcp_dport[0x10];
379
380 u8 reserved_at_c0[0x20];
381
382 u8 udp_sport[0x10];
383 u8 udp_dport[0x10];
384
385 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
386
387 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
388};
389
390struct mlx5_ifc_fte_match_set_misc_bits {
391 u8 reserved_at_0[0x8];
392 u8 source_sqn[0x18];
393
394 u8 reserved_at_20[0x10];
395 u8 source_port[0x10];
396
397 u8 outer_second_prio[0x3];
398 u8 outer_second_cfi[0x1];
399 u8 outer_second_vid[0xc];
400 u8 inner_second_prio[0x3];
401 u8 inner_second_cfi[0x1];
402 u8 inner_second_vid[0xc];
403
404 u8 outer_second_cvlan_tag[0x1];
405 u8 inner_second_cvlan_tag[0x1];
406 u8 outer_second_svlan_tag[0x1];
407 u8 inner_second_svlan_tag[0x1];
408 u8 reserved_at_64[0xc];
409 u8 gre_protocol[0x10];
410
411 u8 gre_key_h[0x18];
412 u8 gre_key_l[0x8];
413
414 u8 vxlan_vni[0x18];
415 u8 reserved_at_b8[0x8];
416
417 u8 reserved_at_c0[0x20];
418
419 u8 reserved_at_e0[0xc];
420 u8 outer_ipv6_flow_label[0x14];
421
422 u8 reserved_at_100[0xc];
423 u8 inner_ipv6_flow_label[0x14];
424
425 u8 reserved_at_120[0xe0];
426};
427
428struct mlx5_ifc_cmd_pas_bits {
429 u8 pa_h[0x20];
430
431 u8 pa_l[0x14];
432 u8 reserved_at_34[0xc];
433};
434
435struct mlx5_ifc_uint64_bits {
436 u8 hi[0x20];
437
438 u8 lo[0x20];
439};
440
441enum {
442 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
443 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
444 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
445 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
446 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
447 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
448 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
449 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
450 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
451 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
452};
453
454struct mlx5_ifc_ads_bits {
455 u8 fl[0x1];
456 u8 free_ar[0x1];
457 u8 reserved_at_2[0xe];
458 u8 pkey_index[0x10];
459
460 u8 reserved_at_20[0x8];
461 u8 grh[0x1];
462 u8 mlid[0x7];
463 u8 rlid[0x10];
464
465 u8 ack_timeout[0x5];
466 u8 reserved_at_45[0x3];
467 u8 src_addr_index[0x8];
468 u8 reserved_at_50[0x4];
469 u8 stat_rate[0x4];
470 u8 hop_limit[0x8];
471
472 u8 reserved_at_60[0x4];
473 u8 tclass[0x8];
474 u8 flow_label[0x14];
475
476 u8 rgid_rip[16][0x8];
477
478 u8 reserved_at_100[0x4];
479 u8 f_dscp[0x1];
480 u8 f_ecn[0x1];
481 u8 reserved_at_106[0x1];
482 u8 f_eth_prio[0x1];
483 u8 ecn[0x2];
484 u8 dscp[0x6];
485 u8 udp_sport[0x10];
486
487 u8 dei_cfi[0x1];
488 u8 eth_prio[0x3];
489 u8 sl[0x4];
490 u8 port[0x8];
491 u8 rmac_47_32[0x10];
492
493 u8 rmac_31_0[0x20];
494};
495
496struct mlx5_ifc_flow_table_nic_cap_bits {
497 u8 nic_rx_multi_path_tirs[0x1];
498 u8 nic_rx_multi_path_tirs_fts[0x1];
499 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
500 u8 reserved_at_3[0x1fd];
501
502 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
503
504 u8 reserved_at_400[0x200];
505
506 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
507
508 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
509
510 u8 reserved_at_a00[0x200];
511
512 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
513
514 u8 reserved_at_e00[0x7200];
515};
516
517struct mlx5_ifc_flow_table_eswitch_cap_bits {
518 u8 reserved_at_0[0x200];
519
520 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
521
522 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
523
524 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
525
526 u8 reserved_at_800[0x7800];
527};
528
529struct mlx5_ifc_e_switch_cap_bits {
530 u8 vport_svlan_strip[0x1];
531 u8 vport_cvlan_strip[0x1];
532 u8 vport_svlan_insert[0x1];
533 u8 vport_cvlan_insert_if_not_exist[0x1];
534 u8 vport_cvlan_insert_overwrite[0x1];
535 u8 reserved_at_5[0x19];
536 u8 nic_vport_node_guid_modify[0x1];
537 u8 nic_vport_port_guid_modify[0x1];
538
539 u8 vxlan_encap_decap[0x1];
540 u8 nvgre_encap_decap[0x1];
541 u8 reserved_at_22[0x9];
542 u8 log_max_encap_headers[0x5];
543 u8 reserved_2b[0x6];
544 u8 max_encap_header_size[0xa];
545
546 u8 reserved_40[0x7c0];
547
548};
549
550struct mlx5_ifc_qos_cap_bits {
551 u8 packet_pacing[0x1];
552 u8 esw_scheduling[0x1];
553 u8 esw_bw_share[0x1];
554 u8 esw_rate_limit[0x1];
555 u8 reserved_at_4[0x1c];
556
557 u8 reserved_at_20[0x20];
558
559 u8 packet_pacing_max_rate[0x20];
560
561 u8 packet_pacing_min_rate[0x20];
562
563 u8 reserved_at_80[0x10];
564 u8 packet_pacing_rate_table_size[0x10];
565
566 u8 esw_element_type[0x10];
567 u8 esw_tsar_type[0x10];
568
569 u8 reserved_at_c0[0x10];
570 u8 max_qos_para_vport[0x10];
571
572 u8 max_tsar_bw_share[0x20];
573
574 u8 reserved_at_100[0x700];
575};
576
577struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
578 u8 csum_cap[0x1];
579 u8 vlan_cap[0x1];
580 u8 lro_cap[0x1];
581 u8 lro_psh_flag[0x1];
582 u8 lro_time_stamp[0x1];
583 u8 reserved_at_5[0x2];
584 u8 wqe_vlan_insert[0x1];
585 u8 self_lb_en_modifiable[0x1];
586 u8 reserved_at_9[0x2];
587 u8 max_lso_cap[0x5];
588 u8 multi_pkt_send_wqe[0x2];
589 u8 wqe_inline_mode[0x2];
590 u8 rss_ind_tbl_cap[0x4];
591 u8 reg_umr_sq[0x1];
592 u8 scatter_fcs[0x1];
593 u8 reserved_at_1a[0x1];
594 u8 tunnel_lso_const_out_ip_id[0x1];
595 u8 reserved_at_1c[0x2];
596 u8 tunnel_statless_gre[0x1];
597 u8 tunnel_stateless_vxlan[0x1];
598
599 u8 reserved_at_20[0x20];
600
601 u8 reserved_at_40[0x10];
602 u8 lro_min_mss_size[0x10];
603
604 u8 reserved_at_60[0x120];
605
606 u8 lro_timer_supported_periods[4][0x20];
607
608 u8 reserved_at_200[0x600];
609};
610
611struct mlx5_ifc_roce_cap_bits {
612 u8 roce_apm[0x1];
613 u8 reserved_at_1[0x1f];
614
615 u8 reserved_at_20[0x60];
616
617 u8 reserved_at_80[0xc];
618 u8 l3_type[0x4];
619 u8 reserved_at_90[0x8];
620 u8 roce_version[0x8];
621
622 u8 reserved_at_a0[0x10];
623 u8 r_roce_dest_udp_port[0x10];
624
625 u8 r_roce_max_src_udp_port[0x10];
626 u8 r_roce_min_src_udp_port[0x10];
627
628 u8 reserved_at_e0[0x10];
629 u8 roce_address_table_size[0x10];
630
631 u8 reserved_at_100[0x700];
632};
633
634enum {
635 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
636 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
637 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
638 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
640 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
644};
645
646enum {
647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
648 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
649 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
650 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
651 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
652 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
653 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
654 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
656};
657
658struct mlx5_ifc_atomic_caps_bits {
659 u8 reserved_at_0[0x40];
660
661 u8 atomic_req_8B_endianess_mode[0x2];
662 u8 reserved_at_42[0x4];
663 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
664
665 u8 reserved_at_47[0x19];
666
667 u8 reserved_at_60[0x20];
668
669 u8 reserved_at_80[0x10];
670 u8 atomic_operations[0x10];
671
672 u8 reserved_at_a0[0x10];
673 u8 atomic_size_qp[0x10];
674
675 u8 reserved_at_c0[0x10];
676 u8 atomic_size_dc[0x10];
677
678 u8 reserved_at_e0[0x720];
679};
680
681struct mlx5_ifc_odp_cap_bits {
682 u8 reserved_at_0[0x40];
683
684 u8 sig[0x1];
685 u8 reserved_at_41[0x1f];
686
687 u8 reserved_at_60[0x20];
688
689 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
690
691 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
692
693 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
694
695 u8 reserved_at_e0[0x720];
696};
697
698struct mlx5_ifc_calc_op {
699 u8 reserved_at_0[0x10];
700 u8 reserved_at_10[0x9];
701 u8 op_swap_endianness[0x1];
702 u8 op_min[0x1];
703 u8 op_xor[0x1];
704 u8 op_or[0x1];
705 u8 op_and[0x1];
706 u8 op_max[0x1];
707 u8 op_add[0x1];
708};
709
710struct mlx5_ifc_vector_calc_cap_bits {
711 u8 calc_matrix[0x1];
712 u8 reserved_at_1[0x1f];
713 u8 reserved_at_20[0x8];
714 u8 max_vec_count[0x8];
715 u8 reserved_at_30[0xd];
716 u8 max_chunk_size[0x3];
717 struct mlx5_ifc_calc_op calc0;
718 struct mlx5_ifc_calc_op calc1;
719 struct mlx5_ifc_calc_op calc2;
720 struct mlx5_ifc_calc_op calc3;
721
722 u8 reserved_at_e0[0x720];
723};
724
725enum {
726 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
727 MLX5_WQ_TYPE_CYCLIC = 0x1,
728 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
729};
730
731enum {
732 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
733 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
734};
735
736enum {
737 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
738 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
739 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
740 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
741 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
742};
743
744enum {
745 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
746 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
747 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
748 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
749 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
750 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
751};
752
753enum {
754 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
755 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
756};
757
758enum {
759 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
760 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
761 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
762};
763
764enum {
765 MLX5_CAP_PORT_TYPE_IB = 0x0,
766 MLX5_CAP_PORT_TYPE_ETH = 0x1,
767};
768
769struct mlx5_ifc_cmd_hca_cap_bits {
770 u8 reserved_at_0[0x80];
771
772 u8 log_max_srq_sz[0x8];
773 u8 log_max_qp_sz[0x8];
774 u8 reserved_at_90[0xb];
775 u8 log_max_qp[0x5];
776
777 u8 reserved_at_a0[0xb];
778 u8 log_max_srq[0x5];
779 u8 reserved_at_b0[0x10];
780
781 u8 reserved_at_c0[0x8];
782 u8 log_max_cq_sz[0x8];
783 u8 reserved_at_d0[0xb];
784 u8 log_max_cq[0x5];
785
786 u8 log_max_eq_sz[0x8];
787 u8 reserved_at_e8[0x2];
788 u8 log_max_mkey[0x6];
789 u8 reserved_at_f0[0xc];
790 u8 log_max_eq[0x4];
791
792 u8 max_indirection[0x8];
793 u8 fixed_buffer_size[0x1];
794 u8 log_max_mrw_sz[0x7];
795 u8 reserved_at_110[0x2];
796 u8 log_max_bsf_list_size[0x6];
797 u8 umr_extended_translation_offset[0x1];
798 u8 null_mkey[0x1];
799 u8 log_max_klm_list_size[0x6];
800
801 u8 reserved_at_120[0xa];
802 u8 log_max_ra_req_dc[0x6];
803 u8 reserved_at_130[0xa];
804 u8 log_max_ra_res_dc[0x6];
805
806 u8 reserved_at_140[0xa];
807 u8 log_max_ra_req_qp[0x6];
808 u8 reserved_at_150[0xa];
809 u8 log_max_ra_res_qp[0x6];
810
811 u8 end_pad[0x1];
812 u8 cc_query_allowed[0x1];
813 u8 cc_modify_allowed[0x1];
814 u8 start_pad[0x1];
815 u8 cache_line_128byte[0x1];
816 u8 reserved_at_163[0xb];
817 u8 gid_table_size[0x10];
818
819 u8 out_of_seq_cnt[0x1];
820 u8 vport_counters[0x1];
821 u8 retransmission_q_counters[0x1];
822 u8 reserved_at_183[0x1];
823 u8 modify_rq_counter_set_id[0x1];
824 u8 reserved_at_185[0x1];
825 u8 max_qp_cnt[0xa];
826 u8 pkey_table_size[0x10];
827
828 u8 vport_group_manager[0x1];
829 u8 vhca_group_manager[0x1];
830 u8 ib_virt[0x1];
831 u8 eth_virt[0x1];
832 u8 reserved_at_1a4[0x1];
833 u8 ets[0x1];
834 u8 nic_flow_table[0x1];
835 u8 eswitch_flow_table[0x1];
836 u8 early_vf_enable[0x1];
837 u8 mcam_reg[0x1];
838 u8 pcam_reg[0x1];
839 u8 local_ca_ack_delay[0x5];
840 u8 port_module_event[0x1];
841 u8 reserved_at_1b1[0x1];
842 u8 ports_check[0x1];
843 u8 reserved_at_1b3[0x1];
844 u8 disable_link_up[0x1];
845 u8 beacon_led[0x1];
846 u8 port_type[0x2];
847 u8 num_ports[0x8];
848
849 u8 reserved_at_1c0[0x1];
850 u8 pps[0x1];
851 u8 pps_modify[0x1];
852 u8 log_max_msg[0x5];
853 u8 reserved_at_1c8[0x4];
854 u8 max_tc[0x4];
855 u8 reserved_at_1d0[0x1];
856 u8 dcbx[0x1];
857 u8 reserved_at_1d2[0x4];
858 u8 rol_s[0x1];
859 u8 rol_g[0x1];
860 u8 reserved_at_1d8[0x1];
861 u8 wol_s[0x1];
862 u8 wol_g[0x1];
863 u8 wol_a[0x1];
864 u8 wol_b[0x1];
865 u8 wol_m[0x1];
866 u8 wol_u[0x1];
867 u8 wol_p[0x1];
868
869 u8 stat_rate_support[0x10];
870 u8 reserved_at_1f0[0xc];
871 u8 cqe_version[0x4];
872
873 u8 compact_address_vector[0x1];
874 u8 striding_rq[0x1];
875 u8 reserved_at_202[0x1];
876 u8 ipoib_enhanced_offloads[0x1];
877 u8 ipoib_basic_offloads[0x1];
878 u8 reserved_at_205[0xa];
879 u8 drain_sigerr[0x1];
880 u8 cmdif_checksum[0x2];
881 u8 sigerr_cqe[0x1];
882 u8 reserved_at_213[0x1];
883 u8 wq_signature[0x1];
884 u8 sctr_data_cqe[0x1];
885 u8 reserved_at_216[0x1];
886 u8 sho[0x1];
887 u8 tph[0x1];
888 u8 rf[0x1];
889 u8 dct[0x1];
890 u8 qos[0x1];
891 u8 eth_net_offloads[0x1];
892 u8 roce[0x1];
893 u8 atomic[0x1];
894 u8 reserved_at_21f[0x1];
895
896 u8 cq_oi[0x1];
897 u8 cq_resize[0x1];
898 u8 cq_moderation[0x1];
899 u8 reserved_at_223[0x3];
900 u8 cq_eq_remap[0x1];
901 u8 pg[0x1];
902 u8 block_lb_mc[0x1];
903 u8 reserved_at_229[0x1];
904 u8 scqe_break_moderation[0x1];
905 u8 cq_period_start_from_cqe[0x1];
906 u8 cd[0x1];
907 u8 reserved_at_22d[0x1];
908 u8 apm[0x1];
909 u8 vector_calc[0x1];
910 u8 umr_ptr_rlky[0x1];
911 u8 imaicl[0x1];
912 u8 reserved_at_232[0x4];
913 u8 qkv[0x1];
914 u8 pkv[0x1];
915 u8 set_deth_sqpn[0x1];
916 u8 reserved_at_239[0x3];
917 u8 xrc[0x1];
918 u8 ud[0x1];
919 u8 uc[0x1];
920 u8 rc[0x1];
921
922 u8 uar_4k[0x1];
923 u8 reserved_at_241[0x9];
924 u8 uar_sz[0x6];
925 u8 reserved_at_250[0x8];
926 u8 log_pg_sz[0x8];
927
928 u8 bf[0x1];
929 u8 driver_version[0x1];
930 u8 pad_tx_eth_packet[0x1];
931 u8 reserved_at_263[0x8];
932 u8 log_bf_reg_size[0x5];
933
934 u8 reserved_at_270[0xb];
935 u8 lag_master[0x1];
936 u8 num_lag_ports[0x4];
937
938 u8 reserved_at_280[0x10];
939 u8 max_wqe_sz_sq[0x10];
940
941 u8 reserved_at_2a0[0x10];
942 u8 max_wqe_sz_rq[0x10];
943
944 u8 reserved_at_2c0[0x10];
945 u8 max_wqe_sz_sq_dc[0x10];
946
947 u8 reserved_at_2e0[0x7];
948 u8 max_qp_mcg[0x19];
949
950 u8 reserved_at_300[0x18];
951 u8 log_max_mcg[0x8];
952
953 u8 reserved_at_320[0x3];
954 u8 log_max_transport_domain[0x5];
955 u8 reserved_at_328[0x3];
956 u8 log_max_pd[0x5];
957 u8 reserved_at_330[0xb];
958 u8 log_max_xrcd[0x5];
959
960 u8 reserved_at_340[0x8];
961 u8 log_max_flow_counter_bulk[0x8];
962 u8 max_flow_counter[0x10];
963
964
965 u8 reserved_at_360[0x3];
966 u8 log_max_rq[0x5];
967 u8 reserved_at_368[0x3];
968 u8 log_max_sq[0x5];
969 u8 reserved_at_370[0x3];
970 u8 log_max_tir[0x5];
971 u8 reserved_at_378[0x3];
972 u8 log_max_tis[0x5];
973
974 u8 basic_cyclic_rcv_wqe[0x1];
975 u8 reserved_at_381[0x2];
976 u8 log_max_rmp[0x5];
977 u8 reserved_at_388[0x3];
978 u8 log_max_rqt[0x5];
979 u8 reserved_at_390[0x3];
980 u8 log_max_rqt_size[0x5];
981 u8 reserved_at_398[0x3];
982 u8 log_max_tis_per_sq[0x5];
983
984 u8 reserved_at_3a0[0x3];
985 u8 log_max_stride_sz_rq[0x5];
986 u8 reserved_at_3a8[0x3];
987 u8 log_min_stride_sz_rq[0x5];
988 u8 reserved_at_3b0[0x3];
989 u8 log_max_stride_sz_sq[0x5];
990 u8 reserved_at_3b8[0x3];
991 u8 log_min_stride_sz_sq[0x5];
992
993 u8 reserved_at_3c0[0x1b];
994 u8 log_max_wq_sz[0x5];
995
996 u8 nic_vport_change_event[0x1];
997 u8 reserved_at_3e1[0xa];
998 u8 log_max_vlan_list[0x5];
999 u8 reserved_at_3f0[0x3];
1000 u8 log_max_current_mc_list[0x5];
1001 u8 reserved_at_3f8[0x3];
1002 u8 log_max_current_uc_list[0x5];
1003
1004 u8 reserved_at_400[0x80];
1005
1006 u8 reserved_at_480[0x3];
1007 u8 log_max_l2_table[0x5];
1008 u8 reserved_at_488[0x8];
1009 u8 log_uar_page_sz[0x10];
1010
1011 u8 reserved_at_4a0[0x20];
1012 u8 device_frequency_mhz[0x20];
1013 u8 device_frequency_khz[0x20];
1014
1015 u8 reserved_at_500[0x20];
1016 u8 num_of_uars_per_page[0x20];
1017 u8 reserved_at_540[0x40];
1018
1019 u8 reserved_at_580[0x3f];
1020 u8 cqe_compression[0x1];
1021
1022 u8 cqe_compression_timeout[0x10];
1023 u8 cqe_compression_max_num[0x10];
1024
1025 u8 reserved_at_5e0[0x10];
1026 u8 tag_matching[0x1];
1027 u8 rndv_offload_rc[0x1];
1028 u8 rndv_offload_dc[0x1];
1029 u8 log_tag_matching_list_sz[0x5];
1030 u8 reserved_at_5f8[0x3];
1031 u8 log_max_xrq[0x5];
1032
1033 u8 reserved_at_600[0x200];
1034};
1035
1036enum mlx5_flow_destination_type {
1037 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1038 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1039 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1040
1041 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1042};
1043
1044struct mlx5_ifc_dest_format_struct_bits {
1045 u8 destination_type[0x8];
1046 u8 destination_id[0x18];
1047
1048 u8 reserved_at_20[0x20];
1049};
1050
1051struct mlx5_ifc_flow_counter_list_bits {
1052 u8 clear[0x1];
1053 u8 num_of_counters[0xf];
1054 u8 flow_counter_id[0x10];
1055
1056 u8 reserved_at_20[0x20];
1057};
1058
1059union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1060 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1061 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1062 u8 reserved_at_0[0x40];
1063};
1064
1065struct mlx5_ifc_fte_match_param_bits {
1066 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1067
1068 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1069
1070 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1071
1072 u8 reserved_at_600[0xa00];
1073};
1074
1075enum {
1076 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1077 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1078 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1079 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1080 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1081};
1082
1083struct mlx5_ifc_rx_hash_field_select_bits {
1084 u8 l3_prot_type[0x1];
1085 u8 l4_prot_type[0x1];
1086 u8 selected_fields[0x1e];
1087};
1088
1089enum {
1090 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1091 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1092};
1093
1094enum {
1095 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1096 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1097};
1098
1099struct mlx5_ifc_wq_bits {
1100 u8 wq_type[0x4];
1101 u8 wq_signature[0x1];
1102 u8 end_padding_mode[0x2];
1103 u8 cd_slave[0x1];
1104 u8 reserved_at_8[0x18];
1105
1106 u8 hds_skip_first_sge[0x1];
1107 u8 log2_hds_buf_size[0x3];
1108 u8 reserved_at_24[0x7];
1109 u8 page_offset[0x5];
1110 u8 lwm[0x10];
1111
1112 u8 reserved_at_40[0x8];
1113 u8 pd[0x18];
1114
1115 u8 reserved_at_60[0x8];
1116 u8 uar_page[0x18];
1117
1118 u8 dbr_addr[0x40];
1119
1120 u8 hw_counter[0x20];
1121
1122 u8 sw_counter[0x20];
1123
1124 u8 reserved_at_100[0xc];
1125 u8 log_wq_stride[0x4];
1126 u8 reserved_at_110[0x3];
1127 u8 log_wq_pg_sz[0x5];
1128 u8 reserved_at_118[0x3];
1129 u8 log_wq_sz[0x5];
1130
1131 u8 reserved_at_120[0x15];
1132 u8 log_wqe_num_of_strides[0x3];
1133 u8 two_byte_shift_en[0x1];
1134 u8 reserved_at_139[0x4];
1135 u8 log_wqe_stride_size[0x3];
1136
1137 u8 reserved_at_140[0x4c0];
1138
1139 struct mlx5_ifc_cmd_pas_bits pas[0];
1140};
1141
1142struct mlx5_ifc_rq_num_bits {
1143 u8 reserved_at_0[0x8];
1144 u8 rq_num[0x18];
1145};
1146
1147struct mlx5_ifc_mac_address_layout_bits {
1148 u8 reserved_at_0[0x10];
1149 u8 mac_addr_47_32[0x10];
1150
1151 u8 mac_addr_31_0[0x20];
1152};
1153
1154struct mlx5_ifc_vlan_layout_bits {
1155 u8 reserved_at_0[0x14];
1156 u8 vlan[0x0c];
1157
1158 u8 reserved_at_20[0x20];
1159};
1160
1161struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1162 u8 reserved_at_0[0xa0];
1163
1164 u8 min_time_between_cnps[0x20];
1165
1166 u8 reserved_at_c0[0x12];
1167 u8 cnp_dscp[0x6];
1168 u8 reserved_at_d8[0x5];
1169 u8 cnp_802p_prio[0x3];
1170
1171 u8 reserved_at_e0[0x720];
1172};
1173
1174struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1175 u8 reserved_at_0[0x60];
1176
1177 u8 reserved_at_60[0x4];
1178 u8 clamp_tgt_rate[0x1];
1179 u8 reserved_at_65[0x3];
1180 u8 clamp_tgt_rate_after_time_inc[0x1];
1181 u8 reserved_at_69[0x17];
1182
1183 u8 reserved_at_80[0x20];
1184
1185 u8 rpg_time_reset[0x20];
1186
1187 u8 rpg_byte_reset[0x20];
1188
1189 u8 rpg_threshold[0x20];
1190
1191 u8 rpg_max_rate[0x20];
1192
1193 u8 rpg_ai_rate[0x20];
1194
1195 u8 rpg_hai_rate[0x20];
1196
1197 u8 rpg_gd[0x20];
1198
1199 u8 rpg_min_dec_fac[0x20];
1200
1201 u8 rpg_min_rate[0x20];
1202
1203 u8 reserved_at_1c0[0xe0];
1204
1205 u8 rate_to_set_on_first_cnp[0x20];
1206
1207 u8 dce_tcp_g[0x20];
1208
1209 u8 dce_tcp_rtt[0x20];
1210
1211 u8 rate_reduce_monitor_period[0x20];
1212
1213 u8 reserved_at_320[0x20];
1214
1215 u8 initial_alpha_value[0x20];
1216
1217 u8 reserved_at_360[0x4a0];
1218};
1219
1220struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1221 u8 reserved_at_0[0x80];
1222
1223 u8 rppp_max_rps[0x20];
1224
1225 u8 rpg_time_reset[0x20];
1226
1227 u8 rpg_byte_reset[0x20];
1228
1229 u8 rpg_threshold[0x20];
1230
1231 u8 rpg_max_rate[0x20];
1232
1233 u8 rpg_ai_rate[0x20];
1234
1235 u8 rpg_hai_rate[0x20];
1236
1237 u8 rpg_gd[0x20];
1238
1239 u8 rpg_min_dec_fac[0x20];
1240
1241 u8 rpg_min_rate[0x20];
1242
1243 u8 reserved_at_1c0[0x640];
1244};
1245
1246enum {
1247 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1248 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1249 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1250};
1251
1252struct mlx5_ifc_resize_field_select_bits {
1253 u8 resize_field_select[0x20];
1254};
1255
1256enum {
1257 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1258 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1259 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1260 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1261};
1262
1263struct mlx5_ifc_modify_field_select_bits {
1264 u8 modify_field_select[0x20];
1265};
1266
1267struct mlx5_ifc_field_select_r_roce_np_bits {
1268 u8 field_select_r_roce_np[0x20];
1269};
1270
1271struct mlx5_ifc_field_select_r_roce_rp_bits {
1272 u8 field_select_r_roce_rp[0x20];
1273};
1274
1275enum {
1276 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1277 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1278 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1279 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1280 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1281 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1282 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1283 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1284 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1285 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1286};
1287
1288struct mlx5_ifc_field_select_802_1qau_rp_bits {
1289 u8 field_select_8021qaurp[0x20];
1290};
1291
1292struct mlx5_ifc_phys_layer_cntrs_bits {
1293 u8 time_since_last_clear_high[0x20];
1294
1295 u8 time_since_last_clear_low[0x20];
1296
1297 u8 symbol_errors_high[0x20];
1298
1299 u8 symbol_errors_low[0x20];
1300
1301 u8 sync_headers_errors_high[0x20];
1302
1303 u8 sync_headers_errors_low[0x20];
1304
1305 u8 edpl_bip_errors_lane0_high[0x20];
1306
1307 u8 edpl_bip_errors_lane0_low[0x20];
1308
1309 u8 edpl_bip_errors_lane1_high[0x20];
1310
1311 u8 edpl_bip_errors_lane1_low[0x20];
1312
1313 u8 edpl_bip_errors_lane2_high[0x20];
1314
1315 u8 edpl_bip_errors_lane2_low[0x20];
1316
1317 u8 edpl_bip_errors_lane3_high[0x20];
1318
1319 u8 edpl_bip_errors_lane3_low[0x20];
1320
1321 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1322
1323 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1324
1325 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1326
1327 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1328
1329 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1330
1331 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1332
1333 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1334
1335 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1336
1337 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1338
1339 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1340
1341 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1342
1343 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1344
1345 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1346
1347 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1348
1349 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1350
1351 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1352
1353 u8 rs_fec_corrected_blocks_high[0x20];
1354
1355 u8 rs_fec_corrected_blocks_low[0x20];
1356
1357 u8 rs_fec_uncorrectable_blocks_high[0x20];
1358
1359 u8 rs_fec_uncorrectable_blocks_low[0x20];
1360
1361 u8 rs_fec_no_errors_blocks_high[0x20];
1362
1363 u8 rs_fec_no_errors_blocks_low[0x20];
1364
1365 u8 rs_fec_single_error_blocks_high[0x20];
1366
1367 u8 rs_fec_single_error_blocks_low[0x20];
1368
1369 u8 rs_fec_corrected_symbols_total_high[0x20];
1370
1371 u8 rs_fec_corrected_symbols_total_low[0x20];
1372
1373 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1374
1375 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1376
1377 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1378
1379 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1380
1381 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1382
1383 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1384
1385 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1386
1387 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1388
1389 u8 link_down_events[0x20];
1390
1391 u8 successful_recovery_events[0x20];
1392
1393 u8 reserved_at_640[0x180];
1394};
1395
1396struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1397 u8 time_since_last_clear_high[0x20];
1398
1399 u8 time_since_last_clear_low[0x20];
1400
1401 u8 phy_received_bits_high[0x20];
1402
1403 u8 phy_received_bits_low[0x20];
1404
1405 u8 phy_symbol_errors_high[0x20];
1406
1407 u8 phy_symbol_errors_low[0x20];
1408
1409 u8 phy_corrected_bits_high[0x20];
1410
1411 u8 phy_corrected_bits_low[0x20];
1412
1413 u8 phy_corrected_bits_lane0_high[0x20];
1414
1415 u8 phy_corrected_bits_lane0_low[0x20];
1416
1417 u8 phy_corrected_bits_lane1_high[0x20];
1418
1419 u8 phy_corrected_bits_lane1_low[0x20];
1420
1421 u8 phy_corrected_bits_lane2_high[0x20];
1422
1423 u8 phy_corrected_bits_lane2_low[0x20];
1424
1425 u8 phy_corrected_bits_lane3_high[0x20];
1426
1427 u8 phy_corrected_bits_lane3_low[0x20];
1428
1429 u8 reserved_at_200[0x5c0];
1430};
1431
1432struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1433 u8 symbol_error_counter[0x10];
1434
1435 u8 link_error_recovery_counter[0x8];
1436
1437 u8 link_downed_counter[0x8];
1438
1439 u8 port_rcv_errors[0x10];
1440
1441 u8 port_rcv_remote_physical_errors[0x10];
1442
1443 u8 port_rcv_switch_relay_errors[0x10];
1444
1445 u8 port_xmit_discards[0x10];
1446
1447 u8 port_xmit_constraint_errors[0x8];
1448
1449 u8 port_rcv_constraint_errors[0x8];
1450
1451 u8 reserved_at_70[0x8];
1452
1453 u8 link_overrun_errors[0x8];
1454
1455 u8 reserved_at_80[0x10];
1456
1457 u8 vl_15_dropped[0x10];
1458
1459 u8 reserved_at_a0[0x80];
1460
1461 u8 port_xmit_wait[0x20];
1462};
1463
1464struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1465 u8 transmit_queue_high[0x20];
1466
1467 u8 transmit_queue_low[0x20];
1468
1469 u8 reserved_at_40[0x780];
1470};
1471
1472struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1473 u8 rx_octets_high[0x20];
1474
1475 u8 rx_octets_low[0x20];
1476
1477 u8 reserved_at_40[0xc0];
1478
1479 u8 rx_frames_high[0x20];
1480
1481 u8 rx_frames_low[0x20];
1482
1483 u8 tx_octets_high[0x20];
1484
1485 u8 tx_octets_low[0x20];
1486
1487 u8 reserved_at_180[0xc0];
1488
1489 u8 tx_frames_high[0x20];
1490
1491 u8 tx_frames_low[0x20];
1492
1493 u8 rx_pause_high[0x20];
1494
1495 u8 rx_pause_low[0x20];
1496
1497 u8 rx_pause_duration_high[0x20];
1498
1499 u8 rx_pause_duration_low[0x20];
1500
1501 u8 tx_pause_high[0x20];
1502
1503 u8 tx_pause_low[0x20];
1504
1505 u8 tx_pause_duration_high[0x20];
1506
1507 u8 tx_pause_duration_low[0x20];
1508
1509 u8 rx_pause_transition_high[0x20];
1510
1511 u8 rx_pause_transition_low[0x20];
1512
1513 u8 reserved_at_3c0[0x400];
1514};
1515
1516struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1517 u8 port_transmit_wait_high[0x20];
1518
1519 u8 port_transmit_wait_low[0x20];
1520
1521 u8 reserved_at_40[0x780];
1522};
1523
1524struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1525 u8 dot3stats_alignment_errors_high[0x20];
1526
1527 u8 dot3stats_alignment_errors_low[0x20];
1528
1529 u8 dot3stats_fcs_errors_high[0x20];
1530
1531 u8 dot3stats_fcs_errors_low[0x20];
1532
1533 u8 dot3stats_single_collision_frames_high[0x20];
1534
1535 u8 dot3stats_single_collision_frames_low[0x20];
1536
1537 u8 dot3stats_multiple_collision_frames_high[0x20];
1538
1539 u8 dot3stats_multiple_collision_frames_low[0x20];
1540
1541 u8 dot3stats_sqe_test_errors_high[0x20];
1542
1543 u8 dot3stats_sqe_test_errors_low[0x20];
1544
1545 u8 dot3stats_deferred_transmissions_high[0x20];
1546
1547 u8 dot3stats_deferred_transmissions_low[0x20];
1548
1549 u8 dot3stats_late_collisions_high[0x20];
1550
1551 u8 dot3stats_late_collisions_low[0x20];
1552
1553 u8 dot3stats_excessive_collisions_high[0x20];
1554
1555 u8 dot3stats_excessive_collisions_low[0x20];
1556
1557 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1558
1559 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1560
1561 u8 dot3stats_carrier_sense_errors_high[0x20];
1562
1563 u8 dot3stats_carrier_sense_errors_low[0x20];
1564
1565 u8 dot3stats_frame_too_longs_high[0x20];
1566
1567 u8 dot3stats_frame_too_longs_low[0x20];
1568
1569 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1570
1571 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1572
1573 u8 dot3stats_symbol_errors_high[0x20];
1574
1575 u8 dot3stats_symbol_errors_low[0x20];
1576
1577 u8 dot3control_in_unknown_opcodes_high[0x20];
1578
1579 u8 dot3control_in_unknown_opcodes_low[0x20];
1580
1581 u8 dot3in_pause_frames_high[0x20];
1582
1583 u8 dot3in_pause_frames_low[0x20];
1584
1585 u8 dot3out_pause_frames_high[0x20];
1586
1587 u8 dot3out_pause_frames_low[0x20];
1588
1589 u8 reserved_at_400[0x3c0];
1590};
1591
1592struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1593 u8 ether_stats_drop_events_high[0x20];
1594
1595 u8 ether_stats_drop_events_low[0x20];
1596
1597 u8 ether_stats_octets_high[0x20];
1598
1599 u8 ether_stats_octets_low[0x20];
1600
1601 u8 ether_stats_pkts_high[0x20];
1602
1603 u8 ether_stats_pkts_low[0x20];
1604
1605 u8 ether_stats_broadcast_pkts_high[0x20];
1606
1607 u8 ether_stats_broadcast_pkts_low[0x20];
1608
1609 u8 ether_stats_multicast_pkts_high[0x20];
1610
1611 u8 ether_stats_multicast_pkts_low[0x20];
1612
1613 u8 ether_stats_crc_align_errors_high[0x20];
1614
1615 u8 ether_stats_crc_align_errors_low[0x20];
1616
1617 u8 ether_stats_undersize_pkts_high[0x20];
1618
1619 u8 ether_stats_undersize_pkts_low[0x20];
1620
1621 u8 ether_stats_oversize_pkts_high[0x20];
1622
1623 u8 ether_stats_oversize_pkts_low[0x20];
1624
1625 u8 ether_stats_fragments_high[0x20];
1626
1627 u8 ether_stats_fragments_low[0x20];
1628
1629 u8 ether_stats_jabbers_high[0x20];
1630
1631 u8 ether_stats_jabbers_low[0x20];
1632
1633 u8 ether_stats_collisions_high[0x20];
1634
1635 u8 ether_stats_collisions_low[0x20];
1636
1637 u8 ether_stats_pkts64octets_high[0x20];
1638
1639 u8 ether_stats_pkts64octets_low[0x20];
1640
1641 u8 ether_stats_pkts65to127octets_high[0x20];
1642
1643 u8 ether_stats_pkts65to127octets_low[0x20];
1644
1645 u8 ether_stats_pkts128to255octets_high[0x20];
1646
1647 u8 ether_stats_pkts128to255octets_low[0x20];
1648
1649 u8 ether_stats_pkts256to511octets_high[0x20];
1650
1651 u8 ether_stats_pkts256to511octets_low[0x20];
1652
1653 u8 ether_stats_pkts512to1023octets_high[0x20];
1654
1655 u8 ether_stats_pkts512to1023octets_low[0x20];
1656
1657 u8 ether_stats_pkts1024to1518octets_high[0x20];
1658
1659 u8 ether_stats_pkts1024to1518octets_low[0x20];
1660
1661 u8 ether_stats_pkts1519to2047octets_high[0x20];
1662
1663 u8 ether_stats_pkts1519to2047octets_low[0x20];
1664
1665 u8 ether_stats_pkts2048to4095octets_high[0x20];
1666
1667 u8 ether_stats_pkts2048to4095octets_low[0x20];
1668
1669 u8 ether_stats_pkts4096to8191octets_high[0x20];
1670
1671 u8 ether_stats_pkts4096to8191octets_low[0x20];
1672
1673 u8 ether_stats_pkts8192to10239octets_high[0x20];
1674
1675 u8 ether_stats_pkts8192to10239octets_low[0x20];
1676
1677 u8 reserved_at_540[0x280];
1678};
1679
1680struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1681 u8 if_in_octets_high[0x20];
1682
1683 u8 if_in_octets_low[0x20];
1684
1685 u8 if_in_ucast_pkts_high[0x20];
1686
1687 u8 if_in_ucast_pkts_low[0x20];
1688
1689 u8 if_in_discards_high[0x20];
1690
1691 u8 if_in_discards_low[0x20];
1692
1693 u8 if_in_errors_high[0x20];
1694
1695 u8 if_in_errors_low[0x20];
1696
1697 u8 if_in_unknown_protos_high[0x20];
1698
1699 u8 if_in_unknown_protos_low[0x20];
1700
1701 u8 if_out_octets_high[0x20];
1702
1703 u8 if_out_octets_low[0x20];
1704
1705 u8 if_out_ucast_pkts_high[0x20];
1706
1707 u8 if_out_ucast_pkts_low[0x20];
1708
1709 u8 if_out_discards_high[0x20];
1710
1711 u8 if_out_discards_low[0x20];
1712
1713 u8 if_out_errors_high[0x20];
1714
1715 u8 if_out_errors_low[0x20];
1716
1717 u8 if_in_multicast_pkts_high[0x20];
1718
1719 u8 if_in_multicast_pkts_low[0x20];
1720
1721 u8 if_in_broadcast_pkts_high[0x20];
1722
1723 u8 if_in_broadcast_pkts_low[0x20];
1724
1725 u8 if_out_multicast_pkts_high[0x20];
1726
1727 u8 if_out_multicast_pkts_low[0x20];
1728
1729 u8 if_out_broadcast_pkts_high[0x20];
1730
1731 u8 if_out_broadcast_pkts_low[0x20];
1732
1733 u8 reserved_at_340[0x480];
1734};
1735
1736struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1737 u8 a_frames_transmitted_ok_high[0x20];
1738
1739 u8 a_frames_transmitted_ok_low[0x20];
1740
1741 u8 a_frames_received_ok_high[0x20];
1742
1743 u8 a_frames_received_ok_low[0x20];
1744
1745 u8 a_frame_check_sequence_errors_high[0x20];
1746
1747 u8 a_frame_check_sequence_errors_low[0x20];
1748
1749 u8 a_alignment_errors_high[0x20];
1750
1751 u8 a_alignment_errors_low[0x20];
1752
1753 u8 a_octets_transmitted_ok_high[0x20];
1754
1755 u8 a_octets_transmitted_ok_low[0x20];
1756
1757 u8 a_octets_received_ok_high[0x20];
1758
1759 u8 a_octets_received_ok_low[0x20];
1760
1761 u8 a_multicast_frames_xmitted_ok_high[0x20];
1762
1763 u8 a_multicast_frames_xmitted_ok_low[0x20];
1764
1765 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1766
1767 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1768
1769 u8 a_multicast_frames_received_ok_high[0x20];
1770
1771 u8 a_multicast_frames_received_ok_low[0x20];
1772
1773 u8 a_broadcast_frames_received_ok_high[0x20];
1774
1775 u8 a_broadcast_frames_received_ok_low[0x20];
1776
1777 u8 a_in_range_length_errors_high[0x20];
1778
1779 u8 a_in_range_length_errors_low[0x20];
1780
1781 u8 a_out_of_range_length_field_high[0x20];
1782
1783 u8 a_out_of_range_length_field_low[0x20];
1784
1785 u8 a_frame_too_long_errors_high[0x20];
1786
1787 u8 a_frame_too_long_errors_low[0x20];
1788
1789 u8 a_symbol_error_during_carrier_high[0x20];
1790
1791 u8 a_symbol_error_during_carrier_low[0x20];
1792
1793 u8 a_mac_control_frames_transmitted_high[0x20];
1794
1795 u8 a_mac_control_frames_transmitted_low[0x20];
1796
1797 u8 a_mac_control_frames_received_high[0x20];
1798
1799 u8 a_mac_control_frames_received_low[0x20];
1800
1801 u8 a_unsupported_opcodes_received_high[0x20];
1802
1803 u8 a_unsupported_opcodes_received_low[0x20];
1804
1805 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1806
1807 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1808
1809 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1810
1811 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1812
1813 u8 reserved_at_4c0[0x300];
1814};
1815
1816struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1817 u8 life_time_counter_high[0x20];
1818
1819 u8 life_time_counter_low[0x20];
1820
1821 u8 rx_errors[0x20];
1822
1823 u8 tx_errors[0x20];
1824
1825 u8 l0_to_recovery_eieos[0x20];
1826
1827 u8 l0_to_recovery_ts[0x20];
1828
1829 u8 l0_to_recovery_framing[0x20];
1830
1831 u8 l0_to_recovery_retrain[0x20];
1832
1833 u8 crc_error_dllp[0x20];
1834
1835 u8 crc_error_tlp[0x20];
1836
1837 u8 reserved_at_140[0x680];
1838};
1839
1840struct mlx5_ifc_cmd_inter_comp_event_bits {
1841 u8 command_completion_vector[0x20];
1842
1843 u8 reserved_at_20[0xc0];
1844};
1845
1846struct mlx5_ifc_stall_vl_event_bits {
1847 u8 reserved_at_0[0x18];
1848 u8 port_num[0x1];
1849 u8 reserved_at_19[0x3];
1850 u8 vl[0x4];
1851
1852 u8 reserved_at_20[0xa0];
1853};
1854
1855struct mlx5_ifc_db_bf_congestion_event_bits {
1856 u8 event_subtype[0x8];
1857 u8 reserved_at_8[0x8];
1858 u8 congestion_level[0x8];
1859 u8 reserved_at_18[0x8];
1860
1861 u8 reserved_at_20[0xa0];
1862};
1863
1864struct mlx5_ifc_gpio_event_bits {
1865 u8 reserved_at_0[0x60];
1866
1867 u8 gpio_event_hi[0x20];
1868
1869 u8 gpio_event_lo[0x20];
1870
1871 u8 reserved_at_a0[0x40];
1872};
1873
1874struct mlx5_ifc_port_state_change_event_bits {
1875 u8 reserved_at_0[0x40];
1876
1877 u8 port_num[0x4];
1878 u8 reserved_at_44[0x1c];
1879
1880 u8 reserved_at_60[0x80];
1881};
1882
1883struct mlx5_ifc_dropped_packet_logged_bits {
1884 u8 reserved_at_0[0xe0];
1885};
1886
1887enum {
1888 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1889 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1890};
1891
1892struct mlx5_ifc_cq_error_bits {
1893 u8 reserved_at_0[0x8];
1894 u8 cqn[0x18];
1895
1896 u8 reserved_at_20[0x20];
1897
1898 u8 reserved_at_40[0x18];
1899 u8 syndrome[0x8];
1900
1901 u8 reserved_at_60[0x80];
1902};
1903
1904struct mlx5_ifc_rdma_page_fault_event_bits {
1905 u8 bytes_committed[0x20];
1906
1907 u8 r_key[0x20];
1908
1909 u8 reserved_at_40[0x10];
1910 u8 packet_len[0x10];
1911
1912 u8 rdma_op_len[0x20];
1913
1914 u8 rdma_va[0x40];
1915
1916 u8 reserved_at_c0[0x5];
1917 u8 rdma[0x1];
1918 u8 write[0x1];
1919 u8 requestor[0x1];
1920 u8 qp_number[0x18];
1921};
1922
1923struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1924 u8 bytes_committed[0x20];
1925
1926 u8 reserved_at_20[0x10];
1927 u8 wqe_index[0x10];
1928
1929 u8 reserved_at_40[0x10];
1930 u8 len[0x10];
1931
1932 u8 reserved_at_60[0x60];
1933
1934 u8 reserved_at_c0[0x5];
1935 u8 rdma[0x1];
1936 u8 write_read[0x1];
1937 u8 requestor[0x1];
1938 u8 qpn[0x18];
1939};
1940
1941struct mlx5_ifc_qp_events_bits {
1942 u8 reserved_at_0[0xa0];
1943
1944 u8 type[0x8];
1945 u8 reserved_at_a8[0x18];
1946
1947 u8 reserved_at_c0[0x8];
1948 u8 qpn_rqn_sqn[0x18];
1949};
1950
1951struct mlx5_ifc_dct_events_bits {
1952 u8 reserved_at_0[0xc0];
1953
1954 u8 reserved_at_c0[0x8];
1955 u8 dct_number[0x18];
1956};
1957
1958struct mlx5_ifc_comp_event_bits {
1959 u8 reserved_at_0[0xc0];
1960
1961 u8 reserved_at_c0[0x8];
1962 u8 cq_number[0x18];
1963};
1964
1965enum {
1966 MLX5_QPC_STATE_RST = 0x0,
1967 MLX5_QPC_STATE_INIT = 0x1,
1968 MLX5_QPC_STATE_RTR = 0x2,
1969 MLX5_QPC_STATE_RTS = 0x3,
1970 MLX5_QPC_STATE_SQER = 0x4,
1971 MLX5_QPC_STATE_ERR = 0x6,
1972 MLX5_QPC_STATE_SQD = 0x7,
1973 MLX5_QPC_STATE_SUSPENDED = 0x9,
1974};
1975
1976enum {
1977 MLX5_QPC_ST_RC = 0x0,
1978 MLX5_QPC_ST_UC = 0x1,
1979 MLX5_QPC_ST_UD = 0x2,
1980 MLX5_QPC_ST_XRC = 0x3,
1981 MLX5_QPC_ST_DCI = 0x5,
1982 MLX5_QPC_ST_QP0 = 0x7,
1983 MLX5_QPC_ST_QP1 = 0x8,
1984 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1985 MLX5_QPC_ST_REG_UMR = 0xc,
1986};
1987
1988enum {
1989 MLX5_QPC_PM_STATE_ARMED = 0x0,
1990 MLX5_QPC_PM_STATE_REARM = 0x1,
1991 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1992 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1993};
1994
1995enum {
1996 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1997 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1998};
1999
2000enum {
2001 MLX5_QPC_MTU_256_BYTES = 0x1,
2002 MLX5_QPC_MTU_512_BYTES = 0x2,
2003 MLX5_QPC_MTU_1K_BYTES = 0x3,
2004 MLX5_QPC_MTU_2K_BYTES = 0x4,
2005 MLX5_QPC_MTU_4K_BYTES = 0x5,
2006 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2007};
2008
2009enum {
2010 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2011 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2012 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2013 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2014 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2015 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2016 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2017 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2018};
2019
2020enum {
2021 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2022 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2023 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2024};
2025
2026enum {
2027 MLX5_QPC_CS_RES_DISABLE = 0x0,
2028 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2029 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2030};
2031
2032struct mlx5_ifc_qpc_bits {
2033 u8 state[0x4];
2034 u8 lag_tx_port_affinity[0x4];
2035 u8 st[0x8];
2036 u8 reserved_at_10[0x3];
2037 u8 pm_state[0x2];
2038 u8 reserved_at_15[0x7];
2039 u8 end_padding_mode[0x2];
2040 u8 reserved_at_1e[0x2];
2041
2042 u8 wq_signature[0x1];
2043 u8 block_lb_mc[0x1];
2044 u8 atomic_like_write_en[0x1];
2045 u8 latency_sensitive[0x1];
2046 u8 reserved_at_24[0x1];
2047 u8 drain_sigerr[0x1];
2048 u8 reserved_at_26[0x2];
2049 u8 pd[0x18];
2050
2051 u8 mtu[0x3];
2052 u8 log_msg_max[0x5];
2053 u8 reserved_at_48[0x1];
2054 u8 log_rq_size[0x4];
2055 u8 log_rq_stride[0x3];
2056 u8 no_sq[0x1];
2057 u8 log_sq_size[0x4];
2058 u8 reserved_at_55[0x6];
2059 u8 rlky[0x1];
2060 u8 ulp_stateless_offload_mode[0x4];
2061
2062 u8 counter_set_id[0x8];
2063 u8 uar_page[0x18];
2064
2065 u8 reserved_at_80[0x8];
2066 u8 user_index[0x18];
2067
2068 u8 reserved_at_a0[0x3];
2069 u8 log_page_size[0x5];
2070 u8 remote_qpn[0x18];
2071
2072 struct mlx5_ifc_ads_bits primary_address_path;
2073
2074 struct mlx5_ifc_ads_bits secondary_address_path;
2075
2076 u8 log_ack_req_freq[0x4];
2077 u8 reserved_at_384[0x4];
2078 u8 log_sra_max[0x3];
2079 u8 reserved_at_38b[0x2];
2080 u8 retry_count[0x3];
2081 u8 rnr_retry[0x3];
2082 u8 reserved_at_393[0x1];
2083 u8 fre[0x1];
2084 u8 cur_rnr_retry[0x3];
2085 u8 cur_retry_count[0x3];
2086 u8 reserved_at_39b[0x5];
2087
2088 u8 reserved_at_3a0[0x20];
2089
2090 u8 reserved_at_3c0[0x8];
2091 u8 next_send_psn[0x18];
2092
2093 u8 reserved_at_3e0[0x8];
2094 u8 cqn_snd[0x18];
2095
2096 u8 reserved_at_400[0x8];
2097 u8 deth_sqpn[0x18];
2098
2099 u8 reserved_at_420[0x20];
2100
2101 u8 reserved_at_440[0x8];
2102 u8 last_acked_psn[0x18];
2103
2104 u8 reserved_at_460[0x8];
2105 u8 ssn[0x18];
2106
2107 u8 reserved_at_480[0x8];
2108 u8 log_rra_max[0x3];
2109 u8 reserved_at_48b[0x1];
2110 u8 atomic_mode[0x4];
2111 u8 rre[0x1];
2112 u8 rwe[0x1];
2113 u8 rae[0x1];
2114 u8 reserved_at_493[0x1];
2115 u8 page_offset[0x6];
2116 u8 reserved_at_49a[0x3];
2117 u8 cd_slave_receive[0x1];
2118 u8 cd_slave_send[0x1];
2119 u8 cd_master[0x1];
2120
2121 u8 reserved_at_4a0[0x3];
2122 u8 min_rnr_nak[0x5];
2123 u8 next_rcv_psn[0x18];
2124
2125 u8 reserved_at_4c0[0x8];
2126 u8 xrcd[0x18];
2127
2128 u8 reserved_at_4e0[0x8];
2129 u8 cqn_rcv[0x18];
2130
2131 u8 dbr_addr[0x40];
2132
2133 u8 q_key[0x20];
2134
2135 u8 reserved_at_560[0x5];
2136 u8 rq_type[0x3];
2137 u8 srqn_rmpn_xrqn[0x18];
2138
2139 u8 reserved_at_580[0x8];
2140 u8 rmsn[0x18];
2141
2142 u8 hw_sq_wqebb_counter[0x10];
2143 u8 sw_sq_wqebb_counter[0x10];
2144
2145 u8 hw_rq_counter[0x20];
2146
2147 u8 sw_rq_counter[0x20];
2148
2149 u8 reserved_at_600[0x20];
2150
2151 u8 reserved_at_620[0xf];
2152 u8 cgs[0x1];
2153 u8 cs_req[0x8];
2154 u8 cs_res[0x8];
2155
2156 u8 dc_access_key[0x40];
2157
2158 u8 reserved_at_680[0xc0];
2159};
2160
2161struct mlx5_ifc_roce_addr_layout_bits {
2162 u8 source_l3_address[16][0x8];
2163
2164 u8 reserved_at_80[0x3];
2165 u8 vlan_valid[0x1];
2166 u8 vlan_id[0xc];
2167 u8 source_mac_47_32[0x10];
2168
2169 u8 source_mac_31_0[0x20];
2170
2171 u8 reserved_at_c0[0x14];
2172 u8 roce_l3_type[0x4];
2173 u8 roce_version[0x8];
2174
2175 u8 reserved_at_e0[0x20];
2176};
2177
2178union mlx5_ifc_hca_cap_union_bits {
2179 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2180 struct mlx5_ifc_odp_cap_bits odp_cap;
2181 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2182 struct mlx5_ifc_roce_cap_bits roce_cap;
2183 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2184 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2185 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2186 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2187 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2188 struct mlx5_ifc_qos_cap_bits qos_cap;
2189 u8 reserved_at_0[0x8000];
2190};
2191
2192enum {
2193 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2194 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2195 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2196 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2197 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2198 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2199 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2200};
2201
2202struct mlx5_ifc_flow_context_bits {
2203 u8 reserved_at_0[0x20];
2204
2205 u8 group_id[0x20];
2206
2207 u8 reserved_at_40[0x8];
2208 u8 flow_tag[0x18];
2209
2210 u8 reserved_at_60[0x10];
2211 u8 action[0x10];
2212
2213 u8 reserved_at_80[0x8];
2214 u8 destination_list_size[0x18];
2215
2216 u8 reserved_at_a0[0x8];
2217 u8 flow_counter_list_size[0x18];
2218
2219 u8 encap_id[0x20];
2220
2221 u8 modify_header_id[0x20];
2222
2223 u8 reserved_at_100[0x100];
2224
2225 struct mlx5_ifc_fte_match_param_bits match_value;
2226
2227 u8 reserved_at_1200[0x600];
2228
2229 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2230};
2231
2232enum {
2233 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2234 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2235};
2236
2237struct mlx5_ifc_xrc_srqc_bits {
2238 u8 state[0x4];
2239 u8 log_xrc_srq_size[0x4];
2240 u8 reserved_at_8[0x18];
2241
2242 u8 wq_signature[0x1];
2243 u8 cont_srq[0x1];
2244 u8 reserved_at_22[0x1];
2245 u8 rlky[0x1];
2246 u8 basic_cyclic_rcv_wqe[0x1];
2247 u8 log_rq_stride[0x3];
2248 u8 xrcd[0x18];
2249
2250 u8 page_offset[0x6];
2251 u8 reserved_at_46[0x2];
2252 u8 cqn[0x18];
2253
2254 u8 reserved_at_60[0x20];
2255
2256 u8 user_index_equal_xrc_srqn[0x1];
2257 u8 reserved_at_81[0x1];
2258 u8 log_page_size[0x6];
2259 u8 user_index[0x18];
2260
2261 u8 reserved_at_a0[0x20];
2262
2263 u8 reserved_at_c0[0x8];
2264 u8 pd[0x18];
2265
2266 u8 lwm[0x10];
2267 u8 wqe_cnt[0x10];
2268
2269 u8 reserved_at_100[0x40];
2270
2271 u8 db_record_addr_h[0x20];
2272
2273 u8 db_record_addr_l[0x1e];
2274 u8 reserved_at_17e[0x2];
2275
2276 u8 reserved_at_180[0x80];
2277};
2278
2279struct mlx5_ifc_traffic_counter_bits {
2280 u8 packets[0x40];
2281
2282 u8 octets[0x40];
2283};
2284
2285struct mlx5_ifc_tisc_bits {
2286 u8 strict_lag_tx_port_affinity[0x1];
2287 u8 reserved_at_1[0x3];
2288 u8 lag_tx_port_affinity[0x04];
2289
2290 u8 reserved_at_8[0x4];
2291 u8 prio[0x4];
2292 u8 reserved_at_10[0x10];
2293
2294 u8 reserved_at_20[0x100];
2295
2296 u8 reserved_at_120[0x8];
2297 u8 transport_domain[0x18];
2298
2299 u8 reserved_at_140[0x8];
2300 u8 underlay_qpn[0x18];
2301 u8 reserved_at_160[0x3a0];
2302};
2303
2304enum {
2305 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2306 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2307};
2308
2309enum {
2310 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2311 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2312};
2313
2314enum {
2315 MLX5_RX_HASH_FN_NONE = 0x0,
2316 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2317 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2318};
2319
2320enum {
2321 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2322 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2323};
2324
2325struct mlx5_ifc_tirc_bits {
2326 u8 reserved_at_0[0x20];
2327
2328 u8 disp_type[0x4];
2329 u8 reserved_at_24[0x1c];
2330
2331 u8 reserved_at_40[0x40];
2332
2333 u8 reserved_at_80[0x4];
2334 u8 lro_timeout_period_usecs[0x10];
2335 u8 lro_enable_mask[0x4];
2336 u8 lro_max_ip_payload_size[0x8];
2337
2338 u8 reserved_at_a0[0x40];
2339
2340 u8 reserved_at_e0[0x8];
2341 u8 inline_rqn[0x18];
2342
2343 u8 rx_hash_symmetric[0x1];
2344 u8 reserved_at_101[0x1];
2345 u8 tunneled_offload_en[0x1];
2346 u8 reserved_at_103[0x5];
2347 u8 indirect_table[0x18];
2348
2349 u8 rx_hash_fn[0x4];
2350 u8 reserved_at_124[0x2];
2351 u8 self_lb_block[0x2];
2352 u8 transport_domain[0x18];
2353
2354 u8 rx_hash_toeplitz_key[10][0x20];
2355
2356 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2357
2358 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2359
2360 u8 reserved_at_2c0[0x4c0];
2361};
2362
2363enum {
2364 MLX5_SRQC_STATE_GOOD = 0x0,
2365 MLX5_SRQC_STATE_ERROR = 0x1,
2366};
2367
2368struct mlx5_ifc_srqc_bits {
2369 u8 state[0x4];
2370 u8 log_srq_size[0x4];
2371 u8 reserved_at_8[0x18];
2372
2373 u8 wq_signature[0x1];
2374 u8 cont_srq[0x1];
2375 u8 reserved_at_22[0x1];
2376 u8 rlky[0x1];
2377 u8 reserved_at_24[0x1];
2378 u8 log_rq_stride[0x3];
2379 u8 xrcd[0x18];
2380
2381 u8 page_offset[0x6];
2382 u8 reserved_at_46[0x2];
2383 u8 cqn[0x18];
2384
2385 u8 reserved_at_60[0x20];
2386
2387 u8 reserved_at_80[0x2];
2388 u8 log_page_size[0x6];
2389 u8 reserved_at_88[0x18];
2390
2391 u8 reserved_at_a0[0x20];
2392
2393 u8 reserved_at_c0[0x8];
2394 u8 pd[0x18];
2395
2396 u8 lwm[0x10];
2397 u8 wqe_cnt[0x10];
2398
2399 u8 reserved_at_100[0x40];
2400
2401 u8 dbr_addr[0x40];
2402
2403 u8 reserved_at_180[0x80];
2404};
2405
2406enum {
2407 MLX5_SQC_STATE_RST = 0x0,
2408 MLX5_SQC_STATE_RDY = 0x1,
2409 MLX5_SQC_STATE_ERR = 0x3,
2410};
2411
2412struct mlx5_ifc_sqc_bits {
2413 u8 rlky[0x1];
2414 u8 cd_master[0x1];
2415 u8 fre[0x1];
2416 u8 flush_in_error_en[0x1];
2417 u8 reserved_at_4[0x1];
2418 u8 min_wqe_inline_mode[0x3];
2419 u8 state[0x4];
2420 u8 reg_umr[0x1];
2421 u8 reserved_at_d[0x13];
2422
2423 u8 reserved_at_20[0x8];
2424 u8 user_index[0x18];
2425
2426 u8 reserved_at_40[0x8];
2427 u8 cqn[0x18];
2428
2429 u8 reserved_at_60[0x90];
2430
2431 u8 packet_pacing_rate_limit_index[0x10];
2432 u8 tis_lst_sz[0x10];
2433 u8 reserved_at_110[0x10];
2434
2435 u8 reserved_at_120[0x40];
2436
2437 u8 reserved_at_160[0x8];
2438 u8 tis_num_0[0x18];
2439
2440 struct mlx5_ifc_wq_bits wq;
2441};
2442
2443enum {
2444 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2445 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2446 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2447 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2448};
2449
2450struct mlx5_ifc_scheduling_context_bits {
2451 u8 element_type[0x8];
2452 u8 reserved_at_8[0x18];
2453
2454 u8 element_attributes[0x20];
2455
2456 u8 parent_element_id[0x20];
2457
2458 u8 reserved_at_60[0x40];
2459
2460 u8 bw_share[0x20];
2461
2462 u8 max_average_bw[0x20];
2463
2464 u8 reserved_at_e0[0x120];
2465};
2466
2467struct mlx5_ifc_rqtc_bits {
2468 u8 reserved_at_0[0xa0];
2469
2470 u8 reserved_at_a0[0x10];
2471 u8 rqt_max_size[0x10];
2472
2473 u8 reserved_at_c0[0x10];
2474 u8 rqt_actual_size[0x10];
2475
2476 u8 reserved_at_e0[0x6a0];
2477
2478 struct mlx5_ifc_rq_num_bits rq_num[0];
2479};
2480
2481enum {
2482 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2483 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2484};
2485
2486enum {
2487 MLX5_RQC_STATE_RST = 0x0,
2488 MLX5_RQC_STATE_RDY = 0x1,
2489 MLX5_RQC_STATE_ERR = 0x3,
2490};
2491
2492struct mlx5_ifc_rqc_bits {
2493 u8 rlky[0x1];
2494 u8 reserved_at_1[0x1];
2495 u8 scatter_fcs[0x1];
2496 u8 vsd[0x1];
2497 u8 mem_rq_type[0x4];
2498 u8 state[0x4];
2499 u8 reserved_at_c[0x1];
2500 u8 flush_in_error_en[0x1];
2501 u8 reserved_at_e[0x12];
2502
2503 u8 reserved_at_20[0x8];
2504 u8 user_index[0x18];
2505
2506 u8 reserved_at_40[0x8];
2507 u8 cqn[0x18];
2508
2509 u8 counter_set_id[0x8];
2510 u8 reserved_at_68[0x18];
2511
2512 u8 reserved_at_80[0x8];
2513 u8 rmpn[0x18];
2514
2515 u8 reserved_at_a0[0xe0];
2516
2517 struct mlx5_ifc_wq_bits wq;
2518};
2519
2520enum {
2521 MLX5_RMPC_STATE_RDY = 0x1,
2522 MLX5_RMPC_STATE_ERR = 0x3,
2523};
2524
2525struct mlx5_ifc_rmpc_bits {
2526 u8 reserved_at_0[0x8];
2527 u8 state[0x4];
2528 u8 reserved_at_c[0x14];
2529
2530 u8 basic_cyclic_rcv_wqe[0x1];
2531 u8 reserved_at_21[0x1f];
2532
2533 u8 reserved_at_40[0x140];
2534
2535 struct mlx5_ifc_wq_bits wq;
2536};
2537
2538struct mlx5_ifc_nic_vport_context_bits {
2539 u8 reserved_at_0[0x5];
2540 u8 min_wqe_inline_mode[0x3];
2541 u8 reserved_at_8[0x17];
2542 u8 roce_en[0x1];
2543
2544 u8 arm_change_event[0x1];
2545 u8 reserved_at_21[0x1a];
2546 u8 event_on_mtu[0x1];
2547 u8 event_on_promisc_change[0x1];
2548 u8 event_on_vlan_change[0x1];
2549 u8 event_on_mc_address_change[0x1];
2550 u8 event_on_uc_address_change[0x1];
2551
2552 u8 reserved_at_40[0xf0];
2553
2554 u8 mtu[0x10];
2555
2556 u8 system_image_guid[0x40];
2557 u8 port_guid[0x40];
2558 u8 node_guid[0x40];
2559
2560 u8 reserved_at_200[0x140];
2561 u8 qkey_violation_counter[0x10];
2562 u8 reserved_at_350[0x430];
2563
2564 u8 promisc_uc[0x1];
2565 u8 promisc_mc[0x1];
2566 u8 promisc_all[0x1];
2567 u8 reserved_at_783[0x2];
2568 u8 allowed_list_type[0x3];
2569 u8 reserved_at_788[0xc];
2570 u8 allowed_list_size[0xc];
2571
2572 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2573
2574 u8 reserved_at_7e0[0x20];
2575
2576 u8 current_uc_mac_address[0][0x40];
2577};
2578
2579enum {
2580 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2581 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2582 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2583 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2584};
2585
2586struct mlx5_ifc_mkc_bits {
2587 u8 reserved_at_0[0x1];
2588 u8 free[0x1];
2589 u8 reserved_at_2[0xd];
2590 u8 small_fence_on_rdma_read_response[0x1];
2591 u8 umr_en[0x1];
2592 u8 a[0x1];
2593 u8 rw[0x1];
2594 u8 rr[0x1];
2595 u8 lw[0x1];
2596 u8 lr[0x1];
2597 u8 access_mode[0x2];
2598 u8 reserved_at_18[0x8];
2599
2600 u8 qpn[0x18];
2601 u8 mkey_7_0[0x8];
2602
2603 u8 reserved_at_40[0x20];
2604
2605 u8 length64[0x1];
2606 u8 bsf_en[0x1];
2607 u8 sync_umr[0x1];
2608 u8 reserved_at_63[0x2];
2609 u8 expected_sigerr_count[0x1];
2610 u8 reserved_at_66[0x1];
2611 u8 en_rinval[0x1];
2612 u8 pd[0x18];
2613
2614 u8 start_addr[0x40];
2615
2616 u8 len[0x40];
2617
2618 u8 bsf_octword_size[0x20];
2619
2620 u8 reserved_at_120[0x80];
2621
2622 u8 translations_octword_size[0x20];
2623
2624 u8 reserved_at_1c0[0x1b];
2625 u8 log_page_size[0x5];
2626
2627 u8 reserved_at_1e0[0x20];
2628};
2629
2630struct mlx5_ifc_pkey_bits {
2631 u8 reserved_at_0[0x10];
2632 u8 pkey[0x10];
2633};
2634
2635struct mlx5_ifc_array128_auto_bits {
2636 u8 array128_auto[16][0x8];
2637};
2638
2639struct mlx5_ifc_hca_vport_context_bits {
2640 u8 field_select[0x20];
2641
2642 u8 reserved_at_20[0xe0];
2643
2644 u8 sm_virt_aware[0x1];
2645 u8 has_smi[0x1];
2646 u8 has_raw[0x1];
2647 u8 grh_required[0x1];
2648 u8 reserved_at_104[0xc];
2649 u8 port_physical_state[0x4];
2650 u8 vport_state_policy[0x4];
2651 u8 port_state[0x4];
2652 u8 vport_state[0x4];
2653
2654 u8 reserved_at_120[0x20];
2655
2656 u8 system_image_guid[0x40];
2657
2658 u8 port_guid[0x40];
2659
2660 u8 node_guid[0x40];
2661
2662 u8 cap_mask1[0x20];
2663
2664 u8 cap_mask1_field_select[0x20];
2665
2666 u8 cap_mask2[0x20];
2667
2668 u8 cap_mask2_field_select[0x20];
2669
2670 u8 reserved_at_280[0x80];
2671
2672 u8 lid[0x10];
2673 u8 reserved_at_310[0x4];
2674 u8 init_type_reply[0x4];
2675 u8 lmc[0x3];
2676 u8 subnet_timeout[0x5];
2677
2678 u8 sm_lid[0x10];
2679 u8 sm_sl[0x4];
2680 u8 reserved_at_334[0xc];
2681
2682 u8 qkey_violation_counter[0x10];
2683 u8 pkey_violation_counter[0x10];
2684
2685 u8 reserved_at_360[0xca0];
2686};
2687
2688struct mlx5_ifc_esw_vport_context_bits {
2689 u8 reserved_at_0[0x3];
2690 u8 vport_svlan_strip[0x1];
2691 u8 vport_cvlan_strip[0x1];
2692 u8 vport_svlan_insert[0x1];
2693 u8 vport_cvlan_insert[0x2];
2694 u8 reserved_at_8[0x18];
2695
2696 u8 reserved_at_20[0x20];
2697
2698 u8 svlan_cfi[0x1];
2699 u8 svlan_pcp[0x3];
2700 u8 svlan_id[0xc];
2701 u8 cvlan_cfi[0x1];
2702 u8 cvlan_pcp[0x3];
2703 u8 cvlan_id[0xc];
2704
2705 u8 reserved_at_60[0x7a0];
2706};
2707
2708enum {
2709 MLX5_EQC_STATUS_OK = 0x0,
2710 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2711};
2712
2713enum {
2714 MLX5_EQC_ST_ARMED = 0x9,
2715 MLX5_EQC_ST_FIRED = 0xa,
2716};
2717
2718struct mlx5_ifc_eqc_bits {
2719 u8 status[0x4];
2720 u8 reserved_at_4[0x9];
2721 u8 ec[0x1];
2722 u8 oi[0x1];
2723 u8 reserved_at_f[0x5];
2724 u8 st[0x4];
2725 u8 reserved_at_18[0x8];
2726
2727 u8 reserved_at_20[0x20];
2728
2729 u8 reserved_at_40[0x14];
2730 u8 page_offset[0x6];
2731 u8 reserved_at_5a[0x6];
2732
2733 u8 reserved_at_60[0x3];
2734 u8 log_eq_size[0x5];
2735 u8 uar_page[0x18];
2736
2737 u8 reserved_at_80[0x20];
2738
2739 u8 reserved_at_a0[0x18];
2740 u8 intr[0x8];
2741
2742 u8 reserved_at_c0[0x3];
2743 u8 log_page_size[0x5];
2744 u8 reserved_at_c8[0x18];
2745
2746 u8 reserved_at_e0[0x60];
2747
2748 u8 reserved_at_140[0x8];
2749 u8 consumer_counter[0x18];
2750
2751 u8 reserved_at_160[0x8];
2752 u8 producer_counter[0x18];
2753
2754 u8 reserved_at_180[0x80];
2755};
2756
2757enum {
2758 MLX5_DCTC_STATE_ACTIVE = 0x0,
2759 MLX5_DCTC_STATE_DRAINING = 0x1,
2760 MLX5_DCTC_STATE_DRAINED = 0x2,
2761};
2762
2763enum {
2764 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2765 MLX5_DCTC_CS_RES_NA = 0x1,
2766 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2767};
2768
2769enum {
2770 MLX5_DCTC_MTU_256_BYTES = 0x1,
2771 MLX5_DCTC_MTU_512_BYTES = 0x2,
2772 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2773 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2774 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2775};
2776
2777struct mlx5_ifc_dctc_bits {
2778 u8 reserved_at_0[0x4];
2779 u8 state[0x4];
2780 u8 reserved_at_8[0x18];
2781
2782 u8 reserved_at_20[0x8];
2783 u8 user_index[0x18];
2784
2785 u8 reserved_at_40[0x8];
2786 u8 cqn[0x18];
2787
2788 u8 counter_set_id[0x8];
2789 u8 atomic_mode[0x4];
2790 u8 rre[0x1];
2791 u8 rwe[0x1];
2792 u8 rae[0x1];
2793 u8 atomic_like_write_en[0x1];
2794 u8 latency_sensitive[0x1];
2795 u8 rlky[0x1];
2796 u8 free_ar[0x1];
2797 u8 reserved_at_73[0xd];
2798
2799 u8 reserved_at_80[0x8];
2800 u8 cs_res[0x8];
2801 u8 reserved_at_90[0x3];
2802 u8 min_rnr_nak[0x5];
2803 u8 reserved_at_98[0x8];
2804
2805 u8 reserved_at_a0[0x8];
2806 u8 srqn_xrqn[0x18];
2807
2808 u8 reserved_at_c0[0x8];
2809 u8 pd[0x18];
2810
2811 u8 tclass[0x8];
2812 u8 reserved_at_e8[0x4];
2813 u8 flow_label[0x14];
2814
2815 u8 dc_access_key[0x40];
2816
2817 u8 reserved_at_140[0x5];
2818 u8 mtu[0x3];
2819 u8 port[0x8];
2820 u8 pkey_index[0x10];
2821
2822 u8 reserved_at_160[0x8];
2823 u8 my_addr_index[0x8];
2824 u8 reserved_at_170[0x8];
2825 u8 hop_limit[0x8];
2826
2827 u8 dc_access_key_violation_count[0x20];
2828
2829 u8 reserved_at_1a0[0x14];
2830 u8 dei_cfi[0x1];
2831 u8 eth_prio[0x3];
2832 u8 ecn[0x2];
2833 u8 dscp[0x6];
2834
2835 u8 reserved_at_1c0[0x40];
2836};
2837
2838enum {
2839 MLX5_CQC_STATUS_OK = 0x0,
2840 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2841 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2842};
2843
2844enum {
2845 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2846 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2847};
2848
2849enum {
2850 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2851 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2852 MLX5_CQC_ST_FIRED = 0xa,
2853};
2854
2855enum {
2856 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2857 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2858 MLX5_CQ_PERIOD_NUM_MODES
2859};
2860
2861struct mlx5_ifc_cqc_bits {
2862 u8 status[0x4];
2863 u8 reserved_at_4[0x4];
2864 u8 cqe_sz[0x3];
2865 u8 cc[0x1];
2866 u8 reserved_at_c[0x1];
2867 u8 scqe_break_moderation_en[0x1];
2868 u8 oi[0x1];
2869 u8 cq_period_mode[0x2];
2870 u8 cqe_comp_en[0x1];
2871 u8 mini_cqe_res_format[0x2];
2872 u8 st[0x4];
2873 u8 reserved_at_18[0x8];
2874
2875 u8 reserved_at_20[0x20];
2876
2877 u8 reserved_at_40[0x14];
2878 u8 page_offset[0x6];
2879 u8 reserved_at_5a[0x6];
2880
2881 u8 reserved_at_60[0x3];
2882 u8 log_cq_size[0x5];
2883 u8 uar_page[0x18];
2884
2885 u8 reserved_at_80[0x4];
2886 u8 cq_period[0xc];
2887 u8 cq_max_count[0x10];
2888
2889 u8 reserved_at_a0[0x18];
2890 u8 c_eqn[0x8];
2891
2892 u8 reserved_at_c0[0x3];
2893 u8 log_page_size[0x5];
2894 u8 reserved_at_c8[0x18];
2895
2896 u8 reserved_at_e0[0x20];
2897
2898 u8 reserved_at_100[0x8];
2899 u8 last_notified_index[0x18];
2900
2901 u8 reserved_at_120[0x8];
2902 u8 last_solicit_index[0x18];
2903
2904 u8 reserved_at_140[0x8];
2905 u8 consumer_counter[0x18];
2906
2907 u8 reserved_at_160[0x8];
2908 u8 producer_counter[0x18];
2909
2910 u8 reserved_at_180[0x40];
2911
2912 u8 dbr_addr[0x40];
2913};
2914
2915union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2916 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2917 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2918 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2919 u8 reserved_at_0[0x800];
2920};
2921
2922struct mlx5_ifc_query_adapter_param_block_bits {
2923 u8 reserved_at_0[0xc0];
2924
2925 u8 reserved_at_c0[0x8];
2926 u8 ieee_vendor_id[0x18];
2927
2928 u8 reserved_at_e0[0x10];
2929 u8 vsd_vendor_id[0x10];
2930
2931 u8 vsd[208][0x8];
2932
2933 u8 vsd_contd_psid[16][0x8];
2934};
2935
2936enum {
2937 MLX5_XRQC_STATE_GOOD = 0x0,
2938 MLX5_XRQC_STATE_ERROR = 0x1,
2939};
2940
2941enum {
2942 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2943 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2944};
2945
2946enum {
2947 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2948};
2949
2950struct mlx5_ifc_tag_matching_topology_context_bits {
2951 u8 log_matching_list_sz[0x4];
2952 u8 reserved_at_4[0xc];
2953 u8 append_next_index[0x10];
2954
2955 u8 sw_phase_cnt[0x10];
2956 u8 hw_phase_cnt[0x10];
2957
2958 u8 reserved_at_40[0x40];
2959};
2960
2961struct mlx5_ifc_xrqc_bits {
2962 u8 state[0x4];
2963 u8 rlkey[0x1];
2964 u8 reserved_at_5[0xf];
2965 u8 topology[0x4];
2966 u8 reserved_at_18[0x4];
2967 u8 offload[0x4];
2968
2969 u8 reserved_at_20[0x8];
2970 u8 user_index[0x18];
2971
2972 u8 reserved_at_40[0x8];
2973 u8 cqn[0x18];
2974
2975 u8 reserved_at_60[0xa0];
2976
2977 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2978
2979 u8 reserved_at_180[0x880];
2980
2981 struct mlx5_ifc_wq_bits wq;
2982};
2983
2984union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2985 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2986 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2987 u8 reserved_at_0[0x20];
2988};
2989
2990union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2991 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2992 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2993 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2994 u8 reserved_at_0[0x20];
2995};
2996
2997union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2998 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2999 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3000 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3001 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3002 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3003 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3004 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3005 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3006 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3007 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3008 u8 reserved_at_0[0x7c0];
3009};
3010
3011union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3012 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3013 u8 reserved_at_0[0x7c0];
3014};
3015
3016union mlx5_ifc_event_auto_bits {
3017 struct mlx5_ifc_comp_event_bits comp_event;
3018 struct mlx5_ifc_dct_events_bits dct_events;
3019 struct mlx5_ifc_qp_events_bits qp_events;
3020 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3021 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3022 struct mlx5_ifc_cq_error_bits cq_error;
3023 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3024 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3025 struct mlx5_ifc_gpio_event_bits gpio_event;
3026 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3027 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3028 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3029 u8 reserved_at_0[0xe0];
3030};
3031
3032struct mlx5_ifc_health_buffer_bits {
3033 u8 reserved_at_0[0x100];
3034
3035 u8 assert_existptr[0x20];
3036
3037 u8 assert_callra[0x20];
3038
3039 u8 reserved_at_140[0x40];
3040
3041 u8 fw_version[0x20];
3042
3043 u8 hw_id[0x20];
3044
3045 u8 reserved_at_1c0[0x20];
3046
3047 u8 irisc_index[0x8];
3048 u8 synd[0x8];
3049 u8 ext_synd[0x10];
3050};
3051
3052struct mlx5_ifc_register_loopback_control_bits {
3053 u8 no_lb[0x1];
3054 u8 reserved_at_1[0x7];
3055 u8 port[0x8];
3056 u8 reserved_at_10[0x10];
3057
3058 u8 reserved_at_20[0x60];
3059};
3060
3061struct mlx5_ifc_vport_tc_element_bits {
3062 u8 traffic_class[0x4];
3063 u8 reserved_at_4[0xc];
3064 u8 vport_number[0x10];
3065};
3066
3067struct mlx5_ifc_vport_element_bits {
3068 u8 reserved_at_0[0x10];
3069 u8 vport_number[0x10];
3070};
3071
3072enum {
3073 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3074 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3075 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3076};
3077
3078struct mlx5_ifc_tsar_element_bits {
3079 u8 reserved_at_0[0x8];
3080 u8 tsar_type[0x8];
3081 u8 reserved_at_10[0x10];
3082};
3083
3084struct mlx5_ifc_teardown_hca_out_bits {
3085 u8 status[0x8];
3086 u8 reserved_at_8[0x18];
3087
3088 u8 syndrome[0x20];
3089
3090 u8 reserved_at_40[0x40];
3091};
3092
3093enum {
3094 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3095 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
3096};
3097
3098struct mlx5_ifc_teardown_hca_in_bits {
3099 u8 opcode[0x10];
3100 u8 reserved_at_10[0x10];
3101
3102 u8 reserved_at_20[0x10];
3103 u8 op_mod[0x10];
3104
3105 u8 reserved_at_40[0x10];
3106 u8 profile[0x10];
3107
3108 u8 reserved_at_60[0x20];
3109};
3110
3111struct mlx5_ifc_sqerr2rts_qp_out_bits {
3112 u8 status[0x8];
3113 u8 reserved_at_8[0x18];
3114
3115 u8 syndrome[0x20];
3116
3117 u8 reserved_at_40[0x40];
3118};
3119
3120struct mlx5_ifc_sqerr2rts_qp_in_bits {
3121 u8 opcode[0x10];
3122 u8 reserved_at_10[0x10];
3123
3124 u8 reserved_at_20[0x10];
3125 u8 op_mod[0x10];
3126
3127 u8 reserved_at_40[0x8];
3128 u8 qpn[0x18];
3129
3130 u8 reserved_at_60[0x20];
3131
3132 u8 opt_param_mask[0x20];
3133
3134 u8 reserved_at_a0[0x20];
3135
3136 struct mlx5_ifc_qpc_bits qpc;
3137
3138 u8 reserved_at_800[0x80];
3139};
3140
3141struct mlx5_ifc_sqd2rts_qp_out_bits {
3142 u8 status[0x8];
3143 u8 reserved_at_8[0x18];
3144
3145 u8 syndrome[0x20];
3146
3147 u8 reserved_at_40[0x40];
3148};
3149
3150struct mlx5_ifc_sqd2rts_qp_in_bits {
3151 u8 opcode[0x10];
3152 u8 reserved_at_10[0x10];
3153
3154 u8 reserved_at_20[0x10];
3155 u8 op_mod[0x10];
3156
3157 u8 reserved_at_40[0x8];
3158 u8 qpn[0x18];
3159
3160 u8 reserved_at_60[0x20];
3161
3162 u8 opt_param_mask[0x20];
3163
3164 u8 reserved_at_a0[0x20];
3165
3166 struct mlx5_ifc_qpc_bits qpc;
3167
3168 u8 reserved_at_800[0x80];
3169};
3170
3171struct mlx5_ifc_set_roce_address_out_bits {
3172 u8 status[0x8];
3173 u8 reserved_at_8[0x18];
3174
3175 u8 syndrome[0x20];
3176
3177 u8 reserved_at_40[0x40];
3178};
3179
3180struct mlx5_ifc_set_roce_address_in_bits {
3181 u8 opcode[0x10];
3182 u8 reserved_at_10[0x10];
3183
3184 u8 reserved_at_20[0x10];
3185 u8 op_mod[0x10];
3186
3187 u8 roce_address_index[0x10];
3188 u8 reserved_at_50[0x10];
3189
3190 u8 reserved_at_60[0x20];
3191
3192 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3193};
3194
3195struct mlx5_ifc_set_mad_demux_out_bits {
3196 u8 status[0x8];
3197 u8 reserved_at_8[0x18];
3198
3199 u8 syndrome[0x20];
3200
3201 u8 reserved_at_40[0x40];
3202};
3203
3204enum {
3205 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3206 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3207};
3208
3209struct mlx5_ifc_set_mad_demux_in_bits {
3210 u8 opcode[0x10];
3211 u8 reserved_at_10[0x10];
3212
3213 u8 reserved_at_20[0x10];
3214 u8 op_mod[0x10];
3215
3216 u8 reserved_at_40[0x20];
3217
3218 u8 reserved_at_60[0x6];
3219 u8 demux_mode[0x2];
3220 u8 reserved_at_68[0x18];
3221};
3222
3223struct mlx5_ifc_set_l2_table_entry_out_bits {
3224 u8 status[0x8];
3225 u8 reserved_at_8[0x18];
3226
3227 u8 syndrome[0x20];
3228
3229 u8 reserved_at_40[0x40];
3230};
3231
3232struct mlx5_ifc_set_l2_table_entry_in_bits {
3233 u8 opcode[0x10];
3234 u8 reserved_at_10[0x10];
3235
3236 u8 reserved_at_20[0x10];
3237 u8 op_mod[0x10];
3238
3239 u8 reserved_at_40[0x60];
3240
3241 u8 reserved_at_a0[0x8];
3242 u8 table_index[0x18];
3243
3244 u8 reserved_at_c0[0x20];
3245
3246 u8 reserved_at_e0[0x13];
3247 u8 vlan_valid[0x1];
3248 u8 vlan[0xc];
3249
3250 struct mlx5_ifc_mac_address_layout_bits mac_address;
3251
3252 u8 reserved_at_140[0xc0];
3253};
3254
3255struct mlx5_ifc_set_issi_out_bits {
3256 u8 status[0x8];
3257 u8 reserved_at_8[0x18];
3258
3259 u8 syndrome[0x20];
3260
3261 u8 reserved_at_40[0x40];
3262};
3263
3264struct mlx5_ifc_set_issi_in_bits {
3265 u8 opcode[0x10];
3266 u8 reserved_at_10[0x10];
3267
3268 u8 reserved_at_20[0x10];
3269 u8 op_mod[0x10];
3270
3271 u8 reserved_at_40[0x10];
3272 u8 current_issi[0x10];
3273
3274 u8 reserved_at_60[0x20];
3275};
3276
3277struct mlx5_ifc_set_hca_cap_out_bits {
3278 u8 status[0x8];
3279 u8 reserved_at_8[0x18];
3280
3281 u8 syndrome[0x20];
3282
3283 u8 reserved_at_40[0x40];
3284};
3285
3286struct mlx5_ifc_set_hca_cap_in_bits {
3287 u8 opcode[0x10];
3288 u8 reserved_at_10[0x10];
3289
3290 u8 reserved_at_20[0x10];
3291 u8 op_mod[0x10];
3292
3293 u8 reserved_at_40[0x40];
3294
3295 union mlx5_ifc_hca_cap_union_bits capability;
3296};
3297
3298enum {
3299 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3300 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3301 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3302 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3303};
3304
3305struct mlx5_ifc_set_fte_out_bits {
3306 u8 status[0x8];
3307 u8 reserved_at_8[0x18];
3308
3309 u8 syndrome[0x20];
3310
3311 u8 reserved_at_40[0x40];
3312};
3313
3314struct mlx5_ifc_set_fte_in_bits {
3315 u8 opcode[0x10];
3316 u8 reserved_at_10[0x10];
3317
3318 u8 reserved_at_20[0x10];
3319 u8 op_mod[0x10];
3320
3321 u8 other_vport[0x1];
3322 u8 reserved_at_41[0xf];
3323 u8 vport_number[0x10];
3324
3325 u8 reserved_at_60[0x20];
3326
3327 u8 table_type[0x8];
3328 u8 reserved_at_88[0x18];
3329
3330 u8 reserved_at_a0[0x8];
3331 u8 table_id[0x18];
3332
3333 u8 reserved_at_c0[0x18];
3334 u8 modify_enable_mask[0x8];
3335
3336 u8 reserved_at_e0[0x20];
3337
3338 u8 flow_index[0x20];
3339
3340 u8 reserved_at_120[0xe0];
3341
3342 struct mlx5_ifc_flow_context_bits flow_context;
3343};
3344
3345struct mlx5_ifc_rts2rts_qp_out_bits {
3346 u8 status[0x8];
3347 u8 reserved_at_8[0x18];
3348
3349 u8 syndrome[0x20];
3350
3351 u8 reserved_at_40[0x40];
3352};
3353
3354struct mlx5_ifc_rts2rts_qp_in_bits {
3355 u8 opcode[0x10];
3356 u8 reserved_at_10[0x10];
3357
3358 u8 reserved_at_20[0x10];
3359 u8 op_mod[0x10];
3360
3361 u8 reserved_at_40[0x8];
3362 u8 qpn[0x18];
3363
3364 u8 reserved_at_60[0x20];
3365
3366 u8 opt_param_mask[0x20];
3367
3368 u8 reserved_at_a0[0x20];
3369
3370 struct mlx5_ifc_qpc_bits qpc;
3371
3372 u8 reserved_at_800[0x80];
3373};
3374
3375struct mlx5_ifc_rtr2rts_qp_out_bits {
3376 u8 status[0x8];
3377 u8 reserved_at_8[0x18];
3378
3379 u8 syndrome[0x20];
3380
3381 u8 reserved_at_40[0x40];
3382};
3383
3384struct mlx5_ifc_rtr2rts_qp_in_bits {
3385 u8 opcode[0x10];
3386 u8 reserved_at_10[0x10];
3387
3388 u8 reserved_at_20[0x10];
3389 u8 op_mod[0x10];
3390
3391 u8 reserved_at_40[0x8];
3392 u8 qpn[0x18];
3393
3394 u8 reserved_at_60[0x20];
3395
3396 u8 opt_param_mask[0x20];
3397
3398 u8 reserved_at_a0[0x20];
3399
3400 struct mlx5_ifc_qpc_bits qpc;
3401
3402 u8 reserved_at_800[0x80];
3403};
3404
3405struct mlx5_ifc_rst2init_qp_out_bits {
3406 u8 status[0x8];
3407 u8 reserved_at_8[0x18];
3408
3409 u8 syndrome[0x20];
3410
3411 u8 reserved_at_40[0x40];
3412};
3413
3414struct mlx5_ifc_rst2init_qp_in_bits {
3415 u8 opcode[0x10];
3416 u8 reserved_at_10[0x10];
3417
3418 u8 reserved_at_20[0x10];
3419 u8 op_mod[0x10];
3420
3421 u8 reserved_at_40[0x8];
3422 u8 qpn[0x18];
3423
3424 u8 reserved_at_60[0x20];
3425
3426 u8 opt_param_mask[0x20];
3427
3428 u8 reserved_at_a0[0x20];
3429
3430 struct mlx5_ifc_qpc_bits qpc;
3431
3432 u8 reserved_at_800[0x80];
3433};
3434
3435struct mlx5_ifc_query_xrq_out_bits {
3436 u8 status[0x8];
3437 u8 reserved_at_8[0x18];
3438
3439 u8 syndrome[0x20];
3440
3441 u8 reserved_at_40[0x40];
3442
3443 struct mlx5_ifc_xrqc_bits xrq_context;
3444};
3445
3446struct mlx5_ifc_query_xrq_in_bits {
3447 u8 opcode[0x10];
3448 u8 reserved_at_10[0x10];
3449
3450 u8 reserved_at_20[0x10];
3451 u8 op_mod[0x10];
3452
3453 u8 reserved_at_40[0x8];
3454 u8 xrqn[0x18];
3455
3456 u8 reserved_at_60[0x20];
3457};
3458
3459struct mlx5_ifc_query_xrc_srq_out_bits {
3460 u8 status[0x8];
3461 u8 reserved_at_8[0x18];
3462
3463 u8 syndrome[0x20];
3464
3465 u8 reserved_at_40[0x40];
3466
3467 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3468
3469 u8 reserved_at_280[0x600];
3470
3471 u8 pas[0][0x40];
3472};
3473
3474struct mlx5_ifc_query_xrc_srq_in_bits {
3475 u8 opcode[0x10];
3476 u8 reserved_at_10[0x10];
3477
3478 u8 reserved_at_20[0x10];
3479 u8 op_mod[0x10];
3480
3481 u8 reserved_at_40[0x8];
3482 u8 xrc_srqn[0x18];
3483
3484 u8 reserved_at_60[0x20];
3485};
3486
3487enum {
3488 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3489 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3490};
3491
3492struct mlx5_ifc_query_vport_state_out_bits {
3493 u8 status[0x8];
3494 u8 reserved_at_8[0x18];
3495
3496 u8 syndrome[0x20];
3497
3498 u8 reserved_at_40[0x20];
3499
3500 u8 reserved_at_60[0x18];
3501 u8 admin_state[0x4];
3502 u8 state[0x4];
3503};
3504
3505enum {
3506 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3507 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3508};
3509
3510struct mlx5_ifc_query_vport_state_in_bits {
3511 u8 opcode[0x10];
3512 u8 reserved_at_10[0x10];
3513
3514 u8 reserved_at_20[0x10];
3515 u8 op_mod[0x10];
3516
3517 u8 other_vport[0x1];
3518 u8 reserved_at_41[0xf];
3519 u8 vport_number[0x10];
3520
3521 u8 reserved_at_60[0x20];
3522};
3523
3524struct mlx5_ifc_query_vport_counter_out_bits {
3525 u8 status[0x8];
3526 u8 reserved_at_8[0x18];
3527
3528 u8 syndrome[0x20];
3529
3530 u8 reserved_at_40[0x40];
3531
3532 struct mlx5_ifc_traffic_counter_bits received_errors;
3533
3534 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3535
3536 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3537
3538 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3539
3540 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3541
3542 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3543
3544 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3545
3546 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3547
3548 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3549
3550 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3551
3552 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3553
3554 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3555
3556 u8 reserved_at_680[0xa00];
3557};
3558
3559enum {
3560 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3561};
3562
3563struct mlx5_ifc_query_vport_counter_in_bits {
3564 u8 opcode[0x10];
3565 u8 reserved_at_10[0x10];
3566
3567 u8 reserved_at_20[0x10];
3568 u8 op_mod[0x10];
3569
3570 u8 other_vport[0x1];
3571 u8 reserved_at_41[0xb];
3572 u8 port_num[0x4];
3573 u8 vport_number[0x10];
3574
3575 u8 reserved_at_60[0x60];
3576
3577 u8 clear[0x1];
3578 u8 reserved_at_c1[0x1f];
3579
3580 u8 reserved_at_e0[0x20];
3581};
3582
3583struct mlx5_ifc_query_tis_out_bits {
3584 u8 status[0x8];
3585 u8 reserved_at_8[0x18];
3586
3587 u8 syndrome[0x20];
3588
3589 u8 reserved_at_40[0x40];
3590
3591 struct mlx5_ifc_tisc_bits tis_context;
3592};
3593
3594struct mlx5_ifc_query_tis_in_bits {
3595 u8 opcode[0x10];
3596 u8 reserved_at_10[0x10];
3597
3598 u8 reserved_at_20[0x10];
3599 u8 op_mod[0x10];
3600
3601 u8 reserved_at_40[0x8];
3602 u8 tisn[0x18];
3603
3604 u8 reserved_at_60[0x20];
3605};
3606
3607struct mlx5_ifc_query_tir_out_bits {
3608 u8 status[0x8];
3609 u8 reserved_at_8[0x18];
3610
3611 u8 syndrome[0x20];
3612
3613 u8 reserved_at_40[0xc0];
3614
3615 struct mlx5_ifc_tirc_bits tir_context;
3616};
3617
3618struct mlx5_ifc_query_tir_in_bits {
3619 u8 opcode[0x10];
3620 u8 reserved_at_10[0x10];
3621
3622 u8 reserved_at_20[0x10];
3623 u8 op_mod[0x10];
3624
3625 u8 reserved_at_40[0x8];
3626 u8 tirn[0x18];
3627
3628 u8 reserved_at_60[0x20];
3629};
3630
3631struct mlx5_ifc_query_srq_out_bits {
3632 u8 status[0x8];
3633 u8 reserved_at_8[0x18];
3634
3635 u8 syndrome[0x20];
3636
3637 u8 reserved_at_40[0x40];
3638
3639 struct mlx5_ifc_srqc_bits srq_context_entry;
3640
3641 u8 reserved_at_280[0x600];
3642
3643 u8 pas[0][0x40];
3644};
3645
3646struct mlx5_ifc_query_srq_in_bits {
3647 u8 opcode[0x10];
3648 u8 reserved_at_10[0x10];
3649
3650 u8 reserved_at_20[0x10];
3651 u8 op_mod[0x10];
3652
3653 u8 reserved_at_40[0x8];
3654 u8 srqn[0x18];
3655
3656 u8 reserved_at_60[0x20];
3657};
3658
3659struct mlx5_ifc_query_sq_out_bits {
3660 u8 status[0x8];
3661 u8 reserved_at_8[0x18];
3662
3663 u8 syndrome[0x20];
3664
3665 u8 reserved_at_40[0xc0];
3666
3667 struct mlx5_ifc_sqc_bits sq_context;
3668};
3669
3670struct mlx5_ifc_query_sq_in_bits {
3671 u8 opcode[0x10];
3672 u8 reserved_at_10[0x10];
3673
3674 u8 reserved_at_20[0x10];
3675 u8 op_mod[0x10];
3676
3677 u8 reserved_at_40[0x8];
3678 u8 sqn[0x18];
3679
3680 u8 reserved_at_60[0x20];
3681};
3682
3683struct mlx5_ifc_query_special_contexts_out_bits {
3684 u8 status[0x8];
3685 u8 reserved_at_8[0x18];
3686
3687 u8 syndrome[0x20];
3688
3689 u8 dump_fill_mkey[0x20];
3690
3691 u8 resd_lkey[0x20];
3692
3693 u8 null_mkey[0x20];
3694
3695 u8 reserved_at_a0[0x60];
3696};
3697
3698struct mlx5_ifc_query_special_contexts_in_bits {
3699 u8 opcode[0x10];
3700 u8 reserved_at_10[0x10];
3701
3702 u8 reserved_at_20[0x10];
3703 u8 op_mod[0x10];
3704
3705 u8 reserved_at_40[0x40];
3706};
3707
3708struct mlx5_ifc_query_scheduling_element_out_bits {
3709 u8 opcode[0x10];
3710 u8 reserved_at_10[0x10];
3711
3712 u8 reserved_at_20[0x10];
3713 u8 op_mod[0x10];
3714
3715 u8 reserved_at_40[0xc0];
3716
3717 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3718
3719 u8 reserved_at_300[0x100];
3720};
3721
3722enum {
3723 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3724};
3725
3726struct mlx5_ifc_query_scheduling_element_in_bits {
3727 u8 opcode[0x10];
3728 u8 reserved_at_10[0x10];
3729
3730 u8 reserved_at_20[0x10];
3731 u8 op_mod[0x10];
3732
3733 u8 scheduling_hierarchy[0x8];
3734 u8 reserved_at_48[0x18];
3735
3736 u8 scheduling_element_id[0x20];
3737
3738 u8 reserved_at_80[0x180];
3739};
3740
3741struct mlx5_ifc_query_rqt_out_bits {
3742 u8 status[0x8];
3743 u8 reserved_at_8[0x18];
3744
3745 u8 syndrome[0x20];
3746
3747 u8 reserved_at_40[0xc0];
3748
3749 struct mlx5_ifc_rqtc_bits rqt_context;
3750};
3751
3752struct mlx5_ifc_query_rqt_in_bits {
3753 u8 opcode[0x10];
3754 u8 reserved_at_10[0x10];
3755
3756 u8 reserved_at_20[0x10];
3757 u8 op_mod[0x10];
3758
3759 u8 reserved_at_40[0x8];
3760 u8 rqtn[0x18];
3761
3762 u8 reserved_at_60[0x20];
3763};
3764
3765struct mlx5_ifc_query_rq_out_bits {
3766 u8 status[0x8];
3767 u8 reserved_at_8[0x18];
3768
3769 u8 syndrome[0x20];
3770
3771 u8 reserved_at_40[0xc0];
3772
3773 struct mlx5_ifc_rqc_bits rq_context;
3774};
3775
3776struct mlx5_ifc_query_rq_in_bits {
3777 u8 opcode[0x10];
3778 u8 reserved_at_10[0x10];
3779
3780 u8 reserved_at_20[0x10];
3781 u8 op_mod[0x10];
3782
3783 u8 reserved_at_40[0x8];
3784 u8 rqn[0x18];
3785
3786 u8 reserved_at_60[0x20];
3787};
3788
3789struct mlx5_ifc_query_roce_address_out_bits {
3790 u8 status[0x8];
3791 u8 reserved_at_8[0x18];
3792
3793 u8 syndrome[0x20];
3794
3795 u8 reserved_at_40[0x40];
3796
3797 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3798};
3799
3800struct mlx5_ifc_query_roce_address_in_bits {
3801 u8 opcode[0x10];
3802 u8 reserved_at_10[0x10];
3803
3804 u8 reserved_at_20[0x10];
3805 u8 op_mod[0x10];
3806
3807 u8 roce_address_index[0x10];
3808 u8 reserved_at_50[0x10];
3809
3810 u8 reserved_at_60[0x20];
3811};
3812
3813struct mlx5_ifc_query_rmp_out_bits {
3814 u8 status[0x8];
3815 u8 reserved_at_8[0x18];
3816
3817 u8 syndrome[0x20];
3818
3819 u8 reserved_at_40[0xc0];
3820
3821 struct mlx5_ifc_rmpc_bits rmp_context;
3822};
3823
3824struct mlx5_ifc_query_rmp_in_bits {
3825 u8 opcode[0x10];
3826 u8 reserved_at_10[0x10];
3827
3828 u8 reserved_at_20[0x10];
3829 u8 op_mod[0x10];
3830
3831 u8 reserved_at_40[0x8];
3832 u8 rmpn[0x18];
3833
3834 u8 reserved_at_60[0x20];
3835};
3836
3837struct mlx5_ifc_query_qp_out_bits {
3838 u8 status[0x8];
3839 u8 reserved_at_8[0x18];
3840
3841 u8 syndrome[0x20];
3842
3843 u8 reserved_at_40[0x40];
3844
3845 u8 opt_param_mask[0x20];
3846
3847 u8 reserved_at_a0[0x20];
3848
3849 struct mlx5_ifc_qpc_bits qpc;
3850
3851 u8 reserved_at_800[0x80];
3852
3853 u8 pas[0][0x40];
3854};
3855
3856struct mlx5_ifc_query_qp_in_bits {
3857 u8 opcode[0x10];
3858 u8 reserved_at_10[0x10];
3859
3860 u8 reserved_at_20[0x10];
3861 u8 op_mod[0x10];
3862
3863 u8 reserved_at_40[0x8];
3864 u8 qpn[0x18];
3865
3866 u8 reserved_at_60[0x20];
3867};
3868
3869struct mlx5_ifc_query_q_counter_out_bits {
3870 u8 status[0x8];
3871 u8 reserved_at_8[0x18];
3872
3873 u8 syndrome[0x20];
3874
3875 u8 reserved_at_40[0x40];
3876
3877 u8 rx_write_requests[0x20];
3878
3879 u8 reserved_at_a0[0x20];
3880
3881 u8 rx_read_requests[0x20];
3882
3883 u8 reserved_at_e0[0x20];
3884
3885 u8 rx_atomic_requests[0x20];
3886
3887 u8 reserved_at_120[0x20];
3888
3889 u8 rx_dct_connect[0x20];
3890
3891 u8 reserved_at_160[0x20];
3892
3893 u8 out_of_buffer[0x20];
3894
3895 u8 reserved_at_1a0[0x20];
3896
3897 u8 out_of_sequence[0x20];
3898
3899 u8 reserved_at_1e0[0x20];
3900
3901 u8 duplicate_request[0x20];
3902
3903 u8 reserved_at_220[0x20];
3904
3905 u8 rnr_nak_retry_err[0x20];
3906
3907 u8 reserved_at_260[0x20];
3908
3909 u8 packet_seq_err[0x20];
3910
3911 u8 reserved_at_2a0[0x20];
3912
3913 u8 implied_nak_seq_err[0x20];
3914
3915 u8 reserved_at_2e0[0x20];
3916
3917 u8 local_ack_timeout_err[0x20];
3918
3919 u8 reserved_at_320[0x4e0];
3920};
3921
3922struct mlx5_ifc_query_q_counter_in_bits {
3923 u8 opcode[0x10];
3924 u8 reserved_at_10[0x10];
3925
3926 u8 reserved_at_20[0x10];
3927 u8 op_mod[0x10];
3928
3929 u8 reserved_at_40[0x80];
3930
3931 u8 clear[0x1];
3932 u8 reserved_at_c1[0x1f];
3933
3934 u8 reserved_at_e0[0x18];
3935 u8 counter_set_id[0x8];
3936};
3937
3938struct mlx5_ifc_query_pages_out_bits {
3939 u8 status[0x8];
3940 u8 reserved_at_8[0x18];
3941
3942 u8 syndrome[0x20];
3943
3944 u8 reserved_at_40[0x10];
3945 u8 function_id[0x10];
3946
3947 u8 num_pages[0x20];
3948};
3949
3950enum {
3951 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3952 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3953 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3954};
3955
3956struct mlx5_ifc_query_pages_in_bits {
3957 u8 opcode[0x10];
3958 u8 reserved_at_10[0x10];
3959
3960 u8 reserved_at_20[0x10];
3961 u8 op_mod[0x10];
3962
3963 u8 reserved_at_40[0x10];
3964 u8 function_id[0x10];
3965
3966 u8 reserved_at_60[0x20];
3967};
3968
3969struct mlx5_ifc_query_nic_vport_context_out_bits {
3970 u8 status[0x8];
3971 u8 reserved_at_8[0x18];
3972
3973 u8 syndrome[0x20];
3974
3975 u8 reserved_at_40[0x40];
3976
3977 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3978};
3979
3980struct mlx5_ifc_query_nic_vport_context_in_bits {
3981 u8 opcode[0x10];
3982 u8 reserved_at_10[0x10];
3983
3984 u8 reserved_at_20[0x10];
3985 u8 op_mod[0x10];
3986
3987 u8 other_vport[0x1];
3988 u8 reserved_at_41[0xf];
3989 u8 vport_number[0x10];
3990
3991 u8 reserved_at_60[0x5];
3992 u8 allowed_list_type[0x3];
3993 u8 reserved_at_68[0x18];
3994};
3995
3996struct mlx5_ifc_query_mkey_out_bits {
3997 u8 status[0x8];
3998 u8 reserved_at_8[0x18];
3999
4000 u8 syndrome[0x20];
4001
4002 u8 reserved_at_40[0x40];
4003
4004 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4005
4006 u8 reserved_at_280[0x600];
4007
4008 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4009
4010 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4011};
4012
4013struct mlx5_ifc_query_mkey_in_bits {
4014 u8 opcode[0x10];
4015 u8 reserved_at_10[0x10];
4016
4017 u8 reserved_at_20[0x10];
4018 u8 op_mod[0x10];
4019
4020 u8 reserved_at_40[0x8];
4021 u8 mkey_index[0x18];
4022
4023 u8 pg_access[0x1];
4024 u8 reserved_at_61[0x1f];
4025};
4026
4027struct mlx5_ifc_query_mad_demux_out_bits {
4028 u8 status[0x8];
4029 u8 reserved_at_8[0x18];
4030
4031 u8 syndrome[0x20];
4032
4033 u8 reserved_at_40[0x40];
4034
4035 u8 mad_dumux_parameters_block[0x20];
4036};
4037
4038struct mlx5_ifc_query_mad_demux_in_bits {
4039 u8 opcode[0x10];
4040 u8 reserved_at_10[0x10];
4041
4042 u8 reserved_at_20[0x10];
4043 u8 op_mod[0x10];
4044
4045 u8 reserved_at_40[0x40];
4046};
4047
4048struct mlx5_ifc_query_l2_table_entry_out_bits {
4049 u8 status[0x8];
4050 u8 reserved_at_8[0x18];
4051
4052 u8 syndrome[0x20];
4053
4054 u8 reserved_at_40[0xa0];
4055
4056 u8 reserved_at_e0[0x13];
4057 u8 vlan_valid[0x1];
4058 u8 vlan[0xc];
4059
4060 struct mlx5_ifc_mac_address_layout_bits mac_address;
4061
4062 u8 reserved_at_140[0xc0];
4063};
4064
4065struct mlx5_ifc_query_l2_table_entry_in_bits {
4066 u8 opcode[0x10];
4067 u8 reserved_at_10[0x10];
4068
4069 u8 reserved_at_20[0x10];
4070 u8 op_mod[0x10];
4071
4072 u8 reserved_at_40[0x60];
4073
4074 u8 reserved_at_a0[0x8];
4075 u8 table_index[0x18];
4076
4077 u8 reserved_at_c0[0x140];
4078};
4079
4080struct mlx5_ifc_query_issi_out_bits {
4081 u8 status[0x8];
4082 u8 reserved_at_8[0x18];
4083
4084 u8 syndrome[0x20];
4085
4086 u8 reserved_at_40[0x10];
4087 u8 current_issi[0x10];
4088
4089 u8 reserved_at_60[0xa0];
4090
4091 u8 reserved_at_100[76][0x8];
4092 u8 supported_issi_dw0[0x20];
4093};
4094
4095struct mlx5_ifc_query_issi_in_bits {
4096 u8 opcode[0x10];
4097 u8 reserved_at_10[0x10];
4098
4099 u8 reserved_at_20[0x10];
4100 u8 op_mod[0x10];
4101
4102 u8 reserved_at_40[0x40];
4103};
4104
4105struct mlx5_ifc_set_driver_version_out_bits {
4106 u8 status[0x8];
4107 u8 reserved_0[0x18];
4108
4109 u8 syndrome[0x20];
4110 u8 reserved_1[0x40];
4111};
4112
4113struct mlx5_ifc_set_driver_version_in_bits {
4114 u8 opcode[0x10];
4115 u8 reserved_0[0x10];
4116
4117 u8 reserved_1[0x10];
4118 u8 op_mod[0x10];
4119
4120 u8 reserved_2[0x40];
4121 u8 driver_version[64][0x8];
4122};
4123
4124struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4125 u8 status[0x8];
4126 u8 reserved_at_8[0x18];
4127
4128 u8 syndrome[0x20];
4129
4130 u8 reserved_at_40[0x40];
4131
4132 struct mlx5_ifc_pkey_bits pkey[0];
4133};
4134
4135struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4136 u8 opcode[0x10];
4137 u8 reserved_at_10[0x10];
4138
4139 u8 reserved_at_20[0x10];
4140 u8 op_mod[0x10];
4141
4142 u8 other_vport[0x1];
4143 u8 reserved_at_41[0xb];
4144 u8 port_num[0x4];
4145 u8 vport_number[0x10];
4146
4147 u8 reserved_at_60[0x10];
4148 u8 pkey_index[0x10];
4149};
4150
4151enum {
4152 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4153 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4154 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4155};
4156
4157struct mlx5_ifc_query_hca_vport_gid_out_bits {
4158 u8 status[0x8];
4159 u8 reserved_at_8[0x18];
4160
4161 u8 syndrome[0x20];
4162
4163 u8 reserved_at_40[0x20];
4164
4165 u8 gids_num[0x10];
4166 u8 reserved_at_70[0x10];
4167
4168 struct mlx5_ifc_array128_auto_bits gid[0];
4169};
4170
4171struct mlx5_ifc_query_hca_vport_gid_in_bits {
4172 u8 opcode[0x10];
4173 u8 reserved_at_10[0x10];
4174
4175 u8 reserved_at_20[0x10];
4176 u8 op_mod[0x10];
4177
4178 u8 other_vport[0x1];
4179 u8 reserved_at_41[0xb];
4180 u8 port_num[0x4];
4181 u8 vport_number[0x10];
4182
4183 u8 reserved_at_60[0x10];
4184 u8 gid_index[0x10];
4185};
4186
4187struct mlx5_ifc_query_hca_vport_context_out_bits {
4188 u8 status[0x8];
4189 u8 reserved_at_8[0x18];
4190
4191 u8 syndrome[0x20];
4192
4193 u8 reserved_at_40[0x40];
4194
4195 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4196};
4197
4198struct mlx5_ifc_query_hca_vport_context_in_bits {
4199 u8 opcode[0x10];
4200 u8 reserved_at_10[0x10];
4201
4202 u8 reserved_at_20[0x10];
4203 u8 op_mod[0x10];
4204
4205 u8 other_vport[0x1];
4206 u8 reserved_at_41[0xb];
4207 u8 port_num[0x4];
4208 u8 vport_number[0x10];
4209
4210 u8 reserved_at_60[0x20];
4211};
4212
4213struct mlx5_ifc_query_hca_cap_out_bits {
4214 u8 status[0x8];
4215 u8 reserved_at_8[0x18];
4216
4217 u8 syndrome[0x20];
4218
4219 u8 reserved_at_40[0x40];
4220
4221 union mlx5_ifc_hca_cap_union_bits capability;
4222};
4223
4224struct mlx5_ifc_query_hca_cap_in_bits {
4225 u8 opcode[0x10];
4226 u8 reserved_at_10[0x10];
4227
4228 u8 reserved_at_20[0x10];
4229 u8 op_mod[0x10];
4230
4231 u8 reserved_at_40[0x40];
4232};
4233
4234struct mlx5_ifc_query_flow_table_out_bits {
4235 u8 status[0x8];
4236 u8 reserved_at_8[0x18];
4237
4238 u8 syndrome[0x20];
4239
4240 u8 reserved_at_40[0x80];
4241
4242 u8 reserved_at_c0[0x8];
4243 u8 level[0x8];
4244 u8 reserved_at_d0[0x8];
4245 u8 log_size[0x8];
4246
4247 u8 reserved_at_e0[0x120];
4248};
4249
4250struct mlx5_ifc_query_flow_table_in_bits {
4251 u8 opcode[0x10];
4252 u8 reserved_at_10[0x10];
4253
4254 u8 reserved_at_20[0x10];
4255 u8 op_mod[0x10];
4256
4257 u8 reserved_at_40[0x40];
4258
4259 u8 table_type[0x8];
4260 u8 reserved_at_88[0x18];
4261
4262 u8 reserved_at_a0[0x8];
4263 u8 table_id[0x18];
4264
4265 u8 reserved_at_c0[0x140];
4266};
4267
4268struct mlx5_ifc_query_fte_out_bits {
4269 u8 status[0x8];
4270 u8 reserved_at_8[0x18];
4271
4272 u8 syndrome[0x20];
4273
4274 u8 reserved_at_40[0x1c0];
4275
4276 struct mlx5_ifc_flow_context_bits flow_context;
4277};
4278
4279struct mlx5_ifc_query_fte_in_bits {
4280 u8 opcode[0x10];
4281 u8 reserved_at_10[0x10];
4282
4283 u8 reserved_at_20[0x10];
4284 u8 op_mod[0x10];
4285
4286 u8 reserved_at_40[0x40];
4287
4288 u8 table_type[0x8];
4289 u8 reserved_at_88[0x18];
4290
4291 u8 reserved_at_a0[0x8];
4292 u8 table_id[0x18];
4293
4294 u8 reserved_at_c0[0x40];
4295
4296 u8 flow_index[0x20];
4297
4298 u8 reserved_at_120[0xe0];
4299};
4300
4301enum {
4302 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4303 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4304 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4305};
4306
4307struct mlx5_ifc_query_flow_group_out_bits {
4308 u8 status[0x8];
4309 u8 reserved_at_8[0x18];
4310
4311 u8 syndrome[0x20];
4312
4313 u8 reserved_at_40[0xa0];
4314
4315 u8 start_flow_index[0x20];
4316
4317 u8 reserved_at_100[0x20];
4318
4319 u8 end_flow_index[0x20];
4320
4321 u8 reserved_at_140[0xa0];
4322
4323 u8 reserved_at_1e0[0x18];
4324 u8 match_criteria_enable[0x8];
4325
4326 struct mlx5_ifc_fte_match_param_bits match_criteria;
4327
4328 u8 reserved_at_1200[0xe00];
4329};
4330
4331struct mlx5_ifc_query_flow_group_in_bits {
4332 u8 opcode[0x10];
4333 u8 reserved_at_10[0x10];
4334
4335 u8 reserved_at_20[0x10];
4336 u8 op_mod[0x10];
4337
4338 u8 reserved_at_40[0x40];
4339
4340 u8 table_type[0x8];
4341 u8 reserved_at_88[0x18];
4342
4343 u8 reserved_at_a0[0x8];
4344 u8 table_id[0x18];
4345
4346 u8 group_id[0x20];
4347
4348 u8 reserved_at_e0[0x120];
4349};
4350
4351struct mlx5_ifc_query_flow_counter_out_bits {
4352 u8 status[0x8];
4353 u8 reserved_at_8[0x18];
4354
4355 u8 syndrome[0x20];
4356
4357 u8 reserved_at_40[0x40];
4358
4359 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4360};
4361
4362struct mlx5_ifc_query_flow_counter_in_bits {
4363 u8 opcode[0x10];
4364 u8 reserved_at_10[0x10];
4365
4366 u8 reserved_at_20[0x10];
4367 u8 op_mod[0x10];
4368
4369 u8 reserved_at_40[0x80];
4370
4371 u8 clear[0x1];
4372 u8 reserved_at_c1[0xf];
4373 u8 num_of_counters[0x10];
4374
4375 u8 reserved_at_e0[0x10];
4376 u8 flow_counter_id[0x10];
4377};
4378
4379struct mlx5_ifc_query_esw_vport_context_out_bits {
4380 u8 status[0x8];
4381 u8 reserved_at_8[0x18];
4382
4383 u8 syndrome[0x20];
4384
4385 u8 reserved_at_40[0x40];
4386
4387 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4388};
4389
4390struct mlx5_ifc_query_esw_vport_context_in_bits {
4391 u8 opcode[0x10];
4392 u8 reserved_at_10[0x10];
4393
4394 u8 reserved_at_20[0x10];
4395 u8 op_mod[0x10];
4396
4397 u8 other_vport[0x1];
4398 u8 reserved_at_41[0xf];
4399 u8 vport_number[0x10];
4400
4401 u8 reserved_at_60[0x20];
4402};
4403
4404struct mlx5_ifc_modify_esw_vport_context_out_bits {
4405 u8 status[0x8];
4406 u8 reserved_at_8[0x18];
4407
4408 u8 syndrome[0x20];
4409
4410 u8 reserved_at_40[0x40];
4411};
4412
4413struct mlx5_ifc_esw_vport_context_fields_select_bits {
4414 u8 reserved_at_0[0x1c];
4415 u8 vport_cvlan_insert[0x1];
4416 u8 vport_svlan_insert[0x1];
4417 u8 vport_cvlan_strip[0x1];
4418 u8 vport_svlan_strip[0x1];
4419};
4420
4421struct mlx5_ifc_modify_esw_vport_context_in_bits {
4422 u8 opcode[0x10];
4423 u8 reserved_at_10[0x10];
4424
4425 u8 reserved_at_20[0x10];
4426 u8 op_mod[0x10];
4427
4428 u8 other_vport[0x1];
4429 u8 reserved_at_41[0xf];
4430 u8 vport_number[0x10];
4431
4432 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4433
4434 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4435};
4436
4437struct mlx5_ifc_query_eq_out_bits {
4438 u8 status[0x8];
4439 u8 reserved_at_8[0x18];
4440
4441 u8 syndrome[0x20];
4442
4443 u8 reserved_at_40[0x40];
4444
4445 struct mlx5_ifc_eqc_bits eq_context_entry;
4446
4447 u8 reserved_at_280[0x40];
4448
4449 u8 event_bitmask[0x40];
4450
4451 u8 reserved_at_300[0x580];
4452
4453 u8 pas[0][0x40];
4454};
4455
4456struct mlx5_ifc_query_eq_in_bits {
4457 u8 opcode[0x10];
4458 u8 reserved_at_10[0x10];
4459
4460 u8 reserved_at_20[0x10];
4461 u8 op_mod[0x10];
4462
4463 u8 reserved_at_40[0x18];
4464 u8 eq_number[0x8];
4465
4466 u8 reserved_at_60[0x20];
4467};
4468
4469struct mlx5_ifc_encap_header_in_bits {
4470 u8 reserved_at_0[0x5];
4471 u8 header_type[0x3];
4472 u8 reserved_at_8[0xe];
4473 u8 encap_header_size[0xa];
4474
4475 u8 reserved_at_20[0x10];
4476 u8 encap_header[2][0x8];
4477
4478 u8 more_encap_header[0][0x8];
4479};
4480
4481struct mlx5_ifc_query_encap_header_out_bits {
4482 u8 status[0x8];
4483 u8 reserved_at_8[0x18];
4484
4485 u8 syndrome[0x20];
4486
4487 u8 reserved_at_40[0xa0];
4488
4489 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4490};
4491
4492struct mlx5_ifc_query_encap_header_in_bits {
4493 u8 opcode[0x10];
4494 u8 reserved_at_10[0x10];
4495
4496 u8 reserved_at_20[0x10];
4497 u8 op_mod[0x10];
4498
4499 u8 encap_id[0x20];
4500
4501 u8 reserved_at_60[0xa0];
4502};
4503
4504struct mlx5_ifc_alloc_encap_header_out_bits {
4505 u8 status[0x8];
4506 u8 reserved_at_8[0x18];
4507
4508 u8 syndrome[0x20];
4509
4510 u8 encap_id[0x20];
4511
4512 u8 reserved_at_60[0x20];
4513};
4514
4515struct mlx5_ifc_alloc_encap_header_in_bits {
4516 u8 opcode[0x10];
4517 u8 reserved_at_10[0x10];
4518
4519 u8 reserved_at_20[0x10];
4520 u8 op_mod[0x10];
4521
4522 u8 reserved_at_40[0xa0];
4523
4524 struct mlx5_ifc_encap_header_in_bits encap_header;
4525};
4526
4527struct mlx5_ifc_dealloc_encap_header_out_bits {
4528 u8 status[0x8];
4529 u8 reserved_at_8[0x18];
4530
4531 u8 syndrome[0x20];
4532
4533 u8 reserved_at_40[0x40];
4534};
4535
4536struct mlx5_ifc_dealloc_encap_header_in_bits {
4537 u8 opcode[0x10];
4538 u8 reserved_at_10[0x10];
4539
4540 u8 reserved_20[0x10];
4541 u8 op_mod[0x10];
4542
4543 u8 encap_id[0x20];
4544
4545 u8 reserved_60[0x20];
4546};
4547
4548struct mlx5_ifc_set_action_in_bits {
4549 u8 action_type[0x4];
4550 u8 field[0xc];
4551 u8 reserved_at_10[0x3];
4552 u8 offset[0x5];
4553 u8 reserved_at_18[0x3];
4554 u8 length[0x5];
4555
4556 u8 data[0x20];
4557};
4558
4559struct mlx5_ifc_add_action_in_bits {
4560 u8 action_type[0x4];
4561 u8 field[0xc];
4562 u8 reserved_at_10[0x10];
4563
4564 u8 data[0x20];
4565};
4566
4567union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4568 struct mlx5_ifc_set_action_in_bits set_action_in;
4569 struct mlx5_ifc_add_action_in_bits add_action_in;
4570 u8 reserved_at_0[0x40];
4571};
4572
4573enum {
4574 MLX5_ACTION_TYPE_SET = 0x1,
4575 MLX5_ACTION_TYPE_ADD = 0x2,
4576};
4577
4578enum {
4579 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4580 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4581 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4582 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4583 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4584 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4585 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4586 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4587 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4588 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4589 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4590 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4591 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4592 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4593 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4594 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4595 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4596 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4597 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4598 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4599 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4600 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4601};
4602
4603struct mlx5_ifc_alloc_modify_header_context_out_bits {
4604 u8 status[0x8];
4605 u8 reserved_at_8[0x18];
4606
4607 u8 syndrome[0x20];
4608
4609 u8 modify_header_id[0x20];
4610
4611 u8 reserved_at_60[0x20];
4612};
4613
4614struct mlx5_ifc_alloc_modify_header_context_in_bits {
4615 u8 opcode[0x10];
4616 u8 reserved_at_10[0x10];
4617
4618 u8 reserved_at_20[0x10];
4619 u8 op_mod[0x10];
4620
4621 u8 reserved_at_40[0x20];
4622
4623 u8 table_type[0x8];
4624 u8 reserved_at_68[0x10];
4625 u8 num_of_actions[0x8];
4626
4627 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4628};
4629
4630struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4631 u8 status[0x8];
4632 u8 reserved_at_8[0x18];
4633
4634 u8 syndrome[0x20];
4635
4636 u8 reserved_at_40[0x40];
4637};
4638
4639struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4640 u8 opcode[0x10];
4641 u8 reserved_at_10[0x10];
4642
4643 u8 reserved_at_20[0x10];
4644 u8 op_mod[0x10];
4645
4646 u8 modify_header_id[0x20];
4647
4648 u8 reserved_at_60[0x20];
4649};
4650
4651struct mlx5_ifc_query_dct_out_bits {
4652 u8 status[0x8];
4653 u8 reserved_at_8[0x18];
4654
4655 u8 syndrome[0x20];
4656
4657 u8 reserved_at_40[0x40];
4658
4659 struct mlx5_ifc_dctc_bits dct_context_entry;
4660
4661 u8 reserved_at_280[0x180];
4662};
4663
4664struct mlx5_ifc_query_dct_in_bits {
4665 u8 opcode[0x10];
4666 u8 reserved_at_10[0x10];
4667
4668 u8 reserved_at_20[0x10];
4669 u8 op_mod[0x10];
4670
4671 u8 reserved_at_40[0x8];
4672 u8 dctn[0x18];
4673
4674 u8 reserved_at_60[0x20];
4675};
4676
4677struct mlx5_ifc_query_cq_out_bits {
4678 u8 status[0x8];
4679 u8 reserved_at_8[0x18];
4680
4681 u8 syndrome[0x20];
4682
4683 u8 reserved_at_40[0x40];
4684
4685 struct mlx5_ifc_cqc_bits cq_context;
4686
4687 u8 reserved_at_280[0x600];
4688
4689 u8 pas[0][0x40];
4690};
4691
4692struct mlx5_ifc_query_cq_in_bits {
4693 u8 opcode[0x10];
4694 u8 reserved_at_10[0x10];
4695
4696 u8 reserved_at_20[0x10];
4697 u8 op_mod[0x10];
4698
4699 u8 reserved_at_40[0x8];
4700 u8 cqn[0x18];
4701
4702 u8 reserved_at_60[0x20];
4703};
4704
4705struct mlx5_ifc_query_cong_status_out_bits {
4706 u8 status[0x8];
4707 u8 reserved_at_8[0x18];
4708
4709 u8 syndrome[0x20];
4710
4711 u8 reserved_at_40[0x20];
4712
4713 u8 enable[0x1];
4714 u8 tag_enable[0x1];
4715 u8 reserved_at_62[0x1e];
4716};
4717
4718struct mlx5_ifc_query_cong_status_in_bits {
4719 u8 opcode[0x10];
4720 u8 reserved_at_10[0x10];
4721
4722 u8 reserved_at_20[0x10];
4723 u8 op_mod[0x10];
4724
4725 u8 reserved_at_40[0x18];
4726 u8 priority[0x4];
4727 u8 cong_protocol[0x4];
4728
4729 u8 reserved_at_60[0x20];
4730};
4731
4732struct mlx5_ifc_query_cong_statistics_out_bits {
4733 u8 status[0x8];
4734 u8 reserved_at_8[0x18];
4735
4736 u8 syndrome[0x20];
4737
4738 u8 reserved_at_40[0x40];
4739
4740 u8 rp_cur_flows[0x20];
4741
4742 u8 sum_flows[0x20];
4743
4744 u8 rp_cnp_ignored_high[0x20];
4745
4746 u8 rp_cnp_ignored_low[0x20];
4747
4748 u8 rp_cnp_handled_high[0x20];
4749
4750 u8 rp_cnp_handled_low[0x20];
4751
4752 u8 reserved_at_140[0x100];
4753
4754 u8 time_stamp_high[0x20];
4755
4756 u8 time_stamp_low[0x20];
4757
4758 u8 accumulators_period[0x20];
4759
4760 u8 np_ecn_marked_roce_packets_high[0x20];
4761
4762 u8 np_ecn_marked_roce_packets_low[0x20];
4763
4764 u8 np_cnp_sent_high[0x20];
4765
4766 u8 np_cnp_sent_low[0x20];
4767
4768 u8 reserved_at_320[0x560];
4769};
4770
4771struct mlx5_ifc_query_cong_statistics_in_bits {
4772 u8 opcode[0x10];
4773 u8 reserved_at_10[0x10];
4774
4775 u8 reserved_at_20[0x10];
4776 u8 op_mod[0x10];
4777
4778 u8 clear[0x1];
4779 u8 reserved_at_41[0x1f];
4780
4781 u8 reserved_at_60[0x20];
4782};
4783
4784struct mlx5_ifc_query_cong_params_out_bits {
4785 u8 status[0x8];
4786 u8 reserved_at_8[0x18];
4787
4788 u8 syndrome[0x20];
4789
4790 u8 reserved_at_40[0x40];
4791
4792 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4793};
4794
4795struct mlx5_ifc_query_cong_params_in_bits {
4796 u8 opcode[0x10];
4797 u8 reserved_at_10[0x10];
4798
4799 u8 reserved_at_20[0x10];
4800 u8 op_mod[0x10];
4801
4802 u8 reserved_at_40[0x1c];
4803 u8 cong_protocol[0x4];
4804
4805 u8 reserved_at_60[0x20];
4806};
4807
4808struct mlx5_ifc_query_adapter_out_bits {
4809 u8 status[0x8];
4810 u8 reserved_at_8[0x18];
4811
4812 u8 syndrome[0x20];
4813
4814 u8 reserved_at_40[0x40];
4815
4816 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4817};
4818
4819struct mlx5_ifc_query_adapter_in_bits {
4820 u8 opcode[0x10];
4821 u8 reserved_at_10[0x10];
4822
4823 u8 reserved_at_20[0x10];
4824 u8 op_mod[0x10];
4825
4826 u8 reserved_at_40[0x40];
4827};
4828
4829struct mlx5_ifc_qp_2rst_out_bits {
4830 u8 status[0x8];
4831 u8 reserved_at_8[0x18];
4832
4833 u8 syndrome[0x20];
4834
4835 u8 reserved_at_40[0x40];
4836};
4837
4838struct mlx5_ifc_qp_2rst_in_bits {
4839 u8 opcode[0x10];
4840 u8 reserved_at_10[0x10];
4841
4842 u8 reserved_at_20[0x10];
4843 u8 op_mod[0x10];
4844
4845 u8 reserved_at_40[0x8];
4846 u8 qpn[0x18];
4847
4848 u8 reserved_at_60[0x20];
4849};
4850
4851struct mlx5_ifc_qp_2err_out_bits {
4852 u8 status[0x8];
4853 u8 reserved_at_8[0x18];
4854
4855 u8 syndrome[0x20];
4856
4857 u8 reserved_at_40[0x40];
4858};
4859
4860struct mlx5_ifc_qp_2err_in_bits {
4861 u8 opcode[0x10];
4862 u8 reserved_at_10[0x10];
4863
4864 u8 reserved_at_20[0x10];
4865 u8 op_mod[0x10];
4866
4867 u8 reserved_at_40[0x8];
4868 u8 qpn[0x18];
4869
4870 u8 reserved_at_60[0x20];
4871};
4872
4873struct mlx5_ifc_page_fault_resume_out_bits {
4874 u8 status[0x8];
4875 u8 reserved_at_8[0x18];
4876
4877 u8 syndrome[0x20];
4878
4879 u8 reserved_at_40[0x40];
4880};
4881
4882struct mlx5_ifc_page_fault_resume_in_bits {
4883 u8 opcode[0x10];
4884 u8 reserved_at_10[0x10];
4885
4886 u8 reserved_at_20[0x10];
4887 u8 op_mod[0x10];
4888
4889 u8 error[0x1];
4890 u8 reserved_at_41[0x4];
4891 u8 page_fault_type[0x3];
4892 u8 wq_number[0x18];
4893
4894 u8 reserved_at_60[0x8];
4895 u8 token[0x18];
4896};
4897
4898struct mlx5_ifc_nop_out_bits {
4899 u8 status[0x8];
4900 u8 reserved_at_8[0x18];
4901
4902 u8 syndrome[0x20];
4903
4904 u8 reserved_at_40[0x40];
4905};
4906
4907struct mlx5_ifc_nop_in_bits {
4908 u8 opcode[0x10];
4909 u8 reserved_at_10[0x10];
4910
4911 u8 reserved_at_20[0x10];
4912 u8 op_mod[0x10];
4913
4914 u8 reserved_at_40[0x40];
4915};
4916
4917struct mlx5_ifc_modify_vport_state_out_bits {
4918 u8 status[0x8];
4919 u8 reserved_at_8[0x18];
4920
4921 u8 syndrome[0x20];
4922
4923 u8 reserved_at_40[0x40];
4924};
4925
4926struct mlx5_ifc_modify_vport_state_in_bits {
4927 u8 opcode[0x10];
4928 u8 reserved_at_10[0x10];
4929
4930 u8 reserved_at_20[0x10];
4931 u8 op_mod[0x10];
4932
4933 u8 other_vport[0x1];
4934 u8 reserved_at_41[0xf];
4935 u8 vport_number[0x10];
4936
4937 u8 reserved_at_60[0x18];
4938 u8 admin_state[0x4];
4939 u8 reserved_at_7c[0x4];
4940};
4941
4942struct mlx5_ifc_modify_tis_out_bits {
4943 u8 status[0x8];
4944 u8 reserved_at_8[0x18];
4945
4946 u8 syndrome[0x20];
4947
4948 u8 reserved_at_40[0x40];
4949};
4950
4951struct mlx5_ifc_modify_tis_bitmask_bits {
4952 u8 reserved_at_0[0x20];
4953
4954 u8 reserved_at_20[0x1d];
4955 u8 lag_tx_port_affinity[0x1];
4956 u8 strict_lag_tx_port_affinity[0x1];
4957 u8 prio[0x1];
4958};
4959
4960struct mlx5_ifc_modify_tis_in_bits {
4961 u8 opcode[0x10];
4962 u8 reserved_at_10[0x10];
4963
4964 u8 reserved_at_20[0x10];
4965 u8 op_mod[0x10];
4966
4967 u8 reserved_at_40[0x8];
4968 u8 tisn[0x18];
4969
4970 u8 reserved_at_60[0x20];
4971
4972 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4973
4974 u8 reserved_at_c0[0x40];
4975
4976 struct mlx5_ifc_tisc_bits ctx;
4977};
4978
4979struct mlx5_ifc_modify_tir_bitmask_bits {
4980 u8 reserved_at_0[0x20];
4981
4982 u8 reserved_at_20[0x1b];
4983 u8 self_lb_en[0x1];
4984 u8 reserved_at_3c[0x1];
4985 u8 hash[0x1];
4986 u8 reserved_at_3e[0x1];
4987 u8 lro[0x1];
4988};
4989
4990struct mlx5_ifc_modify_tir_out_bits {
4991 u8 status[0x8];
4992 u8 reserved_at_8[0x18];
4993
4994 u8 syndrome[0x20];
4995
4996 u8 reserved_at_40[0x40];
4997};
4998
4999struct mlx5_ifc_modify_tir_in_bits {
5000 u8 opcode[0x10];
5001 u8 reserved_at_10[0x10];
5002
5003 u8 reserved_at_20[0x10];
5004 u8 op_mod[0x10];
5005
5006 u8 reserved_at_40[0x8];
5007 u8 tirn[0x18];
5008
5009 u8 reserved_at_60[0x20];
5010
5011 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5012
5013 u8 reserved_at_c0[0x40];
5014
5015 struct mlx5_ifc_tirc_bits ctx;
5016};
5017
5018struct mlx5_ifc_modify_sq_out_bits {
5019 u8 status[0x8];
5020 u8 reserved_at_8[0x18];
5021
5022 u8 syndrome[0x20];
5023
5024 u8 reserved_at_40[0x40];
5025};
5026
5027struct mlx5_ifc_modify_sq_in_bits {
5028 u8 opcode[0x10];
5029 u8 reserved_at_10[0x10];
5030
5031 u8 reserved_at_20[0x10];
5032 u8 op_mod[0x10];
5033
5034 u8 sq_state[0x4];
5035 u8 reserved_at_44[0x4];
5036 u8 sqn[0x18];
5037
5038 u8 reserved_at_60[0x20];
5039
5040 u8 modify_bitmask[0x40];
5041
5042 u8 reserved_at_c0[0x40];
5043
5044 struct mlx5_ifc_sqc_bits ctx;
5045};
5046
5047struct mlx5_ifc_modify_scheduling_element_out_bits {
5048 u8 status[0x8];
5049 u8 reserved_at_8[0x18];
5050
5051 u8 syndrome[0x20];
5052
5053 u8 reserved_at_40[0x1c0];
5054};
5055
5056enum {
5057 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5058 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5059};
5060
5061struct mlx5_ifc_modify_scheduling_element_in_bits {
5062 u8 opcode[0x10];
5063 u8 reserved_at_10[0x10];
5064
5065 u8 reserved_at_20[0x10];
5066 u8 op_mod[0x10];
5067
5068 u8 scheduling_hierarchy[0x8];
5069 u8 reserved_at_48[0x18];
5070
5071 u8 scheduling_element_id[0x20];
5072
5073 u8 reserved_at_80[0x20];
5074
5075 u8 modify_bitmask[0x20];
5076
5077 u8 reserved_at_c0[0x40];
5078
5079 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5080
5081 u8 reserved_at_300[0x100];
5082};
5083
5084struct mlx5_ifc_modify_rqt_out_bits {
5085 u8 status[0x8];
5086 u8 reserved_at_8[0x18];
5087
5088 u8 syndrome[0x20];
5089
5090 u8 reserved_at_40[0x40];
5091};
5092
5093struct mlx5_ifc_rqt_bitmask_bits {
5094 u8 reserved_at_0[0x20];
5095
5096 u8 reserved_at_20[0x1f];
5097 u8 rqn_list[0x1];
5098};
5099
5100struct mlx5_ifc_modify_rqt_in_bits {
5101 u8 opcode[0x10];
5102 u8 reserved_at_10[0x10];
5103
5104 u8 reserved_at_20[0x10];
5105 u8 op_mod[0x10];
5106
5107 u8 reserved_at_40[0x8];
5108 u8 rqtn[0x18];
5109
5110 u8 reserved_at_60[0x20];
5111
5112 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5113
5114 u8 reserved_at_c0[0x40];
5115
5116 struct mlx5_ifc_rqtc_bits ctx;
5117};
5118
5119struct mlx5_ifc_modify_rq_out_bits {
5120 u8 status[0x8];
5121 u8 reserved_at_8[0x18];
5122
5123 u8 syndrome[0x20];
5124
5125 u8 reserved_at_40[0x40];
5126};
5127
5128enum {
5129 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5130 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5131 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5132};
5133
5134struct mlx5_ifc_modify_rq_in_bits {
5135 u8 opcode[0x10];
5136 u8 reserved_at_10[0x10];
5137
5138 u8 reserved_at_20[0x10];
5139 u8 op_mod[0x10];
5140
5141 u8 rq_state[0x4];
5142 u8 reserved_at_44[0x4];
5143 u8 rqn[0x18];
5144
5145 u8 reserved_at_60[0x20];
5146
5147 u8 modify_bitmask[0x40];
5148
5149 u8 reserved_at_c0[0x40];
5150
5151 struct mlx5_ifc_rqc_bits ctx;
5152};
5153
5154struct mlx5_ifc_modify_rmp_out_bits {
5155 u8 status[0x8];
5156 u8 reserved_at_8[0x18];
5157
5158 u8 syndrome[0x20];
5159
5160 u8 reserved_at_40[0x40];
5161};
5162
5163struct mlx5_ifc_rmp_bitmask_bits {
5164 u8 reserved_at_0[0x20];
5165
5166 u8 reserved_at_20[0x1f];
5167 u8 lwm[0x1];
5168};
5169
5170struct mlx5_ifc_modify_rmp_in_bits {
5171 u8 opcode[0x10];
5172 u8 reserved_at_10[0x10];
5173
5174 u8 reserved_at_20[0x10];
5175 u8 op_mod[0x10];
5176
5177 u8 rmp_state[0x4];
5178 u8 reserved_at_44[0x4];
5179 u8 rmpn[0x18];
5180
5181 u8 reserved_at_60[0x20];
5182
5183 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5184
5185 u8 reserved_at_c0[0x40];
5186
5187 struct mlx5_ifc_rmpc_bits ctx;
5188};
5189
5190struct mlx5_ifc_modify_nic_vport_context_out_bits {
5191 u8 status[0x8];
5192 u8 reserved_at_8[0x18];
5193
5194 u8 syndrome[0x20];
5195
5196 u8 reserved_at_40[0x40];
5197};
5198
5199struct mlx5_ifc_modify_nic_vport_field_select_bits {
5200 u8 reserved_at_0[0x16];
5201 u8 node_guid[0x1];
5202 u8 port_guid[0x1];
5203 u8 min_inline[0x1];
5204 u8 mtu[0x1];
5205 u8 change_event[0x1];
5206 u8 promisc[0x1];
5207 u8 permanent_address[0x1];
5208 u8 addresses_list[0x1];
5209 u8 roce_en[0x1];
5210 u8 reserved_at_1f[0x1];
5211};
5212
5213struct mlx5_ifc_modify_nic_vport_context_in_bits {
5214 u8 opcode[0x10];
5215 u8 reserved_at_10[0x10];
5216
5217 u8 reserved_at_20[0x10];
5218 u8 op_mod[0x10];
5219
5220 u8 other_vport[0x1];
5221 u8 reserved_at_41[0xf];
5222 u8 vport_number[0x10];
5223
5224 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5225
5226 u8 reserved_at_80[0x780];
5227
5228 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5229};
5230
5231struct mlx5_ifc_modify_hca_vport_context_out_bits {
5232 u8 status[0x8];
5233 u8 reserved_at_8[0x18];
5234
5235 u8 syndrome[0x20];
5236
5237 u8 reserved_at_40[0x40];
5238};
5239
5240struct mlx5_ifc_modify_hca_vport_context_in_bits {
5241 u8 opcode[0x10];
5242 u8 reserved_at_10[0x10];
5243
5244 u8 reserved_at_20[0x10];
5245 u8 op_mod[0x10];
5246
5247 u8 other_vport[0x1];
5248 u8 reserved_at_41[0xb];
5249 u8 port_num[0x4];
5250 u8 vport_number[0x10];
5251
5252 u8 reserved_at_60[0x20];
5253
5254 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5255};
5256
5257struct mlx5_ifc_modify_cq_out_bits {
5258 u8 status[0x8];
5259 u8 reserved_at_8[0x18];
5260
5261 u8 syndrome[0x20];
5262
5263 u8 reserved_at_40[0x40];
5264};
5265
5266enum {
5267 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5268 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5269};
5270
5271struct mlx5_ifc_modify_cq_in_bits {
5272 u8 opcode[0x10];
5273 u8 reserved_at_10[0x10];
5274
5275 u8 reserved_at_20[0x10];
5276 u8 op_mod[0x10];
5277
5278 u8 reserved_at_40[0x8];
5279 u8 cqn[0x18];
5280
5281 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5282
5283 struct mlx5_ifc_cqc_bits cq_context;
5284
5285 u8 reserved_at_280[0x600];
5286
5287 u8 pas[0][0x40];
5288};
5289
5290struct mlx5_ifc_modify_cong_status_out_bits {
5291 u8 status[0x8];
5292 u8 reserved_at_8[0x18];
5293
5294 u8 syndrome[0x20];
5295
5296 u8 reserved_at_40[0x40];
5297};
5298
5299struct mlx5_ifc_modify_cong_status_in_bits {
5300 u8 opcode[0x10];
5301 u8 reserved_at_10[0x10];
5302
5303 u8 reserved_at_20[0x10];
5304 u8 op_mod[0x10];
5305
5306 u8 reserved_at_40[0x18];
5307 u8 priority[0x4];
5308 u8 cong_protocol[0x4];
5309
5310 u8 enable[0x1];
5311 u8 tag_enable[0x1];
5312 u8 reserved_at_62[0x1e];
5313};
5314
5315struct mlx5_ifc_modify_cong_params_out_bits {
5316 u8 status[0x8];
5317 u8 reserved_at_8[0x18];
5318
5319 u8 syndrome[0x20];
5320
5321 u8 reserved_at_40[0x40];
5322};
5323
5324struct mlx5_ifc_modify_cong_params_in_bits {
5325 u8 opcode[0x10];
5326 u8 reserved_at_10[0x10];
5327
5328 u8 reserved_at_20[0x10];
5329 u8 op_mod[0x10];
5330
5331 u8 reserved_at_40[0x1c];
5332 u8 cong_protocol[0x4];
5333
5334 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5335
5336 u8 reserved_at_80[0x80];
5337
5338 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5339};
5340
5341struct mlx5_ifc_manage_pages_out_bits {
5342 u8 status[0x8];
5343 u8 reserved_at_8[0x18];
5344
5345 u8 syndrome[0x20];
5346
5347 u8 output_num_entries[0x20];
5348
5349 u8 reserved_at_60[0x20];
5350
5351 u8 pas[0][0x40];
5352};
5353
5354enum {
5355 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5356 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5357 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5358};
5359
5360struct mlx5_ifc_manage_pages_in_bits {
5361 u8 opcode[0x10];
5362 u8 reserved_at_10[0x10];
5363
5364 u8 reserved_at_20[0x10];
5365 u8 op_mod[0x10];
5366
5367 u8 reserved_at_40[0x10];
5368 u8 function_id[0x10];
5369
5370 u8 input_num_entries[0x20];
5371
5372 u8 pas[0][0x40];
5373};
5374
5375struct mlx5_ifc_mad_ifc_out_bits {
5376 u8 status[0x8];
5377 u8 reserved_at_8[0x18];
5378
5379 u8 syndrome[0x20];
5380
5381 u8 reserved_at_40[0x40];
5382
5383 u8 response_mad_packet[256][0x8];
5384};
5385
5386struct mlx5_ifc_mad_ifc_in_bits {
5387 u8 opcode[0x10];
5388 u8 reserved_at_10[0x10];
5389
5390 u8 reserved_at_20[0x10];
5391 u8 op_mod[0x10];
5392
5393 u8 remote_lid[0x10];
5394 u8 reserved_at_50[0x8];
5395 u8 port[0x8];
5396
5397 u8 reserved_at_60[0x20];
5398
5399 u8 mad[256][0x8];
5400};
5401
5402struct mlx5_ifc_init_hca_out_bits {
5403 u8 status[0x8];
5404 u8 reserved_at_8[0x18];
5405
5406 u8 syndrome[0x20];
5407
5408 u8 reserved_at_40[0x40];
5409};
5410
5411struct mlx5_ifc_init_hca_in_bits {
5412 u8 opcode[0x10];
5413 u8 reserved_at_10[0x10];
5414
5415 u8 reserved_at_20[0x10];
5416 u8 op_mod[0x10];
5417
5418 u8 reserved_at_40[0x40];
5419};
5420
5421struct mlx5_ifc_init2rtr_qp_out_bits {
5422 u8 status[0x8];
5423 u8 reserved_at_8[0x18];
5424
5425 u8 syndrome[0x20];
5426
5427 u8 reserved_at_40[0x40];
5428};
5429
5430struct mlx5_ifc_init2rtr_qp_in_bits {
5431 u8 opcode[0x10];
5432 u8 reserved_at_10[0x10];
5433
5434 u8 reserved_at_20[0x10];
5435 u8 op_mod[0x10];
5436
5437 u8 reserved_at_40[0x8];
5438 u8 qpn[0x18];
5439
5440 u8 reserved_at_60[0x20];
5441
5442 u8 opt_param_mask[0x20];
5443
5444 u8 reserved_at_a0[0x20];
5445
5446 struct mlx5_ifc_qpc_bits qpc;
5447
5448 u8 reserved_at_800[0x80];
5449};
5450
5451struct mlx5_ifc_init2init_qp_out_bits {
5452 u8 status[0x8];
5453 u8 reserved_at_8[0x18];
5454
5455 u8 syndrome[0x20];
5456
5457 u8 reserved_at_40[0x40];
5458};
5459
5460struct mlx5_ifc_init2init_qp_in_bits {
5461 u8 opcode[0x10];
5462 u8 reserved_at_10[0x10];
5463
5464 u8 reserved_at_20[0x10];
5465 u8 op_mod[0x10];
5466
5467 u8 reserved_at_40[0x8];
5468 u8 qpn[0x18];
5469
5470 u8 reserved_at_60[0x20];
5471
5472 u8 opt_param_mask[0x20];
5473
5474 u8 reserved_at_a0[0x20];
5475
5476 struct mlx5_ifc_qpc_bits qpc;
5477
5478 u8 reserved_at_800[0x80];
5479};
5480
5481struct mlx5_ifc_get_dropped_packet_log_out_bits {
5482 u8 status[0x8];
5483 u8 reserved_at_8[0x18];
5484
5485 u8 syndrome[0x20];
5486
5487 u8 reserved_at_40[0x40];
5488
5489 u8 packet_headers_log[128][0x8];
5490
5491 u8 packet_syndrome[64][0x8];
5492};
5493
5494struct mlx5_ifc_get_dropped_packet_log_in_bits {
5495 u8 opcode[0x10];
5496 u8 reserved_at_10[0x10];
5497
5498 u8 reserved_at_20[0x10];
5499 u8 op_mod[0x10];
5500
5501 u8 reserved_at_40[0x40];
5502};
5503
5504struct mlx5_ifc_gen_eqe_in_bits {
5505 u8 opcode[0x10];
5506 u8 reserved_at_10[0x10];
5507
5508 u8 reserved_at_20[0x10];
5509 u8 op_mod[0x10];
5510
5511 u8 reserved_at_40[0x18];
5512 u8 eq_number[0x8];
5513
5514 u8 reserved_at_60[0x20];
5515
5516 u8 eqe[64][0x8];
5517};
5518
5519struct mlx5_ifc_gen_eq_out_bits {
5520 u8 status[0x8];
5521 u8 reserved_at_8[0x18];
5522
5523 u8 syndrome[0x20];
5524
5525 u8 reserved_at_40[0x40];
5526};
5527
5528struct mlx5_ifc_enable_hca_out_bits {
5529 u8 status[0x8];
5530 u8 reserved_at_8[0x18];
5531
5532 u8 syndrome[0x20];
5533
5534 u8 reserved_at_40[0x20];
5535};
5536
5537struct mlx5_ifc_enable_hca_in_bits {
5538 u8 opcode[0x10];
5539 u8 reserved_at_10[0x10];
5540
5541 u8 reserved_at_20[0x10];
5542 u8 op_mod[0x10];
5543
5544 u8 reserved_at_40[0x10];
5545 u8 function_id[0x10];
5546
5547 u8 reserved_at_60[0x20];
5548};
5549
5550struct mlx5_ifc_drain_dct_out_bits {
5551 u8 status[0x8];
5552 u8 reserved_at_8[0x18];
5553
5554 u8 syndrome[0x20];
5555
5556 u8 reserved_at_40[0x40];
5557};
5558
5559struct mlx5_ifc_drain_dct_in_bits {
5560 u8 opcode[0x10];
5561 u8 reserved_at_10[0x10];
5562
5563 u8 reserved_at_20[0x10];
5564 u8 op_mod[0x10];
5565
5566 u8 reserved_at_40[0x8];
5567 u8 dctn[0x18];
5568
5569 u8 reserved_at_60[0x20];
5570};
5571
5572struct mlx5_ifc_disable_hca_out_bits {
5573 u8 status[0x8];
5574 u8 reserved_at_8[0x18];
5575
5576 u8 syndrome[0x20];
5577
5578 u8 reserved_at_40[0x20];
5579};
5580
5581struct mlx5_ifc_disable_hca_in_bits {
5582 u8 opcode[0x10];
5583 u8 reserved_at_10[0x10];
5584
5585 u8 reserved_at_20[0x10];
5586 u8 op_mod[0x10];
5587
5588 u8 reserved_at_40[0x10];
5589 u8 function_id[0x10];
5590
5591 u8 reserved_at_60[0x20];
5592};
5593
5594struct mlx5_ifc_detach_from_mcg_out_bits {
5595 u8 status[0x8];
5596 u8 reserved_at_8[0x18];
5597
5598 u8 syndrome[0x20];
5599
5600 u8 reserved_at_40[0x40];
5601};
5602
5603struct mlx5_ifc_detach_from_mcg_in_bits {
5604 u8 opcode[0x10];
5605 u8 reserved_at_10[0x10];
5606
5607 u8 reserved_at_20[0x10];
5608 u8 op_mod[0x10];
5609
5610 u8 reserved_at_40[0x8];
5611 u8 qpn[0x18];
5612
5613 u8 reserved_at_60[0x20];
5614
5615 u8 multicast_gid[16][0x8];
5616};
5617
5618struct mlx5_ifc_destroy_xrq_out_bits {
5619 u8 status[0x8];
5620 u8 reserved_at_8[0x18];
5621
5622 u8 syndrome[0x20];
5623
5624 u8 reserved_at_40[0x40];
5625};
5626
5627struct mlx5_ifc_destroy_xrq_in_bits {
5628 u8 opcode[0x10];
5629 u8 reserved_at_10[0x10];
5630
5631 u8 reserved_at_20[0x10];
5632 u8 op_mod[0x10];
5633
5634 u8 reserved_at_40[0x8];
5635 u8 xrqn[0x18];
5636
5637 u8 reserved_at_60[0x20];
5638};
5639
5640struct mlx5_ifc_destroy_xrc_srq_out_bits {
5641 u8 status[0x8];
5642 u8 reserved_at_8[0x18];
5643
5644 u8 syndrome[0x20];
5645
5646 u8 reserved_at_40[0x40];
5647};
5648
5649struct mlx5_ifc_destroy_xrc_srq_in_bits {
5650 u8 opcode[0x10];
5651 u8 reserved_at_10[0x10];
5652
5653 u8 reserved_at_20[0x10];
5654 u8 op_mod[0x10];
5655
5656 u8 reserved_at_40[0x8];
5657 u8 xrc_srqn[0x18];
5658
5659 u8 reserved_at_60[0x20];
5660};
5661
5662struct mlx5_ifc_destroy_tis_out_bits {
5663 u8 status[0x8];
5664 u8 reserved_at_8[0x18];
5665
5666 u8 syndrome[0x20];
5667
5668 u8 reserved_at_40[0x40];
5669};
5670
5671struct mlx5_ifc_destroy_tis_in_bits {
5672 u8 opcode[0x10];
5673 u8 reserved_at_10[0x10];
5674
5675 u8 reserved_at_20[0x10];
5676 u8 op_mod[0x10];
5677
5678 u8 reserved_at_40[0x8];
5679 u8 tisn[0x18];
5680
5681 u8 reserved_at_60[0x20];
5682};
5683
5684struct mlx5_ifc_destroy_tir_out_bits {
5685 u8 status[0x8];
5686 u8 reserved_at_8[0x18];
5687
5688 u8 syndrome[0x20];
5689
5690 u8 reserved_at_40[0x40];
5691};
5692
5693struct mlx5_ifc_destroy_tir_in_bits {
5694 u8 opcode[0x10];
5695 u8 reserved_at_10[0x10];
5696
5697 u8 reserved_at_20[0x10];
5698 u8 op_mod[0x10];
5699
5700 u8 reserved_at_40[0x8];
5701 u8 tirn[0x18];
5702
5703 u8 reserved_at_60[0x20];
5704};
5705
5706struct mlx5_ifc_destroy_srq_out_bits {
5707 u8 status[0x8];
5708 u8 reserved_at_8[0x18];
5709
5710 u8 syndrome[0x20];
5711
5712 u8 reserved_at_40[0x40];
5713};
5714
5715struct mlx5_ifc_destroy_srq_in_bits {
5716 u8 opcode[0x10];
5717 u8 reserved_at_10[0x10];
5718
5719 u8 reserved_at_20[0x10];
5720 u8 op_mod[0x10];
5721
5722 u8 reserved_at_40[0x8];
5723 u8 srqn[0x18];
5724
5725 u8 reserved_at_60[0x20];
5726};
5727
5728struct mlx5_ifc_destroy_sq_out_bits {
5729 u8 status[0x8];
5730 u8 reserved_at_8[0x18];
5731
5732 u8 syndrome[0x20];
5733
5734 u8 reserved_at_40[0x40];
5735};
5736
5737struct mlx5_ifc_destroy_sq_in_bits {
5738 u8 opcode[0x10];
5739 u8 reserved_at_10[0x10];
5740
5741 u8 reserved_at_20[0x10];
5742 u8 op_mod[0x10];
5743
5744 u8 reserved_at_40[0x8];
5745 u8 sqn[0x18];
5746
5747 u8 reserved_at_60[0x20];
5748};
5749
5750struct mlx5_ifc_destroy_scheduling_element_out_bits {
5751 u8 status[0x8];
5752 u8 reserved_at_8[0x18];
5753
5754 u8 syndrome[0x20];
5755
5756 u8 reserved_at_40[0x1c0];
5757};
5758
5759struct mlx5_ifc_destroy_scheduling_element_in_bits {
5760 u8 opcode[0x10];
5761 u8 reserved_at_10[0x10];
5762
5763 u8 reserved_at_20[0x10];
5764 u8 op_mod[0x10];
5765
5766 u8 scheduling_hierarchy[0x8];
5767 u8 reserved_at_48[0x18];
5768
5769 u8 scheduling_element_id[0x20];
5770
5771 u8 reserved_at_80[0x180];
5772};
5773
5774struct mlx5_ifc_destroy_rqt_out_bits {
5775 u8 status[0x8];
5776 u8 reserved_at_8[0x18];
5777
5778 u8 syndrome[0x20];
5779
5780 u8 reserved_at_40[0x40];
5781};
5782
5783struct mlx5_ifc_destroy_rqt_in_bits {
5784 u8 opcode[0x10];
5785 u8 reserved_at_10[0x10];
5786
5787 u8 reserved_at_20[0x10];
5788 u8 op_mod[0x10];
5789
5790 u8 reserved_at_40[0x8];
5791 u8 rqtn[0x18];
5792
5793 u8 reserved_at_60[0x20];
5794};
5795
5796struct mlx5_ifc_destroy_rq_out_bits {
5797 u8 status[0x8];
5798 u8 reserved_at_8[0x18];
5799
5800 u8 syndrome[0x20];
5801
5802 u8 reserved_at_40[0x40];
5803};
5804
5805struct mlx5_ifc_destroy_rq_in_bits {
5806 u8 opcode[0x10];
5807 u8 reserved_at_10[0x10];
5808
5809 u8 reserved_at_20[0x10];
5810 u8 op_mod[0x10];
5811
5812 u8 reserved_at_40[0x8];
5813 u8 rqn[0x18];
5814
5815 u8 reserved_at_60[0x20];
5816};
5817
5818struct mlx5_ifc_destroy_rmp_out_bits {
5819 u8 status[0x8];
5820 u8 reserved_at_8[0x18];
5821
5822 u8 syndrome[0x20];
5823
5824 u8 reserved_at_40[0x40];
5825};
5826
5827struct mlx5_ifc_destroy_rmp_in_bits {
5828 u8 opcode[0x10];
5829 u8 reserved_at_10[0x10];
5830
5831 u8 reserved_at_20[0x10];
5832 u8 op_mod[0x10];
5833
5834 u8 reserved_at_40[0x8];
5835 u8 rmpn[0x18];
5836
5837 u8 reserved_at_60[0x20];
5838};
5839
5840struct mlx5_ifc_destroy_qp_out_bits {
5841 u8 status[0x8];
5842 u8 reserved_at_8[0x18];
5843
5844 u8 syndrome[0x20];
5845
5846 u8 reserved_at_40[0x40];
5847};
5848
5849struct mlx5_ifc_destroy_qp_in_bits {
5850 u8 opcode[0x10];
5851 u8 reserved_at_10[0x10];
5852
5853 u8 reserved_at_20[0x10];
5854 u8 op_mod[0x10];
5855
5856 u8 reserved_at_40[0x8];
5857 u8 qpn[0x18];
5858
5859 u8 reserved_at_60[0x20];
5860};
5861
5862struct mlx5_ifc_destroy_psv_out_bits {
5863 u8 status[0x8];
5864 u8 reserved_at_8[0x18];
5865
5866 u8 syndrome[0x20];
5867
5868 u8 reserved_at_40[0x40];
5869};
5870
5871struct mlx5_ifc_destroy_psv_in_bits {
5872 u8 opcode[0x10];
5873 u8 reserved_at_10[0x10];
5874
5875 u8 reserved_at_20[0x10];
5876 u8 op_mod[0x10];
5877
5878 u8 reserved_at_40[0x8];
5879 u8 psvn[0x18];
5880
5881 u8 reserved_at_60[0x20];
5882};
5883
5884struct mlx5_ifc_destroy_mkey_out_bits {
5885 u8 status[0x8];
5886 u8 reserved_at_8[0x18];
5887
5888 u8 syndrome[0x20];
5889
5890 u8 reserved_at_40[0x40];
5891};
5892
5893struct mlx5_ifc_destroy_mkey_in_bits {
5894 u8 opcode[0x10];
5895 u8 reserved_at_10[0x10];
5896
5897 u8 reserved_at_20[0x10];
5898 u8 op_mod[0x10];
5899
5900 u8 reserved_at_40[0x8];
5901 u8 mkey_index[0x18];
5902
5903 u8 reserved_at_60[0x20];
5904};
5905
5906struct mlx5_ifc_destroy_flow_table_out_bits {
5907 u8 status[0x8];
5908 u8 reserved_at_8[0x18];
5909
5910 u8 syndrome[0x20];
5911
5912 u8 reserved_at_40[0x40];
5913};
5914
5915struct mlx5_ifc_destroy_flow_table_in_bits {
5916 u8 opcode[0x10];
5917 u8 reserved_at_10[0x10];
5918
5919 u8 reserved_at_20[0x10];
5920 u8 op_mod[0x10];
5921
5922 u8 other_vport[0x1];
5923 u8 reserved_at_41[0xf];
5924 u8 vport_number[0x10];
5925
5926 u8 reserved_at_60[0x20];
5927
5928 u8 table_type[0x8];
5929 u8 reserved_at_88[0x18];
5930
5931 u8 reserved_at_a0[0x8];
5932 u8 table_id[0x18];
5933
5934 u8 reserved_at_c0[0x140];
5935};
5936
5937struct mlx5_ifc_destroy_flow_group_out_bits {
5938 u8 status[0x8];
5939 u8 reserved_at_8[0x18];
5940
5941 u8 syndrome[0x20];
5942
5943 u8 reserved_at_40[0x40];
5944};
5945
5946struct mlx5_ifc_destroy_flow_group_in_bits {
5947 u8 opcode[0x10];
5948 u8 reserved_at_10[0x10];
5949
5950 u8 reserved_at_20[0x10];
5951 u8 op_mod[0x10];
5952
5953 u8 other_vport[0x1];
5954 u8 reserved_at_41[0xf];
5955 u8 vport_number[0x10];
5956
5957 u8 reserved_at_60[0x20];
5958
5959 u8 table_type[0x8];
5960 u8 reserved_at_88[0x18];
5961
5962 u8 reserved_at_a0[0x8];
5963 u8 table_id[0x18];
5964
5965 u8 group_id[0x20];
5966
5967 u8 reserved_at_e0[0x120];
5968};
5969
5970struct mlx5_ifc_destroy_eq_out_bits {
5971 u8 status[0x8];
5972 u8 reserved_at_8[0x18];
5973
5974 u8 syndrome[0x20];
5975
5976 u8 reserved_at_40[0x40];
5977};
5978
5979struct mlx5_ifc_destroy_eq_in_bits {
5980 u8 opcode[0x10];
5981 u8 reserved_at_10[0x10];
5982
5983 u8 reserved_at_20[0x10];
5984 u8 op_mod[0x10];
5985
5986 u8 reserved_at_40[0x18];
5987 u8 eq_number[0x8];
5988
5989 u8 reserved_at_60[0x20];
5990};
5991
5992struct mlx5_ifc_destroy_dct_out_bits {
5993 u8 status[0x8];
5994 u8 reserved_at_8[0x18];
5995
5996 u8 syndrome[0x20];
5997
5998 u8 reserved_at_40[0x40];
5999};
6000
6001struct mlx5_ifc_destroy_dct_in_bits {
6002 u8 opcode[0x10];
6003 u8 reserved_at_10[0x10];
6004
6005 u8 reserved_at_20[0x10];
6006 u8 op_mod[0x10];
6007
6008 u8 reserved_at_40[0x8];
6009 u8 dctn[0x18];
6010
6011 u8 reserved_at_60[0x20];
6012};
6013
6014struct mlx5_ifc_destroy_cq_out_bits {
6015 u8 status[0x8];
6016 u8 reserved_at_8[0x18];
6017
6018 u8 syndrome[0x20];
6019
6020 u8 reserved_at_40[0x40];
6021};
6022
6023struct mlx5_ifc_destroy_cq_in_bits {
6024 u8 opcode[0x10];
6025 u8 reserved_at_10[0x10];
6026
6027 u8 reserved_at_20[0x10];
6028 u8 op_mod[0x10];
6029
6030 u8 reserved_at_40[0x8];
6031 u8 cqn[0x18];
6032
6033 u8 reserved_at_60[0x20];
6034};
6035
6036struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6037 u8 status[0x8];
6038 u8 reserved_at_8[0x18];
6039
6040 u8 syndrome[0x20];
6041
6042 u8 reserved_at_40[0x40];
6043};
6044
6045struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6046 u8 opcode[0x10];
6047 u8 reserved_at_10[0x10];
6048
6049 u8 reserved_at_20[0x10];
6050 u8 op_mod[0x10];
6051
6052 u8 reserved_at_40[0x20];
6053
6054 u8 reserved_at_60[0x10];
6055 u8 vxlan_udp_port[0x10];
6056};
6057
6058struct mlx5_ifc_delete_l2_table_entry_out_bits {
6059 u8 status[0x8];
6060 u8 reserved_at_8[0x18];
6061
6062 u8 syndrome[0x20];
6063
6064 u8 reserved_at_40[0x40];
6065};
6066
6067struct mlx5_ifc_delete_l2_table_entry_in_bits {
6068 u8 opcode[0x10];
6069 u8 reserved_at_10[0x10];
6070
6071 u8 reserved_at_20[0x10];
6072 u8 op_mod[0x10];
6073
6074 u8 reserved_at_40[0x60];
6075
6076 u8 reserved_at_a0[0x8];
6077 u8 table_index[0x18];
6078
6079 u8 reserved_at_c0[0x140];
6080};
6081
6082struct mlx5_ifc_delete_fte_out_bits {
6083 u8 status[0x8];
6084 u8 reserved_at_8[0x18];
6085
6086 u8 syndrome[0x20];
6087
6088 u8 reserved_at_40[0x40];
6089};
6090
6091struct mlx5_ifc_delete_fte_in_bits {
6092 u8 opcode[0x10];
6093 u8 reserved_at_10[0x10];
6094
6095 u8 reserved_at_20[0x10];
6096 u8 op_mod[0x10];
6097
6098 u8 other_vport[0x1];
6099 u8 reserved_at_41[0xf];
6100 u8 vport_number[0x10];
6101
6102 u8 reserved_at_60[0x20];
6103
6104 u8 table_type[0x8];
6105 u8 reserved_at_88[0x18];
6106
6107 u8 reserved_at_a0[0x8];
6108 u8 table_id[0x18];
6109
6110 u8 reserved_at_c0[0x40];
6111
6112 u8 flow_index[0x20];
6113
6114 u8 reserved_at_120[0xe0];
6115};
6116
6117struct mlx5_ifc_dealloc_xrcd_out_bits {
6118 u8 status[0x8];
6119 u8 reserved_at_8[0x18];
6120
6121 u8 syndrome[0x20];
6122
6123 u8 reserved_at_40[0x40];
6124};
6125
6126struct mlx5_ifc_dealloc_xrcd_in_bits {
6127 u8 opcode[0x10];
6128 u8 reserved_at_10[0x10];
6129
6130 u8 reserved_at_20[0x10];
6131 u8 op_mod[0x10];
6132
6133 u8 reserved_at_40[0x8];
6134 u8 xrcd[0x18];
6135
6136 u8 reserved_at_60[0x20];
6137};
6138
6139struct mlx5_ifc_dealloc_uar_out_bits {
6140 u8 status[0x8];
6141 u8 reserved_at_8[0x18];
6142
6143 u8 syndrome[0x20];
6144
6145 u8 reserved_at_40[0x40];
6146};
6147
6148struct mlx5_ifc_dealloc_uar_in_bits {
6149 u8 opcode[0x10];
6150 u8 reserved_at_10[0x10];
6151
6152 u8 reserved_at_20[0x10];
6153 u8 op_mod[0x10];
6154
6155 u8 reserved_at_40[0x8];
6156 u8 uar[0x18];
6157
6158 u8 reserved_at_60[0x20];
6159};
6160
6161struct mlx5_ifc_dealloc_transport_domain_out_bits {
6162 u8 status[0x8];
6163 u8 reserved_at_8[0x18];
6164
6165 u8 syndrome[0x20];
6166
6167 u8 reserved_at_40[0x40];
6168};
6169
6170struct mlx5_ifc_dealloc_transport_domain_in_bits {
6171 u8 opcode[0x10];
6172 u8 reserved_at_10[0x10];
6173
6174 u8 reserved_at_20[0x10];
6175 u8 op_mod[0x10];
6176
6177 u8 reserved_at_40[0x8];
6178 u8 transport_domain[0x18];
6179
6180 u8 reserved_at_60[0x20];
6181};
6182
6183struct mlx5_ifc_dealloc_q_counter_out_bits {
6184 u8 status[0x8];
6185 u8 reserved_at_8[0x18];
6186
6187 u8 syndrome[0x20];
6188
6189 u8 reserved_at_40[0x40];
6190};
6191
6192struct mlx5_ifc_dealloc_q_counter_in_bits {
6193 u8 opcode[0x10];
6194 u8 reserved_at_10[0x10];
6195
6196 u8 reserved_at_20[0x10];
6197 u8 op_mod[0x10];
6198
6199 u8 reserved_at_40[0x18];
6200 u8 counter_set_id[0x8];
6201
6202 u8 reserved_at_60[0x20];
6203};
6204
6205struct mlx5_ifc_dealloc_pd_out_bits {
6206 u8 status[0x8];
6207 u8 reserved_at_8[0x18];
6208
6209 u8 syndrome[0x20];
6210
6211 u8 reserved_at_40[0x40];
6212};
6213
6214struct mlx5_ifc_dealloc_pd_in_bits {
6215 u8 opcode[0x10];
6216 u8 reserved_at_10[0x10];
6217
6218 u8 reserved_at_20[0x10];
6219 u8 op_mod[0x10];
6220
6221 u8 reserved_at_40[0x8];
6222 u8 pd[0x18];
6223
6224 u8 reserved_at_60[0x20];
6225};
6226
6227struct mlx5_ifc_dealloc_flow_counter_out_bits {
6228 u8 status[0x8];
6229 u8 reserved_at_8[0x18];
6230
6231 u8 syndrome[0x20];
6232
6233 u8 reserved_at_40[0x40];
6234};
6235
6236struct mlx5_ifc_dealloc_flow_counter_in_bits {
6237 u8 opcode[0x10];
6238 u8 reserved_at_10[0x10];
6239
6240 u8 reserved_at_20[0x10];
6241 u8 op_mod[0x10];
6242
6243 u8 reserved_at_40[0x10];
6244 u8 flow_counter_id[0x10];
6245
6246 u8 reserved_at_60[0x20];
6247};
6248
6249struct mlx5_ifc_create_xrq_out_bits {
6250 u8 status[0x8];
6251 u8 reserved_at_8[0x18];
6252
6253 u8 syndrome[0x20];
6254
6255 u8 reserved_at_40[0x8];
6256 u8 xrqn[0x18];
6257
6258 u8 reserved_at_60[0x20];
6259};
6260
6261struct mlx5_ifc_create_xrq_in_bits {
6262 u8 opcode[0x10];
6263 u8 reserved_at_10[0x10];
6264
6265 u8 reserved_at_20[0x10];
6266 u8 op_mod[0x10];
6267
6268 u8 reserved_at_40[0x40];
6269
6270 struct mlx5_ifc_xrqc_bits xrq_context;
6271};
6272
6273struct mlx5_ifc_create_xrc_srq_out_bits {
6274 u8 status[0x8];
6275 u8 reserved_at_8[0x18];
6276
6277 u8 syndrome[0x20];
6278
6279 u8 reserved_at_40[0x8];
6280 u8 xrc_srqn[0x18];
6281
6282 u8 reserved_at_60[0x20];
6283};
6284
6285struct mlx5_ifc_create_xrc_srq_in_bits {
6286 u8 opcode[0x10];
6287 u8 reserved_at_10[0x10];
6288
6289 u8 reserved_at_20[0x10];
6290 u8 op_mod[0x10];
6291
6292 u8 reserved_at_40[0x40];
6293
6294 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6295
6296 u8 reserved_at_280[0x600];
6297
6298 u8 pas[0][0x40];
6299};
6300
6301struct mlx5_ifc_create_tis_out_bits {
6302 u8 status[0x8];
6303 u8 reserved_at_8[0x18];
6304
6305 u8 syndrome[0x20];
6306
6307 u8 reserved_at_40[0x8];
6308 u8 tisn[0x18];
6309
6310 u8 reserved_at_60[0x20];
6311};
6312
6313struct mlx5_ifc_create_tis_in_bits {
6314 u8 opcode[0x10];
6315 u8 reserved_at_10[0x10];
6316
6317 u8 reserved_at_20[0x10];
6318 u8 op_mod[0x10];
6319
6320 u8 reserved_at_40[0xc0];
6321
6322 struct mlx5_ifc_tisc_bits ctx;
6323};
6324
6325struct mlx5_ifc_create_tir_out_bits {
6326 u8 status[0x8];
6327 u8 reserved_at_8[0x18];
6328
6329 u8 syndrome[0x20];
6330
6331 u8 reserved_at_40[0x8];
6332 u8 tirn[0x18];
6333
6334 u8 reserved_at_60[0x20];
6335};
6336
6337struct mlx5_ifc_create_tir_in_bits {
6338 u8 opcode[0x10];
6339 u8 reserved_at_10[0x10];
6340
6341 u8 reserved_at_20[0x10];
6342 u8 op_mod[0x10];
6343
6344 u8 reserved_at_40[0xc0];
6345
6346 struct mlx5_ifc_tirc_bits ctx;
6347};
6348
6349struct mlx5_ifc_create_srq_out_bits {
6350 u8 status[0x8];
6351 u8 reserved_at_8[0x18];
6352
6353 u8 syndrome[0x20];
6354
6355 u8 reserved_at_40[0x8];
6356 u8 srqn[0x18];
6357
6358 u8 reserved_at_60[0x20];
6359};
6360
6361struct mlx5_ifc_create_srq_in_bits {
6362 u8 opcode[0x10];
6363 u8 reserved_at_10[0x10];
6364
6365 u8 reserved_at_20[0x10];
6366 u8 op_mod[0x10];
6367
6368 u8 reserved_at_40[0x40];
6369
6370 struct mlx5_ifc_srqc_bits srq_context_entry;
6371
6372 u8 reserved_at_280[0x600];
6373
6374 u8 pas[0][0x40];
6375};
6376
6377struct mlx5_ifc_create_sq_out_bits {
6378 u8 status[0x8];
6379 u8 reserved_at_8[0x18];
6380
6381 u8 syndrome[0x20];
6382
6383 u8 reserved_at_40[0x8];
6384 u8 sqn[0x18];
6385
6386 u8 reserved_at_60[0x20];
6387};
6388
6389struct mlx5_ifc_create_sq_in_bits {
6390 u8 opcode[0x10];
6391 u8 reserved_at_10[0x10];
6392
6393 u8 reserved_at_20[0x10];
6394 u8 op_mod[0x10];
6395
6396 u8 reserved_at_40[0xc0];
6397
6398 struct mlx5_ifc_sqc_bits ctx;
6399};
6400
6401struct mlx5_ifc_create_scheduling_element_out_bits {
6402 u8 status[0x8];
6403 u8 reserved_at_8[0x18];
6404
6405 u8 syndrome[0x20];
6406
6407 u8 reserved_at_40[0x40];
6408
6409 u8 scheduling_element_id[0x20];
6410
6411 u8 reserved_at_a0[0x160];
6412};
6413
6414struct mlx5_ifc_create_scheduling_element_in_bits {
6415 u8 opcode[0x10];
6416 u8 reserved_at_10[0x10];
6417
6418 u8 reserved_at_20[0x10];
6419 u8 op_mod[0x10];
6420
6421 u8 scheduling_hierarchy[0x8];
6422 u8 reserved_at_48[0x18];
6423
6424 u8 reserved_at_60[0xa0];
6425
6426 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6427
6428 u8 reserved_at_300[0x100];
6429};
6430
6431struct mlx5_ifc_create_rqt_out_bits {
6432 u8 status[0x8];
6433 u8 reserved_at_8[0x18];
6434
6435 u8 syndrome[0x20];
6436
6437 u8 reserved_at_40[0x8];
6438 u8 rqtn[0x18];
6439
6440 u8 reserved_at_60[0x20];
6441};
6442
6443struct mlx5_ifc_create_rqt_in_bits {
6444 u8 opcode[0x10];
6445 u8 reserved_at_10[0x10];
6446
6447 u8 reserved_at_20[0x10];
6448 u8 op_mod[0x10];
6449
6450 u8 reserved_at_40[0xc0];
6451
6452 struct mlx5_ifc_rqtc_bits rqt_context;
6453};
6454
6455struct mlx5_ifc_create_rq_out_bits {
6456 u8 status[0x8];
6457 u8 reserved_at_8[0x18];
6458
6459 u8 syndrome[0x20];
6460
6461 u8 reserved_at_40[0x8];
6462 u8 rqn[0x18];
6463
6464 u8 reserved_at_60[0x20];
6465};
6466
6467struct mlx5_ifc_create_rq_in_bits {
6468 u8 opcode[0x10];
6469 u8 reserved_at_10[0x10];
6470
6471 u8 reserved_at_20[0x10];
6472 u8 op_mod[0x10];
6473
6474 u8 reserved_at_40[0xc0];
6475
6476 struct mlx5_ifc_rqc_bits ctx;
6477};
6478
6479struct mlx5_ifc_create_rmp_out_bits {
6480 u8 status[0x8];
6481 u8 reserved_at_8[0x18];
6482
6483 u8 syndrome[0x20];
6484
6485 u8 reserved_at_40[0x8];
6486 u8 rmpn[0x18];
6487
6488 u8 reserved_at_60[0x20];
6489};
6490
6491struct mlx5_ifc_create_rmp_in_bits {
6492 u8 opcode[0x10];
6493 u8 reserved_at_10[0x10];
6494
6495 u8 reserved_at_20[0x10];
6496 u8 op_mod[0x10];
6497
6498 u8 reserved_at_40[0xc0];
6499
6500 struct mlx5_ifc_rmpc_bits ctx;
6501};
6502
6503struct mlx5_ifc_create_qp_out_bits {
6504 u8 status[0x8];
6505 u8 reserved_at_8[0x18];
6506
6507 u8 syndrome[0x20];
6508
6509 u8 reserved_at_40[0x8];
6510 u8 qpn[0x18];
6511
6512 u8 reserved_at_60[0x20];
6513};
6514
6515struct mlx5_ifc_create_qp_in_bits {
6516 u8 opcode[0x10];
6517 u8 reserved_at_10[0x10];
6518
6519 u8 reserved_at_20[0x10];
6520 u8 op_mod[0x10];
6521
6522 u8 reserved_at_40[0x40];
6523
6524 u8 opt_param_mask[0x20];
6525
6526 u8 reserved_at_a0[0x20];
6527
6528 struct mlx5_ifc_qpc_bits qpc;
6529
6530 u8 reserved_at_800[0x80];
6531
6532 u8 pas[0][0x40];
6533};
6534
6535struct mlx5_ifc_create_psv_out_bits {
6536 u8 status[0x8];
6537 u8 reserved_at_8[0x18];
6538
6539 u8 syndrome[0x20];
6540
6541 u8 reserved_at_40[0x40];
6542
6543 u8 reserved_at_80[0x8];
6544 u8 psv0_index[0x18];
6545
6546 u8 reserved_at_a0[0x8];
6547 u8 psv1_index[0x18];
6548
6549 u8 reserved_at_c0[0x8];
6550 u8 psv2_index[0x18];
6551
6552 u8 reserved_at_e0[0x8];
6553 u8 psv3_index[0x18];
6554};
6555
6556struct mlx5_ifc_create_psv_in_bits {
6557 u8 opcode[0x10];
6558 u8 reserved_at_10[0x10];
6559
6560 u8 reserved_at_20[0x10];
6561 u8 op_mod[0x10];
6562
6563 u8 num_psv[0x4];
6564 u8 reserved_at_44[0x4];
6565 u8 pd[0x18];
6566
6567 u8 reserved_at_60[0x20];
6568};
6569
6570struct mlx5_ifc_create_mkey_out_bits {
6571 u8 status[0x8];
6572 u8 reserved_at_8[0x18];
6573
6574 u8 syndrome[0x20];
6575
6576 u8 reserved_at_40[0x8];
6577 u8 mkey_index[0x18];
6578
6579 u8 reserved_at_60[0x20];
6580};
6581
6582struct mlx5_ifc_create_mkey_in_bits {
6583 u8 opcode[0x10];
6584 u8 reserved_at_10[0x10];
6585
6586 u8 reserved_at_20[0x10];
6587 u8 op_mod[0x10];
6588
6589 u8 reserved_at_40[0x20];
6590
6591 u8 pg_access[0x1];
6592 u8 reserved_at_61[0x1f];
6593
6594 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6595
6596 u8 reserved_at_280[0x80];
6597
6598 u8 translations_octword_actual_size[0x20];
6599
6600 u8 reserved_at_320[0x560];
6601
6602 u8 klm_pas_mtt[0][0x20];
6603};
6604
6605struct mlx5_ifc_create_flow_table_out_bits {
6606 u8 status[0x8];
6607 u8 reserved_at_8[0x18];
6608
6609 u8 syndrome[0x20];
6610
6611 u8 reserved_at_40[0x8];
6612 u8 table_id[0x18];
6613
6614 u8 reserved_at_60[0x20];
6615};
6616
6617struct mlx5_ifc_create_flow_table_in_bits {
6618 u8 opcode[0x10];
6619 u8 reserved_at_10[0x10];
6620
6621 u8 reserved_at_20[0x10];
6622 u8 op_mod[0x10];
6623
6624 u8 other_vport[0x1];
6625 u8 reserved_at_41[0xf];
6626 u8 vport_number[0x10];
6627
6628 u8 reserved_at_60[0x20];
6629
6630 u8 table_type[0x8];
6631 u8 reserved_at_88[0x18];
6632
6633 u8 reserved_at_a0[0x20];
6634
6635 u8 encap_en[0x1];
6636 u8 decap_en[0x1];
6637 u8 reserved_at_c2[0x2];
6638 u8 table_miss_mode[0x4];
6639 u8 level[0x8];
6640 u8 reserved_at_d0[0x8];
6641 u8 log_size[0x8];
6642
6643 u8 reserved_at_e0[0x8];
6644 u8 table_miss_id[0x18];
6645
6646 u8 reserved_at_100[0x8];
6647 u8 lag_master_next_table_id[0x18];
6648
6649 u8 reserved_at_120[0x80];
6650};
6651
6652struct mlx5_ifc_create_flow_group_out_bits {
6653 u8 status[0x8];
6654 u8 reserved_at_8[0x18];
6655
6656 u8 syndrome[0x20];
6657
6658 u8 reserved_at_40[0x8];
6659 u8 group_id[0x18];
6660
6661 u8 reserved_at_60[0x20];
6662};
6663
6664enum {
6665 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6666 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6667 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6668};
6669
6670struct mlx5_ifc_create_flow_group_in_bits {
6671 u8 opcode[0x10];
6672 u8 reserved_at_10[0x10];
6673
6674 u8 reserved_at_20[0x10];
6675 u8 op_mod[0x10];
6676
6677 u8 other_vport[0x1];
6678 u8 reserved_at_41[0xf];
6679 u8 vport_number[0x10];
6680
6681 u8 reserved_at_60[0x20];
6682
6683 u8 table_type[0x8];
6684 u8 reserved_at_88[0x18];
6685
6686 u8 reserved_at_a0[0x8];
6687 u8 table_id[0x18];
6688
6689 u8 reserved_at_c0[0x20];
6690
6691 u8 start_flow_index[0x20];
6692
6693 u8 reserved_at_100[0x20];
6694
6695 u8 end_flow_index[0x20];
6696
6697 u8 reserved_at_140[0xa0];
6698
6699 u8 reserved_at_1e0[0x18];
6700 u8 match_criteria_enable[0x8];
6701
6702 struct mlx5_ifc_fte_match_param_bits match_criteria;
6703
6704 u8 reserved_at_1200[0xe00];
6705};
6706
6707struct mlx5_ifc_create_eq_out_bits {
6708 u8 status[0x8];
6709 u8 reserved_at_8[0x18];
6710
6711 u8 syndrome[0x20];
6712
6713 u8 reserved_at_40[0x18];
6714 u8 eq_number[0x8];
6715
6716 u8 reserved_at_60[0x20];
6717};
6718
6719struct mlx5_ifc_create_eq_in_bits {
6720 u8 opcode[0x10];
6721 u8 reserved_at_10[0x10];
6722
6723 u8 reserved_at_20[0x10];
6724 u8 op_mod[0x10];
6725
6726 u8 reserved_at_40[0x40];
6727
6728 struct mlx5_ifc_eqc_bits eq_context_entry;
6729
6730 u8 reserved_at_280[0x40];
6731
6732 u8 event_bitmask[0x40];
6733
6734 u8 reserved_at_300[0x580];
6735
6736 u8 pas[0][0x40];
6737};
6738
6739struct mlx5_ifc_create_dct_out_bits {
6740 u8 status[0x8];
6741 u8 reserved_at_8[0x18];
6742
6743 u8 syndrome[0x20];
6744
6745 u8 reserved_at_40[0x8];
6746 u8 dctn[0x18];
6747
6748 u8 reserved_at_60[0x20];
6749};
6750
6751struct mlx5_ifc_create_dct_in_bits {
6752 u8 opcode[0x10];
6753 u8 reserved_at_10[0x10];
6754
6755 u8 reserved_at_20[0x10];
6756 u8 op_mod[0x10];
6757
6758 u8 reserved_at_40[0x40];
6759
6760 struct mlx5_ifc_dctc_bits dct_context_entry;
6761
6762 u8 reserved_at_280[0x180];
6763};
6764
6765struct mlx5_ifc_create_cq_out_bits {
6766 u8 status[0x8];
6767 u8 reserved_at_8[0x18];
6768
6769 u8 syndrome[0x20];
6770
6771 u8 reserved_at_40[0x8];
6772 u8 cqn[0x18];
6773
6774 u8 reserved_at_60[0x20];
6775};
6776
6777struct mlx5_ifc_create_cq_in_bits {
6778 u8 opcode[0x10];
6779 u8 reserved_at_10[0x10];
6780
6781 u8 reserved_at_20[0x10];
6782 u8 op_mod[0x10];
6783
6784 u8 reserved_at_40[0x40];
6785
6786 struct mlx5_ifc_cqc_bits cq_context;
6787
6788 u8 reserved_at_280[0x600];
6789
6790 u8 pas[0][0x40];
6791};
6792
6793struct mlx5_ifc_config_int_moderation_out_bits {
6794 u8 status[0x8];
6795 u8 reserved_at_8[0x18];
6796
6797 u8 syndrome[0x20];
6798
6799 u8 reserved_at_40[0x4];
6800 u8 min_delay[0xc];
6801 u8 int_vector[0x10];
6802
6803 u8 reserved_at_60[0x20];
6804};
6805
6806enum {
6807 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6808 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6809};
6810
6811struct mlx5_ifc_config_int_moderation_in_bits {
6812 u8 opcode[0x10];
6813 u8 reserved_at_10[0x10];
6814
6815 u8 reserved_at_20[0x10];
6816 u8 op_mod[0x10];
6817
6818 u8 reserved_at_40[0x4];
6819 u8 min_delay[0xc];
6820 u8 int_vector[0x10];
6821
6822 u8 reserved_at_60[0x20];
6823};
6824
6825struct mlx5_ifc_attach_to_mcg_out_bits {
6826 u8 status[0x8];
6827 u8 reserved_at_8[0x18];
6828
6829 u8 syndrome[0x20];
6830
6831 u8 reserved_at_40[0x40];
6832};
6833
6834struct mlx5_ifc_attach_to_mcg_in_bits {
6835 u8 opcode[0x10];
6836 u8 reserved_at_10[0x10];
6837
6838 u8 reserved_at_20[0x10];
6839 u8 op_mod[0x10];
6840
6841 u8 reserved_at_40[0x8];
6842 u8 qpn[0x18];
6843
6844 u8 reserved_at_60[0x20];
6845
6846 u8 multicast_gid[16][0x8];
6847};
6848
6849struct mlx5_ifc_arm_xrq_out_bits {
6850 u8 status[0x8];
6851 u8 reserved_at_8[0x18];
6852
6853 u8 syndrome[0x20];
6854
6855 u8 reserved_at_40[0x40];
6856};
6857
6858struct mlx5_ifc_arm_xrq_in_bits {
6859 u8 opcode[0x10];
6860 u8 reserved_at_10[0x10];
6861
6862 u8 reserved_at_20[0x10];
6863 u8 op_mod[0x10];
6864
6865 u8 reserved_at_40[0x8];
6866 u8 xrqn[0x18];
6867
6868 u8 reserved_at_60[0x10];
6869 u8 lwm[0x10];
6870};
6871
6872struct mlx5_ifc_arm_xrc_srq_out_bits {
6873 u8 status[0x8];
6874 u8 reserved_at_8[0x18];
6875
6876 u8 syndrome[0x20];
6877
6878 u8 reserved_at_40[0x40];
6879};
6880
6881enum {
6882 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6883};
6884
6885struct mlx5_ifc_arm_xrc_srq_in_bits {
6886 u8 opcode[0x10];
6887 u8 reserved_at_10[0x10];
6888
6889 u8 reserved_at_20[0x10];
6890 u8 op_mod[0x10];
6891
6892 u8 reserved_at_40[0x8];
6893 u8 xrc_srqn[0x18];
6894
6895 u8 reserved_at_60[0x10];
6896 u8 lwm[0x10];
6897};
6898
6899struct mlx5_ifc_arm_rq_out_bits {
6900 u8 status[0x8];
6901 u8 reserved_at_8[0x18];
6902
6903 u8 syndrome[0x20];
6904
6905 u8 reserved_at_40[0x40];
6906};
6907
6908enum {
6909 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6910 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6911};
6912
6913struct mlx5_ifc_arm_rq_in_bits {
6914 u8 opcode[0x10];
6915 u8 reserved_at_10[0x10];
6916
6917 u8 reserved_at_20[0x10];
6918 u8 op_mod[0x10];
6919
6920 u8 reserved_at_40[0x8];
6921 u8 srq_number[0x18];
6922
6923 u8 reserved_at_60[0x10];
6924 u8 lwm[0x10];
6925};
6926
6927struct mlx5_ifc_arm_dct_out_bits {
6928 u8 status[0x8];
6929 u8 reserved_at_8[0x18];
6930
6931 u8 syndrome[0x20];
6932
6933 u8 reserved_at_40[0x40];
6934};
6935
6936struct mlx5_ifc_arm_dct_in_bits {
6937 u8 opcode[0x10];
6938 u8 reserved_at_10[0x10];
6939
6940 u8 reserved_at_20[0x10];
6941 u8 op_mod[0x10];
6942
6943 u8 reserved_at_40[0x8];
6944 u8 dct_number[0x18];
6945
6946 u8 reserved_at_60[0x20];
6947};
6948
6949struct mlx5_ifc_alloc_xrcd_out_bits {
6950 u8 status[0x8];
6951 u8 reserved_at_8[0x18];
6952
6953 u8 syndrome[0x20];
6954
6955 u8 reserved_at_40[0x8];
6956 u8 xrcd[0x18];
6957
6958 u8 reserved_at_60[0x20];
6959};
6960
6961struct mlx5_ifc_alloc_xrcd_in_bits {
6962 u8 opcode[0x10];
6963 u8 reserved_at_10[0x10];
6964
6965 u8 reserved_at_20[0x10];
6966 u8 op_mod[0x10];
6967
6968 u8 reserved_at_40[0x40];
6969};
6970
6971struct mlx5_ifc_alloc_uar_out_bits {
6972 u8 status[0x8];
6973 u8 reserved_at_8[0x18];
6974
6975 u8 syndrome[0x20];
6976
6977 u8 reserved_at_40[0x8];
6978 u8 uar[0x18];
6979
6980 u8 reserved_at_60[0x20];
6981};
6982
6983struct mlx5_ifc_alloc_uar_in_bits {
6984 u8 opcode[0x10];
6985 u8 reserved_at_10[0x10];
6986
6987 u8 reserved_at_20[0x10];
6988 u8 op_mod[0x10];
6989
6990 u8 reserved_at_40[0x40];
6991};
6992
6993struct mlx5_ifc_alloc_transport_domain_out_bits {
6994 u8 status[0x8];
6995 u8 reserved_at_8[0x18];
6996
6997 u8 syndrome[0x20];
6998
6999 u8 reserved_at_40[0x8];
7000 u8 transport_domain[0x18];
7001
7002 u8 reserved_at_60[0x20];
7003};
7004
7005struct mlx5_ifc_alloc_transport_domain_in_bits {
7006 u8 opcode[0x10];
7007 u8 reserved_at_10[0x10];
7008
7009 u8 reserved_at_20[0x10];
7010 u8 op_mod[0x10];
7011
7012 u8 reserved_at_40[0x40];
7013};
7014
7015struct mlx5_ifc_alloc_q_counter_out_bits {
7016 u8 status[0x8];
7017 u8 reserved_at_8[0x18];
7018
7019 u8 syndrome[0x20];
7020
7021 u8 reserved_at_40[0x18];
7022 u8 counter_set_id[0x8];
7023
7024 u8 reserved_at_60[0x20];
7025};
7026
7027struct mlx5_ifc_alloc_q_counter_in_bits {
7028 u8 opcode[0x10];
7029 u8 reserved_at_10[0x10];
7030
7031 u8 reserved_at_20[0x10];
7032 u8 op_mod[0x10];
7033
7034 u8 reserved_at_40[0x40];
7035};
7036
7037struct mlx5_ifc_alloc_pd_out_bits {
7038 u8 status[0x8];
7039 u8 reserved_at_8[0x18];
7040
7041 u8 syndrome[0x20];
7042
7043 u8 reserved_at_40[0x8];
7044 u8 pd[0x18];
7045
7046 u8 reserved_at_60[0x20];
7047};
7048
7049struct mlx5_ifc_alloc_pd_in_bits {
7050 u8 opcode[0x10];
7051 u8 reserved_at_10[0x10];
7052
7053 u8 reserved_at_20[0x10];
7054 u8 op_mod[0x10];
7055
7056 u8 reserved_at_40[0x40];
7057};
7058
7059struct mlx5_ifc_alloc_flow_counter_out_bits {
7060 u8 status[0x8];
7061 u8 reserved_at_8[0x18];
7062
7063 u8 syndrome[0x20];
7064
7065 u8 reserved_at_40[0x10];
7066 u8 flow_counter_id[0x10];
7067
7068 u8 reserved_at_60[0x20];
7069};
7070
7071struct mlx5_ifc_alloc_flow_counter_in_bits {
7072 u8 opcode[0x10];
7073 u8 reserved_at_10[0x10];
7074
7075 u8 reserved_at_20[0x10];
7076 u8 op_mod[0x10];
7077
7078 u8 reserved_at_40[0x40];
7079};
7080
7081struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7082 u8 status[0x8];
7083 u8 reserved_at_8[0x18];
7084
7085 u8 syndrome[0x20];
7086
7087 u8 reserved_at_40[0x40];
7088};
7089
7090struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7091 u8 opcode[0x10];
7092 u8 reserved_at_10[0x10];
7093
7094 u8 reserved_at_20[0x10];
7095 u8 op_mod[0x10];
7096
7097 u8 reserved_at_40[0x20];
7098
7099 u8 reserved_at_60[0x10];
7100 u8 vxlan_udp_port[0x10];
7101};
7102
7103struct mlx5_ifc_set_rate_limit_out_bits {
7104 u8 status[0x8];
7105 u8 reserved_at_8[0x18];
7106
7107 u8 syndrome[0x20];
7108
7109 u8 reserved_at_40[0x40];
7110};
7111
7112struct mlx5_ifc_set_rate_limit_in_bits {
7113 u8 opcode[0x10];
7114 u8 reserved_at_10[0x10];
7115
7116 u8 reserved_at_20[0x10];
7117 u8 op_mod[0x10];
7118
7119 u8 reserved_at_40[0x10];
7120 u8 rate_limit_index[0x10];
7121
7122 u8 reserved_at_60[0x20];
7123
7124 u8 rate_limit[0x20];
7125};
7126
7127struct mlx5_ifc_access_register_out_bits {
7128 u8 status[0x8];
7129 u8 reserved_at_8[0x18];
7130
7131 u8 syndrome[0x20];
7132
7133 u8 reserved_at_40[0x40];
7134
7135 u8 register_data[0][0x20];
7136};
7137
7138enum {
7139 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7140 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7141};
7142
7143struct mlx5_ifc_access_register_in_bits {
7144 u8 opcode[0x10];
7145 u8 reserved_at_10[0x10];
7146
7147 u8 reserved_at_20[0x10];
7148 u8 op_mod[0x10];
7149
7150 u8 reserved_at_40[0x10];
7151 u8 register_id[0x10];
7152
7153 u8 argument[0x20];
7154
7155 u8 register_data[0][0x20];
7156};
7157
7158struct mlx5_ifc_sltp_reg_bits {
7159 u8 status[0x4];
7160 u8 version[0x4];
7161 u8 local_port[0x8];
7162 u8 pnat[0x2];
7163 u8 reserved_at_12[0x2];
7164 u8 lane[0x4];
7165 u8 reserved_at_18[0x8];
7166
7167 u8 reserved_at_20[0x20];
7168
7169 u8 reserved_at_40[0x7];
7170 u8 polarity[0x1];
7171 u8 ob_tap0[0x8];
7172 u8 ob_tap1[0x8];
7173 u8 ob_tap2[0x8];
7174
7175 u8 reserved_at_60[0xc];
7176 u8 ob_preemp_mode[0x4];
7177 u8 ob_reg[0x8];
7178 u8 ob_bias[0x8];
7179
7180 u8 reserved_at_80[0x20];
7181};
7182
7183struct mlx5_ifc_slrg_reg_bits {
7184 u8 status[0x4];
7185 u8 version[0x4];
7186 u8 local_port[0x8];
7187 u8 pnat[0x2];
7188 u8 reserved_at_12[0x2];
7189 u8 lane[0x4];
7190 u8 reserved_at_18[0x8];
7191
7192 u8 time_to_link_up[0x10];
7193 u8 reserved_at_30[0xc];
7194 u8 grade_lane_speed[0x4];
7195
7196 u8 grade_version[0x8];
7197 u8 grade[0x18];
7198
7199 u8 reserved_at_60[0x4];
7200 u8 height_grade_type[0x4];
7201 u8 height_grade[0x18];
7202
7203 u8 height_dz[0x10];
7204 u8 height_dv[0x10];
7205
7206 u8 reserved_at_a0[0x10];
7207 u8 height_sigma[0x10];
7208
7209 u8 reserved_at_c0[0x20];
7210
7211 u8 reserved_at_e0[0x4];
7212 u8 phase_grade_type[0x4];
7213 u8 phase_grade[0x18];
7214
7215 u8 reserved_at_100[0x8];
7216 u8 phase_eo_pos[0x8];
7217 u8 reserved_at_110[0x8];
7218 u8 phase_eo_neg[0x8];
7219
7220 u8 ffe_set_tested[0x10];
7221 u8 test_errors_per_lane[0x10];
7222};
7223
7224struct mlx5_ifc_pvlc_reg_bits {
7225 u8 reserved_at_0[0x8];
7226 u8 local_port[0x8];
7227 u8 reserved_at_10[0x10];
7228
7229 u8 reserved_at_20[0x1c];
7230 u8 vl_hw_cap[0x4];
7231
7232 u8 reserved_at_40[0x1c];
7233 u8 vl_admin[0x4];
7234
7235 u8 reserved_at_60[0x1c];
7236 u8 vl_operational[0x4];
7237};
7238
7239struct mlx5_ifc_pude_reg_bits {
7240 u8 swid[0x8];
7241 u8 local_port[0x8];
7242 u8 reserved_at_10[0x4];
7243 u8 admin_status[0x4];
7244 u8 reserved_at_18[0x4];
7245 u8 oper_status[0x4];
7246
7247 u8 reserved_at_20[0x60];
7248};
7249
7250struct mlx5_ifc_ptys_reg_bits {
7251 u8 reserved_at_0[0x1];
7252 u8 an_disable_admin[0x1];
7253 u8 an_disable_cap[0x1];
7254 u8 reserved_at_3[0x5];
7255 u8 local_port[0x8];
7256 u8 reserved_at_10[0xd];
7257 u8 proto_mask[0x3];
7258
7259 u8 an_status[0x4];
7260 u8 reserved_at_24[0x3c];
7261
7262 u8 eth_proto_capability[0x20];
7263
7264 u8 ib_link_width_capability[0x10];
7265 u8 ib_proto_capability[0x10];
7266
7267 u8 reserved_at_a0[0x20];
7268
7269 u8 eth_proto_admin[0x20];
7270
7271 u8 ib_link_width_admin[0x10];
7272 u8 ib_proto_admin[0x10];
7273
7274 u8 reserved_at_100[0x20];
7275
7276 u8 eth_proto_oper[0x20];
7277
7278 u8 ib_link_width_oper[0x10];
7279 u8 ib_proto_oper[0x10];
7280
7281 u8 reserved_at_160[0x20];
7282
7283 u8 eth_proto_lp_advertise[0x20];
7284
7285 u8 reserved_at_1a0[0x60];
7286};
7287
7288struct mlx5_ifc_mlcr_reg_bits {
7289 u8 reserved_at_0[0x8];
7290 u8 local_port[0x8];
7291 u8 reserved_at_10[0x20];
7292
7293 u8 beacon_duration[0x10];
7294 u8 reserved_at_40[0x10];
7295
7296 u8 beacon_remain[0x10];
7297};
7298
7299struct mlx5_ifc_ptas_reg_bits {
7300 u8 reserved_at_0[0x20];
7301
7302 u8 algorithm_options[0x10];
7303 u8 reserved_at_30[0x4];
7304 u8 repetitions_mode[0x4];
7305 u8 num_of_repetitions[0x8];
7306
7307 u8 grade_version[0x8];
7308 u8 height_grade_type[0x4];
7309 u8 phase_grade_type[0x4];
7310 u8 height_grade_weight[0x8];
7311 u8 phase_grade_weight[0x8];
7312
7313 u8 gisim_measure_bits[0x10];
7314 u8 adaptive_tap_measure_bits[0x10];
7315
7316 u8 ber_bath_high_error_threshold[0x10];
7317 u8 ber_bath_mid_error_threshold[0x10];
7318
7319 u8 ber_bath_low_error_threshold[0x10];
7320 u8 one_ratio_high_threshold[0x10];
7321
7322 u8 one_ratio_high_mid_threshold[0x10];
7323 u8 one_ratio_low_mid_threshold[0x10];
7324
7325 u8 one_ratio_low_threshold[0x10];
7326 u8 ndeo_error_threshold[0x10];
7327
7328 u8 mixer_offset_step_size[0x10];
7329 u8 reserved_at_110[0x8];
7330 u8 mix90_phase_for_voltage_bath[0x8];
7331
7332 u8 mixer_offset_start[0x10];
7333 u8 mixer_offset_end[0x10];
7334
7335 u8 reserved_at_140[0x15];
7336 u8 ber_test_time[0xb];
7337};
7338
7339struct mlx5_ifc_pspa_reg_bits {
7340 u8 swid[0x8];
7341 u8 local_port[0x8];
7342 u8 sub_port[0x8];
7343 u8 reserved_at_18[0x8];
7344
7345 u8 reserved_at_20[0x20];
7346};
7347
7348struct mlx5_ifc_pqdr_reg_bits {
7349 u8 reserved_at_0[0x8];
7350 u8 local_port[0x8];
7351 u8 reserved_at_10[0x5];
7352 u8 prio[0x3];
7353 u8 reserved_at_18[0x6];
7354 u8 mode[0x2];
7355
7356 u8 reserved_at_20[0x20];
7357
7358 u8 reserved_at_40[0x10];
7359 u8 min_threshold[0x10];
7360
7361 u8 reserved_at_60[0x10];
7362 u8 max_threshold[0x10];
7363
7364 u8 reserved_at_80[0x10];
7365 u8 mark_probability_denominator[0x10];
7366
7367 u8 reserved_at_a0[0x60];
7368};
7369
7370struct mlx5_ifc_ppsc_reg_bits {
7371 u8 reserved_at_0[0x8];
7372 u8 local_port[0x8];
7373 u8 reserved_at_10[0x10];
7374
7375 u8 reserved_at_20[0x60];
7376
7377 u8 reserved_at_80[0x1c];
7378 u8 wrps_admin[0x4];
7379
7380 u8 reserved_at_a0[0x1c];
7381 u8 wrps_status[0x4];
7382
7383 u8 reserved_at_c0[0x8];
7384 u8 up_threshold[0x8];
7385 u8 reserved_at_d0[0x8];
7386 u8 down_threshold[0x8];
7387
7388 u8 reserved_at_e0[0x20];
7389
7390 u8 reserved_at_100[0x1c];
7391 u8 srps_admin[0x4];
7392
7393 u8 reserved_at_120[0x1c];
7394 u8 srps_status[0x4];
7395
7396 u8 reserved_at_140[0x40];
7397};
7398
7399struct mlx5_ifc_pplr_reg_bits {
7400 u8 reserved_at_0[0x8];
7401 u8 local_port[0x8];
7402 u8 reserved_at_10[0x10];
7403
7404 u8 reserved_at_20[0x8];
7405 u8 lb_cap[0x8];
7406 u8 reserved_at_30[0x8];
7407 u8 lb_en[0x8];
7408};
7409
7410struct mlx5_ifc_pplm_reg_bits {
7411 u8 reserved_at_0[0x8];
7412 u8 local_port[0x8];
7413 u8 reserved_at_10[0x10];
7414
7415 u8 reserved_at_20[0x20];
7416
7417 u8 port_profile_mode[0x8];
7418 u8 static_port_profile[0x8];
7419 u8 active_port_profile[0x8];
7420 u8 reserved_at_58[0x8];
7421
7422 u8 retransmission_active[0x8];
7423 u8 fec_mode_active[0x18];
7424
7425 u8 reserved_at_80[0x20];
7426};
7427
7428struct mlx5_ifc_ppcnt_reg_bits {
7429 u8 swid[0x8];
7430 u8 local_port[0x8];
7431 u8 pnat[0x2];
7432 u8 reserved_at_12[0x8];
7433 u8 grp[0x6];
7434
7435 u8 clr[0x1];
7436 u8 reserved_at_21[0x1c];
7437 u8 prio_tc[0x3];
7438
7439 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7440};
7441
7442struct mlx5_ifc_mpcnt_reg_bits {
7443 u8 reserved_at_0[0x8];
7444 u8 pcie_index[0x8];
7445 u8 reserved_at_10[0xa];
7446 u8 grp[0x6];
7447
7448 u8 clr[0x1];
7449 u8 reserved_at_21[0x1f];
7450
7451 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7452};
7453
7454struct mlx5_ifc_ppad_reg_bits {
7455 u8 reserved_at_0[0x3];
7456 u8 single_mac[0x1];
7457 u8 reserved_at_4[0x4];
7458 u8 local_port[0x8];
7459 u8 mac_47_32[0x10];
7460
7461 u8 mac_31_0[0x20];
7462
7463 u8 reserved_at_40[0x40];
7464};
7465
7466struct mlx5_ifc_pmtu_reg_bits {
7467 u8 reserved_at_0[0x8];
7468 u8 local_port[0x8];
7469 u8 reserved_at_10[0x10];
7470
7471 u8 max_mtu[0x10];
7472 u8 reserved_at_30[0x10];
7473
7474 u8 admin_mtu[0x10];
7475 u8 reserved_at_50[0x10];
7476
7477 u8 oper_mtu[0x10];
7478 u8 reserved_at_70[0x10];
7479};
7480
7481struct mlx5_ifc_pmpr_reg_bits {
7482 u8 reserved_at_0[0x8];
7483 u8 module[0x8];
7484 u8 reserved_at_10[0x10];
7485
7486 u8 reserved_at_20[0x18];
7487 u8 attenuation_5g[0x8];
7488
7489 u8 reserved_at_40[0x18];
7490 u8 attenuation_7g[0x8];
7491
7492 u8 reserved_at_60[0x18];
7493 u8 attenuation_12g[0x8];
7494};
7495
7496struct mlx5_ifc_pmpe_reg_bits {
7497 u8 reserved_at_0[0x8];
7498 u8 module[0x8];
7499 u8 reserved_at_10[0xc];
7500 u8 module_status[0x4];
7501
7502 u8 reserved_at_20[0x60];
7503};
7504
7505struct mlx5_ifc_pmpc_reg_bits {
7506 u8 module_state_updated[32][0x8];
7507};
7508
7509struct mlx5_ifc_pmlpn_reg_bits {
7510 u8 reserved_at_0[0x4];
7511 u8 mlpn_status[0x4];
7512 u8 local_port[0x8];
7513 u8 reserved_at_10[0x10];
7514
7515 u8 e[0x1];
7516 u8 reserved_at_21[0x1f];
7517};
7518
7519struct mlx5_ifc_pmlp_reg_bits {
7520 u8 rxtx[0x1];
7521 u8 reserved_at_1[0x7];
7522 u8 local_port[0x8];
7523 u8 reserved_at_10[0x8];
7524 u8 width[0x8];
7525
7526 u8 lane0_module_mapping[0x20];
7527
7528 u8 lane1_module_mapping[0x20];
7529
7530 u8 lane2_module_mapping[0x20];
7531
7532 u8 lane3_module_mapping[0x20];
7533
7534 u8 reserved_at_a0[0x160];
7535};
7536
7537struct mlx5_ifc_pmaos_reg_bits {
7538 u8 reserved_at_0[0x8];
7539 u8 module[0x8];
7540 u8 reserved_at_10[0x4];
7541 u8 admin_status[0x4];
7542 u8 reserved_at_18[0x4];
7543 u8 oper_status[0x4];
7544
7545 u8 ase[0x1];
7546 u8 ee[0x1];
7547 u8 reserved_at_22[0x1c];
7548 u8 e[0x2];
7549
7550 u8 reserved_at_40[0x40];
7551};
7552
7553struct mlx5_ifc_plpc_reg_bits {
7554 u8 reserved_at_0[0x4];
7555 u8 profile_id[0xc];
7556 u8 reserved_at_10[0x4];
7557 u8 proto_mask[0x4];
7558 u8 reserved_at_18[0x8];
7559
7560 u8 reserved_at_20[0x10];
7561 u8 lane_speed[0x10];
7562
7563 u8 reserved_at_40[0x17];
7564 u8 lpbf[0x1];
7565 u8 fec_mode_policy[0x8];
7566
7567 u8 retransmission_capability[0x8];
7568 u8 fec_mode_capability[0x18];
7569
7570 u8 retransmission_support_admin[0x8];
7571 u8 fec_mode_support_admin[0x18];
7572
7573 u8 retransmission_request_admin[0x8];
7574 u8 fec_mode_request_admin[0x18];
7575
7576 u8 reserved_at_c0[0x80];
7577};
7578
7579struct mlx5_ifc_plib_reg_bits {
7580 u8 reserved_at_0[0x8];
7581 u8 local_port[0x8];
7582 u8 reserved_at_10[0x8];
7583 u8 ib_port[0x8];
7584
7585 u8 reserved_at_20[0x60];
7586};
7587
7588struct mlx5_ifc_plbf_reg_bits {
7589 u8 reserved_at_0[0x8];
7590 u8 local_port[0x8];
7591 u8 reserved_at_10[0xd];
7592 u8 lbf_mode[0x3];
7593
7594 u8 reserved_at_20[0x20];
7595};
7596
7597struct mlx5_ifc_pipg_reg_bits {
7598 u8 reserved_at_0[0x8];
7599 u8 local_port[0x8];
7600 u8 reserved_at_10[0x10];
7601
7602 u8 dic[0x1];
7603 u8 reserved_at_21[0x19];
7604 u8 ipg[0x4];
7605 u8 reserved_at_3e[0x2];
7606};
7607
7608struct mlx5_ifc_pifr_reg_bits {
7609 u8 reserved_at_0[0x8];
7610 u8 local_port[0x8];
7611 u8 reserved_at_10[0x10];
7612
7613 u8 reserved_at_20[0xe0];
7614
7615 u8 port_filter[8][0x20];
7616
7617 u8 port_filter_update_en[8][0x20];
7618};
7619
7620struct mlx5_ifc_pfcc_reg_bits {
7621 u8 reserved_at_0[0x8];
7622 u8 local_port[0x8];
7623 u8 reserved_at_10[0x10];
7624
7625 u8 ppan[0x4];
7626 u8 reserved_at_24[0x4];
7627 u8 prio_mask_tx[0x8];
7628 u8 reserved_at_30[0x8];
7629 u8 prio_mask_rx[0x8];
7630
7631 u8 pptx[0x1];
7632 u8 aptx[0x1];
7633 u8 reserved_at_42[0x6];
7634 u8 pfctx[0x8];
7635 u8 reserved_at_50[0x10];
7636
7637 u8 pprx[0x1];
7638 u8 aprx[0x1];
7639 u8 reserved_at_62[0x6];
7640 u8 pfcrx[0x8];
7641 u8 reserved_at_70[0x10];
7642
7643 u8 reserved_at_80[0x80];
7644};
7645
7646struct mlx5_ifc_pelc_reg_bits {
7647 u8 op[0x4];
7648 u8 reserved_at_4[0x4];
7649 u8 local_port[0x8];
7650 u8 reserved_at_10[0x10];
7651
7652 u8 op_admin[0x8];
7653 u8 op_capability[0x8];
7654 u8 op_request[0x8];
7655 u8 op_active[0x8];
7656
7657 u8 admin[0x40];
7658
7659 u8 capability[0x40];
7660
7661 u8 request[0x40];
7662
7663 u8 active[0x40];
7664
7665 u8 reserved_at_140[0x80];
7666};
7667
7668struct mlx5_ifc_peir_reg_bits {
7669 u8 reserved_at_0[0x8];
7670 u8 local_port[0x8];
7671 u8 reserved_at_10[0x10];
7672
7673 u8 reserved_at_20[0xc];
7674 u8 error_count[0x4];
7675 u8 reserved_at_30[0x10];
7676
7677 u8 reserved_at_40[0xc];
7678 u8 lane[0x4];
7679 u8 reserved_at_50[0x8];
7680 u8 error_type[0x8];
7681};
7682
7683struct mlx5_ifc_pcam_enhanced_features_bits {
7684 u8 reserved_at_0[0x7e];
7685
7686 u8 ppcnt_discard_group[0x1];
7687 u8 ppcnt_statistical_group[0x1];
7688};
7689
7690struct mlx5_ifc_pcam_reg_bits {
7691 u8 reserved_at_0[0x8];
7692 u8 feature_group[0x8];
7693 u8 reserved_at_10[0x8];
7694 u8 access_reg_group[0x8];
7695
7696 u8 reserved_at_20[0x20];
7697
7698 union {
7699 u8 reserved_at_0[0x80];
7700 } port_access_reg_cap_mask;
7701
7702 u8 reserved_at_c0[0x80];
7703
7704 union {
7705 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7706 u8 reserved_at_0[0x80];
7707 } feature_cap_mask;
7708
7709 u8 reserved_at_1c0[0xc0];
7710};
7711
7712struct mlx5_ifc_mcam_enhanced_features_bits {
7713 u8 reserved_at_0[0x7f];
7714
7715 u8 pcie_performance_group[0x1];
7716};
7717
7718struct mlx5_ifc_mcam_reg_bits {
7719 u8 reserved_at_0[0x8];
7720 u8 feature_group[0x8];
7721 u8 reserved_at_10[0x8];
7722 u8 access_reg_group[0x8];
7723
7724 u8 reserved_at_20[0x20];
7725
7726 union {
7727 u8 reserved_at_0[0x80];
7728 } mng_access_reg_cap_mask;
7729
7730 u8 reserved_at_c0[0x80];
7731
7732 union {
7733 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7734 u8 reserved_at_0[0x80];
7735 } mng_feature_cap_mask;
7736
7737 u8 reserved_at_1c0[0x80];
7738};
7739
7740struct mlx5_ifc_pcap_reg_bits {
7741 u8 reserved_at_0[0x8];
7742 u8 local_port[0x8];
7743 u8 reserved_at_10[0x10];
7744
7745 u8 port_capability_mask[4][0x20];
7746};
7747
7748struct mlx5_ifc_paos_reg_bits {
7749 u8 swid[0x8];
7750 u8 local_port[0x8];
7751 u8 reserved_at_10[0x4];
7752 u8 admin_status[0x4];
7753 u8 reserved_at_18[0x4];
7754 u8 oper_status[0x4];
7755
7756 u8 ase[0x1];
7757 u8 ee[0x1];
7758 u8 reserved_at_22[0x1c];
7759 u8 e[0x2];
7760
7761 u8 reserved_at_40[0x40];
7762};
7763
7764struct mlx5_ifc_pamp_reg_bits {
7765 u8 reserved_at_0[0x8];
7766 u8 opamp_group[0x8];
7767 u8 reserved_at_10[0xc];
7768 u8 opamp_group_type[0x4];
7769
7770 u8 start_index[0x10];
7771 u8 reserved_at_30[0x4];
7772 u8 num_of_indices[0xc];
7773
7774 u8 index_data[18][0x10];
7775};
7776
7777struct mlx5_ifc_pcmr_reg_bits {
7778 u8 reserved_at_0[0x8];
7779 u8 local_port[0x8];
7780 u8 reserved_at_10[0x2e];
7781 u8 fcs_cap[0x1];
7782 u8 reserved_at_3f[0x1f];
7783 u8 fcs_chk[0x1];
7784 u8 reserved_at_5f[0x1];
7785};
7786
7787struct mlx5_ifc_lane_2_module_mapping_bits {
7788 u8 reserved_at_0[0x6];
7789 u8 rx_lane[0x2];
7790 u8 reserved_at_8[0x6];
7791 u8 tx_lane[0x2];
7792 u8 reserved_at_10[0x8];
7793 u8 module[0x8];
7794};
7795
7796struct mlx5_ifc_bufferx_reg_bits {
7797 u8 reserved_at_0[0x6];
7798 u8 lossy[0x1];
7799 u8 epsb[0x1];
7800 u8 reserved_at_8[0xc];
7801 u8 size[0xc];
7802
7803 u8 xoff_threshold[0x10];
7804 u8 xon_threshold[0x10];
7805};
7806
7807struct mlx5_ifc_set_node_in_bits {
7808 u8 node_description[64][0x8];
7809};
7810
7811struct mlx5_ifc_register_power_settings_bits {
7812 u8 reserved_at_0[0x18];
7813 u8 power_settings_level[0x8];
7814
7815 u8 reserved_at_20[0x60];
7816};
7817
7818struct mlx5_ifc_register_host_endianness_bits {
7819 u8 he[0x1];
7820 u8 reserved_at_1[0x1f];
7821
7822 u8 reserved_at_20[0x60];
7823};
7824
7825struct mlx5_ifc_umr_pointer_desc_argument_bits {
7826 u8 reserved_at_0[0x20];
7827
7828 u8 mkey[0x20];
7829
7830 u8 addressh_63_32[0x20];
7831
7832 u8 addressl_31_0[0x20];
7833};
7834
7835struct mlx5_ifc_ud_adrs_vector_bits {
7836 u8 dc_key[0x40];
7837
7838 u8 ext[0x1];
7839 u8 reserved_at_41[0x7];
7840 u8 destination_qp_dct[0x18];
7841
7842 u8 static_rate[0x4];
7843 u8 sl_eth_prio[0x4];
7844 u8 fl[0x1];
7845 u8 mlid[0x7];
7846 u8 rlid_udp_sport[0x10];
7847
7848 u8 reserved_at_80[0x20];
7849
7850 u8 rmac_47_16[0x20];
7851
7852 u8 rmac_15_0[0x10];
7853 u8 tclass[0x8];
7854 u8 hop_limit[0x8];
7855
7856 u8 reserved_at_e0[0x1];
7857 u8 grh[0x1];
7858 u8 reserved_at_e2[0x2];
7859 u8 src_addr_index[0x8];
7860 u8 flow_label[0x14];
7861
7862 u8 rgid_rip[16][0x8];
7863};
7864
7865struct mlx5_ifc_pages_req_event_bits {
7866 u8 reserved_at_0[0x10];
7867 u8 function_id[0x10];
7868
7869 u8 num_pages[0x20];
7870
7871 u8 reserved_at_40[0xa0];
7872};
7873
7874struct mlx5_ifc_eqe_bits {
7875 u8 reserved_at_0[0x8];
7876 u8 event_type[0x8];
7877 u8 reserved_at_10[0x8];
7878 u8 event_sub_type[0x8];
7879
7880 u8 reserved_at_20[0xe0];
7881
7882 union mlx5_ifc_event_auto_bits event_data;
7883
7884 u8 reserved_at_1e0[0x10];
7885 u8 signature[0x8];
7886 u8 reserved_at_1f8[0x7];
7887 u8 owner[0x1];
7888};
7889
7890enum {
7891 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7892};
7893
7894struct mlx5_ifc_cmd_queue_entry_bits {
7895 u8 type[0x8];
7896 u8 reserved_at_8[0x18];
7897
7898 u8 input_length[0x20];
7899
7900 u8 input_mailbox_pointer_63_32[0x20];
7901
7902 u8 input_mailbox_pointer_31_9[0x17];
7903 u8 reserved_at_77[0x9];
7904
7905 u8 command_input_inline_data[16][0x8];
7906
7907 u8 command_output_inline_data[16][0x8];
7908
7909 u8 output_mailbox_pointer_63_32[0x20];
7910
7911 u8 output_mailbox_pointer_31_9[0x17];
7912 u8 reserved_at_1b7[0x9];
7913
7914 u8 output_length[0x20];
7915
7916 u8 token[0x8];
7917 u8 signature[0x8];
7918 u8 reserved_at_1f0[0x8];
7919 u8 status[0x7];
7920 u8 ownership[0x1];
7921};
7922
7923struct mlx5_ifc_cmd_out_bits {
7924 u8 status[0x8];
7925 u8 reserved_at_8[0x18];
7926
7927 u8 syndrome[0x20];
7928
7929 u8 command_output[0x20];
7930};
7931
7932struct mlx5_ifc_cmd_in_bits {
7933 u8 opcode[0x10];
7934 u8 reserved_at_10[0x10];
7935
7936 u8 reserved_at_20[0x10];
7937 u8 op_mod[0x10];
7938
7939 u8 command[0][0x20];
7940};
7941
7942struct mlx5_ifc_cmd_if_box_bits {
7943 u8 mailbox_data[512][0x8];
7944
7945 u8 reserved_at_1000[0x180];
7946
7947 u8 next_pointer_63_32[0x20];
7948
7949 u8 next_pointer_31_10[0x16];
7950 u8 reserved_at_11b6[0xa];
7951
7952 u8 block_number[0x20];
7953
7954 u8 reserved_at_11e0[0x8];
7955 u8 token[0x8];
7956 u8 ctrl_signature[0x8];
7957 u8 signature[0x8];
7958};
7959
7960struct mlx5_ifc_mtt_bits {
7961 u8 ptag_63_32[0x20];
7962
7963 u8 ptag_31_8[0x18];
7964 u8 reserved_at_38[0x6];
7965 u8 wr_en[0x1];
7966 u8 rd_en[0x1];
7967};
7968
7969struct mlx5_ifc_query_wol_rol_out_bits {
7970 u8 status[0x8];
7971 u8 reserved_at_8[0x18];
7972
7973 u8 syndrome[0x20];
7974
7975 u8 reserved_at_40[0x10];
7976 u8 rol_mode[0x8];
7977 u8 wol_mode[0x8];
7978
7979 u8 reserved_at_60[0x20];
7980};
7981
7982struct mlx5_ifc_query_wol_rol_in_bits {
7983 u8 opcode[0x10];
7984 u8 reserved_at_10[0x10];
7985
7986 u8 reserved_at_20[0x10];
7987 u8 op_mod[0x10];
7988
7989 u8 reserved_at_40[0x40];
7990};
7991
7992struct mlx5_ifc_set_wol_rol_out_bits {
7993 u8 status[0x8];
7994 u8 reserved_at_8[0x18];
7995
7996 u8 syndrome[0x20];
7997
7998 u8 reserved_at_40[0x40];
7999};
8000
8001struct mlx5_ifc_set_wol_rol_in_bits {
8002 u8 opcode[0x10];
8003 u8 reserved_at_10[0x10];
8004
8005 u8 reserved_at_20[0x10];
8006 u8 op_mod[0x10];
8007
8008 u8 rol_mode_valid[0x1];
8009 u8 wol_mode_valid[0x1];
8010 u8 reserved_at_42[0xe];
8011 u8 rol_mode[0x8];
8012 u8 wol_mode[0x8];
8013
8014 u8 reserved_at_60[0x20];
8015};
8016
8017enum {
8018 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8019 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8020 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8021};
8022
8023enum {
8024 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8025 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8026 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8027};
8028
8029enum {
8030 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8031 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8032 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8033 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8034 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8035 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8036 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8037 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8038 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8039 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8040 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8041};
8042
8043struct mlx5_ifc_initial_seg_bits {
8044 u8 fw_rev_minor[0x10];
8045 u8 fw_rev_major[0x10];
8046
8047 u8 cmd_interface_rev[0x10];
8048 u8 fw_rev_subminor[0x10];
8049
8050 u8 reserved_at_40[0x40];
8051
8052 u8 cmdq_phy_addr_63_32[0x20];
8053
8054 u8 cmdq_phy_addr_31_12[0x14];
8055 u8 reserved_at_b4[0x2];
8056 u8 nic_interface[0x2];
8057 u8 log_cmdq_size[0x4];
8058 u8 log_cmdq_stride[0x4];
8059
8060 u8 command_doorbell_vector[0x20];
8061
8062 u8 reserved_at_e0[0xf00];
8063
8064 u8 initializing[0x1];
8065 u8 reserved_at_fe1[0x4];
8066 u8 nic_interface_supported[0x3];
8067 u8 reserved_at_fe8[0x18];
8068
8069 struct mlx5_ifc_health_buffer_bits health_buffer;
8070
8071 u8 no_dram_nic_offset[0x20];
8072
8073 u8 reserved_at_1220[0x6e40];
8074
8075 u8 reserved_at_8060[0x1f];
8076 u8 clear_int[0x1];
8077
8078 u8 health_syndrome[0x8];
8079 u8 health_counter[0x18];
8080
8081 u8 reserved_at_80a0[0x17fc0];
8082};
8083
8084struct mlx5_ifc_mtpps_reg_bits {
8085 u8 reserved_at_0[0xc];
8086 u8 cap_number_of_pps_pins[0x4];
8087 u8 reserved_at_10[0x4];
8088 u8 cap_max_num_of_pps_in_pins[0x4];
8089 u8 reserved_at_18[0x4];
8090 u8 cap_max_num_of_pps_out_pins[0x4];
8091
8092 u8 reserved_at_20[0x24];
8093 u8 cap_pin_3_mode[0x4];
8094 u8 reserved_at_48[0x4];
8095 u8 cap_pin_2_mode[0x4];
8096 u8 reserved_at_50[0x4];
8097 u8 cap_pin_1_mode[0x4];
8098 u8 reserved_at_58[0x4];
8099 u8 cap_pin_0_mode[0x4];
8100
8101 u8 reserved_at_60[0x4];
8102 u8 cap_pin_7_mode[0x4];
8103 u8 reserved_at_68[0x4];
8104 u8 cap_pin_6_mode[0x4];
8105 u8 reserved_at_70[0x4];
8106 u8 cap_pin_5_mode[0x4];
8107 u8 reserved_at_78[0x4];
8108 u8 cap_pin_4_mode[0x4];
8109
8110 u8 reserved_at_80[0x80];
8111
8112 u8 enable[0x1];
8113 u8 reserved_at_101[0xb];
8114 u8 pattern[0x4];
8115 u8 reserved_at_110[0x4];
8116 u8 pin_mode[0x4];
8117 u8 pin[0x8];
8118
8119 u8 reserved_at_120[0x20];
8120
8121 u8 time_stamp[0x40];
8122
8123 u8 out_pulse_duration[0x10];
8124 u8 out_periodic_adjustment[0x10];
8125
8126 u8 reserved_at_1a0[0x60];
8127};
8128
8129struct mlx5_ifc_mtppse_reg_bits {
8130 u8 reserved_at_0[0x18];
8131 u8 pin[0x8];
8132 u8 event_arm[0x1];
8133 u8 reserved_at_21[0x1b];
8134 u8 event_generation_mode[0x4];
8135 u8 reserved_at_40[0x40];
8136};
8137
8138union mlx5_ifc_ports_control_registers_document_bits {
8139 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8140 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8141 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8142 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8143 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8144 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8145 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8146 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8147 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8148 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8149 struct mlx5_ifc_paos_reg_bits paos_reg;
8150 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8151 struct mlx5_ifc_peir_reg_bits peir_reg;
8152 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8153 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8154 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8155 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8156 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8157 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8158 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8159 struct mlx5_ifc_plib_reg_bits plib_reg;
8160 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8161 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8162 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8163 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8164 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8165 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8166 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8167 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8168 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8169 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8170 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8171 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8172 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8173 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8174 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8175 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8176 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8177 struct mlx5_ifc_ptys_reg_bits ptys_reg;
8178 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8179 struct mlx5_ifc_pude_reg_bits pude_reg;
8180 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8181 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8182 struct mlx5_ifc_sltp_reg_bits sltp_reg;
8183 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8184 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8185 u8 reserved_at_0[0x60e0];
8186};
8187
8188union mlx5_ifc_debug_enhancements_document_bits {
8189 struct mlx5_ifc_health_buffer_bits health_buffer;
8190 u8 reserved_at_0[0x200];
8191};
8192
8193union mlx5_ifc_uplink_pci_interface_document_bits {
8194 struct mlx5_ifc_initial_seg_bits initial_seg;
8195 u8 reserved_at_0[0x20060];
8196};
8197
8198struct mlx5_ifc_set_flow_table_root_out_bits {
8199 u8 status[0x8];
8200 u8 reserved_at_8[0x18];
8201
8202 u8 syndrome[0x20];
8203
8204 u8 reserved_at_40[0x40];
8205};
8206
8207struct mlx5_ifc_set_flow_table_root_in_bits {
8208 u8 opcode[0x10];
8209 u8 reserved_at_10[0x10];
8210
8211 u8 reserved_at_20[0x10];
8212 u8 op_mod[0x10];
8213
8214 u8 other_vport[0x1];
8215 u8 reserved_at_41[0xf];
8216 u8 vport_number[0x10];
8217
8218 u8 reserved_at_60[0x20];
8219
8220 u8 table_type[0x8];
8221 u8 reserved_at_88[0x18];
8222
8223 u8 reserved_at_a0[0x8];
8224 u8 table_id[0x18];
8225
8226 u8 reserved_at_c0[0x8];
8227 u8 underlay_qpn[0x18];
8228 u8 reserved_at_e0[0x120];
8229};
8230
8231enum {
8232 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8233 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8234};
8235
8236struct mlx5_ifc_modify_flow_table_out_bits {
8237 u8 status[0x8];
8238 u8 reserved_at_8[0x18];
8239
8240 u8 syndrome[0x20];
8241
8242 u8 reserved_at_40[0x40];
8243};
8244
8245struct mlx5_ifc_modify_flow_table_in_bits {
8246 u8 opcode[0x10];
8247 u8 reserved_at_10[0x10];
8248
8249 u8 reserved_at_20[0x10];
8250 u8 op_mod[0x10];
8251
8252 u8 other_vport[0x1];
8253 u8 reserved_at_41[0xf];
8254 u8 vport_number[0x10];
8255
8256 u8 reserved_at_60[0x10];
8257 u8 modify_field_select[0x10];
8258
8259 u8 table_type[0x8];
8260 u8 reserved_at_88[0x18];
8261
8262 u8 reserved_at_a0[0x8];
8263 u8 table_id[0x18];
8264
8265 u8 reserved_at_c0[0x4];
8266 u8 table_miss_mode[0x4];
8267 u8 reserved_at_c8[0x18];
8268
8269 u8 reserved_at_e0[0x8];
8270 u8 table_miss_id[0x18];
8271
8272 u8 reserved_at_100[0x8];
8273 u8 lag_master_next_table_id[0x18];
8274
8275 u8 reserved_at_120[0x80];
8276};
8277
8278struct mlx5_ifc_ets_tcn_config_reg_bits {
8279 u8 g[0x1];
8280 u8 b[0x1];
8281 u8 r[0x1];
8282 u8 reserved_at_3[0x9];
8283 u8 group[0x4];
8284 u8 reserved_at_10[0x9];
8285 u8 bw_allocation[0x7];
8286
8287 u8 reserved_at_20[0xc];
8288 u8 max_bw_units[0x4];
8289 u8 reserved_at_30[0x8];
8290 u8 max_bw_value[0x8];
8291};
8292
8293struct mlx5_ifc_ets_global_config_reg_bits {
8294 u8 reserved_at_0[0x2];
8295 u8 r[0x1];
8296 u8 reserved_at_3[0x1d];
8297
8298 u8 reserved_at_20[0xc];
8299 u8 max_bw_units[0x4];
8300 u8 reserved_at_30[0x8];
8301 u8 max_bw_value[0x8];
8302};
8303
8304struct mlx5_ifc_qetc_reg_bits {
8305 u8 reserved_at_0[0x8];
8306 u8 port_number[0x8];
8307 u8 reserved_at_10[0x30];
8308
8309 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8310 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8311};
8312
8313struct mlx5_ifc_qtct_reg_bits {
8314 u8 reserved_at_0[0x8];
8315 u8 port_number[0x8];
8316 u8 reserved_at_10[0xd];
8317 u8 prio[0x3];
8318
8319 u8 reserved_at_20[0x1d];
8320 u8 tclass[0x3];
8321};
8322
8323struct mlx5_ifc_mcia_reg_bits {
8324 u8 l[0x1];
8325 u8 reserved_at_1[0x7];
8326 u8 module[0x8];
8327 u8 reserved_at_10[0x8];
8328 u8 status[0x8];
8329
8330 u8 i2c_device_address[0x8];
8331 u8 page_number[0x8];
8332 u8 device_address[0x10];
8333
8334 u8 reserved_at_40[0x10];
8335 u8 size[0x10];
8336
8337 u8 reserved_at_60[0x20];
8338
8339 u8 dword_0[0x20];
8340 u8 dword_1[0x20];
8341 u8 dword_2[0x20];
8342 u8 dword_3[0x20];
8343 u8 dword_4[0x20];
8344 u8 dword_5[0x20];
8345 u8 dword_6[0x20];
8346 u8 dword_7[0x20];
8347 u8 dword_8[0x20];
8348 u8 dword_9[0x20];
8349 u8 dword_10[0x20];
8350 u8 dword_11[0x20];
8351};
8352
8353struct mlx5_ifc_dcbx_param_bits {
8354 u8 dcbx_cee_cap[0x1];
8355 u8 dcbx_ieee_cap[0x1];
8356 u8 dcbx_standby_cap[0x1];
8357 u8 reserved_at_0[0x5];
8358 u8 port_number[0x8];
8359 u8 reserved_at_10[0xa];
8360 u8 max_application_table_size[6];
8361 u8 reserved_at_20[0x15];
8362 u8 version_oper[0x3];
8363 u8 reserved_at_38[5];
8364 u8 version_admin[0x3];
8365 u8 willing_admin[0x1];
8366 u8 reserved_at_41[0x3];
8367 u8 pfc_cap_oper[0x4];
8368 u8 reserved_at_48[0x4];
8369 u8 pfc_cap_admin[0x4];
8370 u8 reserved_at_50[0x4];
8371 u8 num_of_tc_oper[0x4];
8372 u8 reserved_at_58[0x4];
8373 u8 num_of_tc_admin[0x4];
8374 u8 remote_willing[0x1];
8375 u8 reserved_at_61[3];
8376 u8 remote_pfc_cap[4];
8377 u8 reserved_at_68[0x14];
8378 u8 remote_num_of_tc[0x4];
8379 u8 reserved_at_80[0x18];
8380 u8 error[0x8];
8381 u8 reserved_at_a0[0x160];
8382};
8383
8384struct mlx5_ifc_lagc_bits {
8385 u8 reserved_at_0[0x1d];
8386 u8 lag_state[0x3];
8387
8388 u8 reserved_at_20[0x14];
8389 u8 tx_remap_affinity_2[0x4];
8390 u8 reserved_at_38[0x4];
8391 u8 tx_remap_affinity_1[0x4];
8392};
8393
8394struct mlx5_ifc_create_lag_out_bits {
8395 u8 status[0x8];
8396 u8 reserved_at_8[0x18];
8397
8398 u8 syndrome[0x20];
8399
8400 u8 reserved_at_40[0x40];
8401};
8402
8403struct mlx5_ifc_create_lag_in_bits {
8404 u8 opcode[0x10];
8405 u8 reserved_at_10[0x10];
8406
8407 u8 reserved_at_20[0x10];
8408 u8 op_mod[0x10];
8409
8410 struct mlx5_ifc_lagc_bits ctx;
8411};
8412
8413struct mlx5_ifc_modify_lag_out_bits {
8414 u8 status[0x8];
8415 u8 reserved_at_8[0x18];
8416
8417 u8 syndrome[0x20];
8418
8419 u8 reserved_at_40[0x40];
8420};
8421
8422struct mlx5_ifc_modify_lag_in_bits {
8423 u8 opcode[0x10];
8424 u8 reserved_at_10[0x10];
8425
8426 u8 reserved_at_20[0x10];
8427 u8 op_mod[0x10];
8428
8429 u8 reserved_at_40[0x20];
8430 u8 field_select[0x20];
8431
8432 struct mlx5_ifc_lagc_bits ctx;
8433};
8434
8435struct mlx5_ifc_query_lag_out_bits {
8436 u8 status[0x8];
8437 u8 reserved_at_8[0x18];
8438
8439 u8 syndrome[0x20];
8440
8441 u8 reserved_at_40[0x40];
8442
8443 struct mlx5_ifc_lagc_bits ctx;
8444};
8445
8446struct mlx5_ifc_query_lag_in_bits {
8447 u8 opcode[0x10];
8448 u8 reserved_at_10[0x10];
8449
8450 u8 reserved_at_20[0x10];
8451 u8 op_mod[0x10];
8452
8453 u8 reserved_at_40[0x40];
8454};
8455
8456struct mlx5_ifc_destroy_lag_out_bits {
8457 u8 status[0x8];
8458 u8 reserved_at_8[0x18];
8459
8460 u8 syndrome[0x20];
8461
8462 u8 reserved_at_40[0x40];
8463};
8464
8465struct mlx5_ifc_destroy_lag_in_bits {
8466 u8 opcode[0x10];
8467 u8 reserved_at_10[0x10];
8468
8469 u8 reserved_at_20[0x10];
8470 u8 op_mod[0x10];
8471
8472 u8 reserved_at_40[0x40];
8473};
8474
8475struct mlx5_ifc_create_vport_lag_out_bits {
8476 u8 status[0x8];
8477 u8 reserved_at_8[0x18];
8478
8479 u8 syndrome[0x20];
8480
8481 u8 reserved_at_40[0x40];
8482};
8483
8484struct mlx5_ifc_create_vport_lag_in_bits {
8485 u8 opcode[0x10];
8486 u8 reserved_at_10[0x10];
8487
8488 u8 reserved_at_20[0x10];
8489 u8 op_mod[0x10];
8490
8491 u8 reserved_at_40[0x40];
8492};
8493
8494struct mlx5_ifc_destroy_vport_lag_out_bits {
8495 u8 status[0x8];
8496 u8 reserved_at_8[0x18];
8497
8498 u8 syndrome[0x20];
8499
8500 u8 reserved_at_40[0x40];
8501};
8502
8503struct mlx5_ifc_destroy_vport_lag_in_bits {
8504 u8 opcode[0x10];
8505 u8 reserved_at_10[0x10];
8506
8507 u8 reserved_at_20[0x10];
8508 u8 op_mod[0x10];
8509
8510 u8 reserved_at_40[0x40];
8511};
8512
8513#endif /* MLX5_IFC_H */