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Linux kernel mirror (for testing)
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linux
1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#ifndef __FCOE_COMMON__
10#define __FCOE_COMMON__
11/*********************/
12/* FCOE FW CONSTANTS */
13/*********************/
14
15#define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12
16#define FCOE_MAX_SIZE_FCP_DATA_SUPER (8600)
17
18struct fcoe_abts_pkt {
19 __le32 abts_rsp_fc_payload_lo;
20 __le16 abts_rsp_rx_id;
21 u8 abts_rsp_rctl;
22 u8 reserved2;
23};
24
25/* FCoE additional WQE (Sq/XferQ) information */
26union fcoe_additional_info_union {
27 __le32 previous_tid;
28 __le32 parent_tid;
29 __le32 burst_length;
30 __le32 seq_rec_updated_offset;
31};
32
33struct fcoe_exp_ro {
34 __le32 data_offset;
35 __le32 reserved;
36};
37
38union fcoe_cleanup_addr_exp_ro_union {
39 struct regpair abts_rsp_fc_payload_hi;
40 struct fcoe_exp_ro exp_ro;
41};
42
43/* FCoE Ramrod Command IDs */
44enum fcoe_completion_status {
45 FCOE_COMPLETION_STATUS_SUCCESS,
46 FCOE_COMPLETION_STATUS_FCOE_VER_ERR,
47 FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR,
48 MAX_FCOE_COMPLETION_STATUS
49};
50
51struct fc_addr_nw {
52 u8 addr_lo;
53 u8 addr_mid;
54 u8 addr_hi;
55};
56
57/* FCoE connection offload */
58struct fcoe_conn_offload_ramrod_data {
59 struct regpair sq_pbl_addr;
60 struct regpair sq_curr_page_addr;
61 struct regpair sq_next_page_addr;
62 struct regpair xferq_pbl_addr;
63 struct regpair xferq_curr_page_addr;
64 struct regpair xferq_next_page_addr;
65 struct regpair respq_pbl_addr;
66 struct regpair respq_curr_page_addr;
67 struct regpair respq_next_page_addr;
68 __le16 dst_mac_addr_lo;
69 __le16 dst_mac_addr_mid;
70 __le16 dst_mac_addr_hi;
71 __le16 src_mac_addr_lo;
72 __le16 src_mac_addr_mid;
73 __le16 src_mac_addr_hi;
74 __le16 tx_max_fc_pay_len;
75 __le16 e_d_tov_timer_val;
76 __le16 rx_max_fc_pay_len;
77 __le16 vlan_tag;
78#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF
79#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0
80#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1
81#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12
82#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7
83#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13
84 __le16 physical_q0;
85 __le16 rec_rr_tov_timer_val;
86 struct fc_addr_nw s_id;
87 u8 max_conc_seqs_c3;
88 struct fc_addr_nw d_id;
89 u8 flags;
90#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1
91#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0
92#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1
93#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1
94#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1
95#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2
96#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1
97#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3
98#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3
99#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 4
100#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x3
101#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 6
102 __le16 conn_id;
103 u8 def_q_idx;
104 u8 reserved[5];
105};
106
107/* FCoE terminate connection request */
108struct fcoe_conn_terminate_ramrod_data {
109 struct regpair terminate_params_addr;
110};
111
112struct fcoe_slow_sgl_ctx {
113 struct regpair base_sgl_addr;
114 __le16 curr_sge_off;
115 __le16 remainder_num_sges;
116 __le16 curr_sgl_index;
117 __le16 reserved;
118};
119
120union fcoe_dix_desc_ctx {
121 struct fcoe_slow_sgl_ctx dix_sgl;
122 struct scsi_sge cached_dix_sge;
123};
124
125struct fcoe_fast_sgl_ctx {
126 struct regpair sgl_start_addr;
127 __le32 sgl_byte_offset;
128 __le16 task_reuse_cnt;
129 __le16 init_offset_in_first_sge;
130};
131
132struct fcoe_fcp_cmd_payload {
133 __le32 opaque[8];
134};
135
136struct fcoe_fcp_rsp_payload {
137 __le32 opaque[6];
138};
139
140struct fcoe_fcp_xfer_payload {
141 __le32 opaque[3];
142};
143
144/* FCoE firmware function init */
145struct fcoe_init_func_ramrod_data {
146 struct scsi_init_func_params func_params;
147 struct scsi_init_func_queues q_params;
148 __le16 mtu;
149 __le16 sq_num_pages_in_pbl;
150 __le32 reserved;
151};
152
153/* FCoE: Mode of the connection: Target or Initiator or both */
154enum fcoe_mode_type {
155 FCOE_INITIATOR_MODE = 0x0,
156 FCOE_TARGET_MODE = 0x1,
157 FCOE_BOTH_OR_NOT_CHOSEN = 0x3,
158 MAX_FCOE_MODE_TYPE
159};
160
161struct fcoe_rx_stat {
162 struct regpair fcoe_rx_byte_cnt;
163 struct regpair fcoe_rx_data_pkt_cnt;
164 struct regpair fcoe_rx_xfer_pkt_cnt;
165 struct regpair fcoe_rx_other_pkt_cnt;
166 __le32 fcoe_silent_drop_pkt_cmdq_full_cnt;
167 __le32 fcoe_silent_drop_pkt_rq_full_cnt;
168 __le32 fcoe_silent_drop_pkt_crc_error_cnt;
169 __le32 fcoe_silent_drop_pkt_task_invalid_cnt;
170 __le32 fcoe_silent_drop_total_pkt_cnt;
171 __le32 rsrv;
172};
173
174struct fcoe_stat_ramrod_data {
175 struct regpair stat_params_addr;
176};
177
178struct protection_info_ctx {
179 __le16 flags;
180#define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3
181#define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0
182#define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1
183#define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2
184#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1
185#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
186#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF
187#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4
188#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
189#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8
190#define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F
191#define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9
192 u8 dix_block_size;
193 u8 dst_size;
194};
195
196union protection_info_union_ctx {
197 struct protection_info_ctx info;
198 __le32 value;
199};
200
201struct fcp_rsp_payload_padded {
202 struct fcoe_fcp_rsp_payload rsp_payload;
203 __le32 reserved[2];
204};
205
206struct fcp_xfer_payload_padded {
207 struct fcoe_fcp_xfer_payload xfer_payload;
208 __le32 reserved[5];
209};
210
211struct fcoe_tx_data_params {
212 __le32 data_offset;
213 __le32 offset_in_io;
214 u8 flags;
215#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1
216#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0
217#define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1
218#define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1
219#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1
220#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2
221#define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F
222#define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3
223 u8 dif_residual;
224 __le16 seq_cnt;
225 __le16 single_sge_saved_offset;
226 __le16 next_dif_offset;
227 __le16 seq_id;
228 __le16 reserved3;
229};
230
231struct fcoe_tx_mid_path_params {
232 __le32 parameter;
233 u8 r_ctl;
234 u8 type;
235 u8 cs_ctl;
236 u8 df_ctl;
237 __le16 rx_id;
238 __le16 ox_id;
239};
240
241struct fcoe_tx_params {
242 struct fcoe_tx_data_params data;
243 struct fcoe_tx_mid_path_params mid_path;
244};
245
246union fcoe_tx_info_union_ctx {
247 struct fcoe_fcp_cmd_payload fcp_cmd_payload;
248 struct fcp_rsp_payload_padded fcp_rsp_payload;
249 struct fcp_xfer_payload_padded fcp_xfer_payload;
250 struct fcoe_tx_params tx_params;
251};
252
253struct ystorm_fcoe_task_st_ctx {
254 u8 task_type;
255 u8 sgl_mode;
256#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
257#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0
258#define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x7F
259#define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 1
260 u8 cached_dix_sge;
261 u8 expect_first_xfer;
262 __le32 num_pbf_zero_write;
263 union protection_info_union_ctx protection_info_union;
264 __le32 data_2_trns_rem;
265 struct scsi_sgl_params sgl_params;
266 u8 reserved1[12];
267 union fcoe_tx_info_union_ctx tx_info_union;
268 union fcoe_dix_desc_ctx dix_desc;
269 struct scsi_cached_sges data_desc;
270 __le16 ox_id;
271 __le16 rx_id;
272 __le32 task_rety_identifier;
273 u8 reserved2[8];
274};
275
276struct ystorm_fcoe_task_ag_ctx {
277 u8 byte0;
278 u8 byte1;
279 __le16 word0;
280 u8 flags0;
281#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF
282#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0
283#define YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
284#define YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
285#define YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
286#define YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
287#define YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
288#define YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
289#define YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
290#define YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
291 u8 flags1;
292#define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
293#define YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0
294#define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
295#define YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
296#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
297#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
298#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
299#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6
300#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
301#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
302 u8 flags2;
303#define YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1
304#define YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0
305#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
306#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
307#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
308#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
309#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
310#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
311#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
312#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
313#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
314#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
315#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
316#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6
317#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
318#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
319 u8 byte2;
320 __le32 reg0;
321 u8 byte3;
322 u8 byte4;
323 __le16 rx_id;
324 __le16 word2;
325 __le16 word3;
326 __le16 word4;
327 __le16 word5;
328 __le32 reg1;
329 __le32 reg2;
330};
331
332struct tstorm_fcoe_task_ag_ctx {
333 u8 reserved;
334 u8 byte1;
335 __le16 icid;
336 u8 flags0;
337#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
338#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
339#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
340#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
341#define TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
342#define TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
343#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1
344#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6
345#define TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1
346#define TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7
347 u8 flags1;
348#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1
349#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0
350#define TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1
351#define TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1
352#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
353#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2
354#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
355#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4
356#define TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
357#define TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6
358 u8 flags2;
359#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
360#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0
361#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
362#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2
363#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
364#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4
365#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3
366#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6
367 u8 flags3;
368#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3
369#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0
370#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1
371#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2
372#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1
373#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
374#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
375#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4
376#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
377#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5
378#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
379#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
380#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1
381#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7
382 u8 flags4;
383#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1
384#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
385#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1
386#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1
387#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
388#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2
389#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
390#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
391#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
392#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4
393#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
394#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5
395#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
396#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6
397#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
398#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7
399 u8 cleanup_state;
400 __le16 last_sent_tid;
401 __le32 rec_rr_tov_exp_timeout;
402 u8 byte3;
403 u8 byte4;
404 __le16 word2;
405 __le16 word3;
406 __le16 word4;
407 __le32 data_offset_end_of_seq;
408 __le32 data_offset_next;
409};
410
411struct fcoe_tstorm_fcoe_task_st_ctx_read_write {
412 union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union;
413 __le16 flags;
414#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x1
415#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0
416#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1
417#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 1
418#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1
419#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 2
420#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1
421#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3
422#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1
423#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4
424#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1
425#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 5
426#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3
427#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 6
428#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0xFF
429#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 8
430 __le16 seq_cnt;
431 u8 seq_id;
432 u8 ooo_rx_seq_id;
433 __le16 rx_id;
434 struct fcoe_abts_pkt abts_data;
435 __le32 e_d_tov_exp_timeout_val;
436 __le16 ooo_rx_seq_cnt;
437 __le16 reserved1;
438};
439
440struct fcoe_tstorm_fcoe_task_st_ctx_read_only {
441 u8 task_type;
442 u8 dev_type;
443 u8 conf_supported;
444 u8 glbl_q_num;
445 __le32 cid;
446 __le32 fcp_cmd_trns_size;
447 __le32 rsrv;
448};
449
450struct tstorm_fcoe_task_st_ctx {
451 struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write;
452 struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only;
453};
454
455struct mstorm_fcoe_task_ag_ctx {
456 u8 byte0;
457 u8 byte1;
458 __le16 icid;
459 u8 flags0;
460#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
461#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
462#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
463#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
464#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1
465#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5
466#define MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
467#define MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
468#define MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
469#define MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
470 u8 flags1;
471#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
472#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0
473#define MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
474#define MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
475#define MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
476#define MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4
477#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
478#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
479#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
480#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
481 u8 flags2;
482#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
483#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0
484#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
485#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
486#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
487#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
488#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
489#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
490#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
491#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
492#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
493#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
494#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1
495#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
496#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
497#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
498 u8 cleanup_state;
499 __le32 received_bytes;
500 u8 byte3;
501 u8 glbl_q_num;
502 __le16 word1;
503 __le16 tid_to_xfer;
504 __le16 word3;
505 __le16 word4;
506 __le16 word5;
507 __le32 expected_bytes;
508 __le32 reg2;
509};
510
511struct mstorm_fcoe_task_st_ctx {
512 struct regpair rsp_buf_addr;
513 __le32 rsrv[2];
514 struct scsi_sgl_params sgl_params;
515 __le32 data_2_trns_rem;
516 __le32 data_buffer_offset;
517 __le16 parent_id;
518 __le16 flags;
519#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK 0xF
520#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT 0
521#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3
522#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT 4
523#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK 0x1
524#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT 6
525#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK 0x1
526#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7
527#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3
528#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT 8
529#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
530#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10
531#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK 0x1
532#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT 11
533#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK 0x1
534#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT 12
535#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
536#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 13
537#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3
538#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT 14
539 struct scsi_cached_sges data_desc;
540};
541
542struct ustorm_fcoe_task_ag_ctx {
543 u8 reserved;
544 u8 byte1;
545 __le16 icid;
546 u8 flags0;
547#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
548#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
549#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
550#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
551#define USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
552#define USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
553#define USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
554#define USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6
555 u8 flags1;
556#define USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
557#define USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0
558#define USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
559#define USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2
560#define USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3
561#define USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4
562#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
563#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
564 u8 flags2;
565#define USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
566#define USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0
567#define USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
568#define USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1
569#define USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
570#define USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2
571#define USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1
572#define USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
573#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
574#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
575#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
576#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5
577#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
578#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6
579#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
580#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7
581 u8 flags3;
582#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
583#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0
584#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
585#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1
586#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
587#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2
588#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
589#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
590#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
591#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
592 __le32 dif_err_intervals;
593 __le32 dif_error_1st_interval;
594 __le32 global_cq_num;
595 __le32 reg3;
596 __le32 reg4;
597 __le32 reg5;
598};
599
600struct fcoe_task_context {
601 struct ystorm_fcoe_task_st_ctx ystorm_st_context;
602 struct regpair ystorm_st_padding[2];
603 struct tdif_task_context tdif_context;
604 struct ystorm_fcoe_task_ag_ctx ystorm_ag_context;
605 struct tstorm_fcoe_task_ag_ctx tstorm_ag_context;
606 struct timers_context timer_context;
607 struct tstorm_fcoe_task_st_ctx tstorm_st_context;
608 struct regpair tstorm_st_padding[2];
609 struct mstorm_fcoe_task_ag_ctx mstorm_ag_context;
610 struct mstorm_fcoe_task_st_ctx mstorm_st_context;
611 struct ustorm_fcoe_task_ag_ctx ustorm_ag_context;
612 struct rdif_task_context rdif_context;
613};
614
615struct fcoe_tx_stat {
616 struct regpair fcoe_tx_byte_cnt;
617 struct regpair fcoe_tx_data_pkt_cnt;
618 struct regpair fcoe_tx_xfer_pkt_cnt;
619 struct regpair fcoe_tx_other_pkt_cnt;
620};
621
622struct fcoe_wqe {
623 __le16 task_id;
624 __le16 flags;
625#define FCOE_WQE_REQ_TYPE_MASK 0xF
626#define FCOE_WQE_REQ_TYPE_SHIFT 0
627#define FCOE_WQE_SGL_MODE_MASK 0x1
628#define FCOE_WQE_SGL_MODE_SHIFT 4
629#define FCOE_WQE_CONTINUATION_MASK 0x1
630#define FCOE_WQE_CONTINUATION_SHIFT 5
631#define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1
632#define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6
633#define FCOE_WQE_RESERVED_MASK 0x1
634#define FCOE_WQE_RESERVED_SHIFT 7
635#define FCOE_WQE_NUM_SGES_MASK 0xF
636#define FCOE_WQE_NUM_SGES_SHIFT 8
637#define FCOE_WQE_RESERVED1_MASK 0xF
638#define FCOE_WQE_RESERVED1_SHIFT 12
639 union fcoe_additional_info_union additional_info_union;
640};
641
642struct xfrqe_prot_flags {
643 u8 flags;
644#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
645#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
646#define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1
647#define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4
648#define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3
649#define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5
650#define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1
651#define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7
652};
653
654struct fcoe_db_data {
655 u8 params;
656#define FCOE_DB_DATA_DEST_MASK 0x3
657#define FCOE_DB_DATA_DEST_SHIFT 0
658#define FCOE_DB_DATA_AGG_CMD_MASK 0x3
659#define FCOE_DB_DATA_AGG_CMD_SHIFT 2
660#define FCOE_DB_DATA_BYPASS_EN_MASK 0x1
661#define FCOE_DB_DATA_BYPASS_EN_SHIFT 4
662#define FCOE_DB_DATA_RESERVED_MASK 0x1
663#define FCOE_DB_DATA_RESERVED_SHIFT 5
664#define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3
665#define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6
666 u8 agg_flags;
667 __le16 sq_prod;
668};
669#endif /* __FCOE_COMMON__ */