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1====================== 2Aspeed Pin Controllers 3====================== 4 5The Aspeed SoCs vary in functionality inside a generation but have a common mux 6device register layout. 7 8Required properties for g4: 9- compatible : Should be one of the following: 10 "aspeed,ast2400-pinctrl" 11 "aspeed,g4-pinctrl" 12 13Required properties for g5: 14- compatible : Should be one of the following: 15 "aspeed,ast2500-pinctrl" 16 "aspeed,g5-pinctrl" 17 18- aspeed,external-nodes: A cell of phandles to external controller nodes: 19 0: compatible with "aspeed,ast2500-gfx", "syscon" 20 1: compatible with "aspeed,ast2500-lhc", "syscon" 21 22The pin controller node should be the child of a syscon node with the required 23property: 24 25- compatible : Should be one of the following: 26 "aspeed,ast2400-scu", "syscon", "simple-mfd" 27 "aspeed,g4-scu", "syscon", "simple-mfd" 28 "aspeed,ast2500-scu", "syscon", "simple-mfd" 29 "aspeed,g5-scu", "syscon", "simple-mfd" 30 31Refer to the the bindings described in 32Documentation/devicetree/bindings/mfd/syscon.txt 33 34Subnode Format 35============== 36 37The required properties of pinmux child nodes are: 38- function: the mux function to select 39- groups : the list of groups to select with this function 40 41Required properties of pinconf child nodes are: 42- groups: A list of groups to select (either this or "pins" must be 43 specified) 44- pins : A list of ball names as strings, eg "D14" (either this or "groups" 45 must be specified) 46 47Optional properties of pinconf child nodes are: 48- bias-disable : disable any pin bias 49- bias-pull-down: pull down the pin 50- drive-strength: sink or source at most X mA 51 52Definitions are as specified in 53Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt, with any 54further limitations as described above. 55 56For pinmux, each mux function has only one associated pin group. Each group is 57named by its function. The following values for the function and groups 58properties are supported: 59 60aspeed,ast2400-pinctrl, aspeed,g4-pinctrl: 61 62ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6 63ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT EXTRST FLACK FLBUSY FLWP GPID GPID0 GPID2 64GPID4 GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 65I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCRST LPCSMI MAC1LINK MAC2LINK MDIO1 66MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4 67NDTR1 NDTR2 NDTR3 NDTR4 NDTS4 NRI1 NRI2 NRI3 NRI4 NRTS1 NRTS2 NRTS3 OSCCLK PWM0 68PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1 69ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK 70SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ 71SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4 72TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS 73VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2 74 75aspeed,ast2500-pinctrl, aspeed,g5-pinctrl: 76 77ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6 78ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT ESPI FWSPICS1 FWSPICS2 GPID0 GPID2 GPID4 79GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 80I2C7 I2C8 I2C9 LAD0 LAD1 LAD2 LAD3 LCLK LFRAME LPCHC LPCPD LPCPLUS LPCPME 81LPCRST LPCSMI LSIRQ MAC1LINK MAC2LINK MDIO1 MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 82NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4 NDTR1 NDTR2 NDTR3 NDTR4 NRI1 NRI2 83NRI3 NRI4 NRTS1 NRTS2 NRTS3 NRTS4 OSCCLK PEWAKE PNOR PWM0 PWM1 PWM2 PWM3 PWM4 84PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 RXD1 RXD2 RXD3 RXD4 SALT1 SALT10 85SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9 86SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ 87SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0 88SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 89TXD3 TXD4 UART6 USBCKI VGABIOSROM VGAHS VGAVS VPI24 VPO WDTRST1 WDTRST2 90 91Examples 92======== 93 94g4 Example 95---------- 96 97syscon: scu@1e6e2000 { 98 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; 99 reg = <0x1e6e2000 0x1a8>; 100 101 pinctrl: pinctrl { 102 compatible = "aspeed,g4-pinctrl"; 103 104 pinctrl_i2c3_default: i2c3_default { 105 function = "I2C3"; 106 groups = "I2C3"; 107 }; 108 109 pinctrl_gpioh0_unbiased_default: gpioh0 { 110 pins = "A8"; 111 bias-disable; 112 }; 113 }; 114}; 115 116g5 Example 117---------- 118 119ahb { 120 apb { 121 syscon: scu@1e6e2000 { 122 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; 123 reg = <0x1e6e2000 0x1a8>; 124 125 pinctrl: pinctrl { 126 compatible = "aspeed,g5-pinctrl"; 127 aspeed,external-nodes = <&gfx &lhc>; 128 129 pinctrl_i2c3_default: i2c3_default { 130 function = "I2C3"; 131 groups = "I2C3"; 132 }; 133 134 pinctrl_gpioh0_unbiased_default: gpioh0 { 135 pins = "A18"; 136 bias-disable; 137 }; 138 }; 139 }; 140 141 gfx: display@1e6e6000 { 142 compatible = "aspeed,ast2500-gfx", "syscon"; 143 reg = <0x1e6e6000 0x1000>; 144 }; 145 }; 146 147 lpc: lpc@1e789000 { 148 compatible = "aspeed,ast2500-lpc", "simple-mfd"; 149 reg = <0x1e789000 0x1000>; 150 151 #address-cells = <1>; 152 #size-cells = <1>; 153 ranges = <0x0 0x1e789000 0x1000>; 154 155 lpc_host: lpc-host@80 { 156 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; 157 reg = <0x80 0x1e0>; 158 reg-io-width = <4>; 159 160 #address-cells = <1>; 161 #size-cells = <1>; 162 ranges = <0x0 0x80 0x1e0>; 163 164 lhc: lhc@20 { 165 compatible = "aspeed,ast2500-lhc"; 166 reg = <0x20 0x24 0x48 0x8>; 167 }; 168 }; 169 }; 170};