tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1Axis ARTPEC-6 Pin Controller
2
3Required properties:
4- compatible: "axis,artpec6-pinctrl".
5- reg: Should contain the register physical address and length for the pin
6 controller.
7
8A pinctrl node should contain at least one subnode representing the pinctrl
9groups available on the machine. Each subnode will list the mux function
10required and what pin group it will use. Each subnode will also configure the
11drive strength and bias pullup of the pin group. If either of these options is
12not set, its actual value will be unspecified.
13
14
15Required subnode-properties:
16- function: Function to mux.
17- groups: Name of the pin group to use for the function above.
18
19 Available functions and groups (function: group0, group1...):
20 gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,
21 i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,
22 spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0,
23 uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0
24 cpuclkout: cpuclkoutgrp0
25 udlclkout: udlclkoutgrp0
26 i2c1: i2c1grp0
27 i2c2: i2c2grp0
28 i2c3: i2c3grp0
29 i2s0: i2s0grp0
30 i2s1: i2s1grp0
31 i2srefclk: i2srefclkgrp0
32 spi0: spi0grp0
33 spi1: spi1grp0
34 pciedebug: pciedebuggrp0
35 uart0: uart0grp0, uart0grp1
36 uart1: uart1grp0
37 uart2: uart2grp0, uart2grp1
38 uart3: uart3grp0
39 uart4: uart4grp0
40 uart5: uart5grp0
41 nand: nandgrp0
42 sdio0: sdio0grp0
43 sdio1: sdio1grp0
44 ethernet: ethernetgrp0
45
46
47Optional subnode-properties (see pinctrl-bindings.txt):
48- drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3.
49- bias-pull-up
50- bias-disable
51
52Examples:
53pinctrl@f801d000 {
54 compatible = "axis,artpec6-pinctrl";
55 reg = <0xf801d000 0x400>;
56
57 pinctrl_uart0: uart0grp {
58 function = "uart0";
59 groups = "uart0grp0";
60 drive-strength = <4>;
61 bias-pull-up;
62 };
63 pinctrl_uart3: uart3grp {
64 function = "uart3";
65 groups = "uart3grp0";
66 };
67};
68uart0: uart@f8036000 {
69 compatible = "arm,pl011", "arm,primecell";
70 reg = <0xf8036000 0x1000>;
71 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
72 clocks = <&pll2div24>, <&apb_pclk>;
73 clock-names = "uart_clk", "apb_pclk";
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_uart0>;
76};
77uart3: uart@f8039000 {
78 compatible = "arm,pl011", "arm,primecell";
79 reg = <0xf8039000 0x1000>;
80 interrupts = <0 128 IRQ_TYPE_LEVEL_HIGH>;
81 clocks = <&pll2div24>, <&apb_pclk>;
82 clock-names = "uart_clk", "apb_pclk";
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_uart3>;
85};