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1/* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef __ETH_COMMON__
34#define __ETH_COMMON__
35
36/********************/
37/* ETH FW CONSTANTS */
38/********************/
39#define ETH_HSI_VER_MAJOR 3
40#define ETH_HSI_VER_MINOR 10
41
42#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
43
44#define ETH_CACHE_LINE_SIZE 64
45#define ETH_RX_CQE_GAP 32
46#define ETH_MAX_RAMROD_PER_CON 8
47#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
48#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
49#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
50#define ETH_RX_NUM_NEXT_PAGE_BDS 2
51
52#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
53#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
54#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
55#define ETH_TX_MAX_LSO_HDR_NBD 4
56#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
57#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
58#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
59#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
60#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
61#define ETH_TX_MAX_LSO_HDR_BYTES 510
62#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
63#define ETH_TX_LSO_WINDOW_MIN_LEN 9700
64#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
65#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
66#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
67
68#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
69#define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \
70 (ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2)
71#define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \
72 (ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
73
74/* Maximum number of buffers, used for RX packet placement */
75#define ETH_RX_MAX_BUFF_PER_PKT 5
76
77/* num of MAC/VLAN filters */
78#define ETH_NUM_MAC_FILTERS 512
79#define ETH_NUM_VLAN_FILTERS 512
80
81/* approx. multicast constants */
82#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
83#define ETH_MULTICAST_MAC_BINS 256
84#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
85
86/* ethernet vport update constants */
87#define ETH_FILTER_RULES_COUNT 10
88#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
89#define ETH_RSS_KEY_SIZE_REGS 10
90#define ETH_RSS_ENGINE_NUM_K2 207
91#define ETH_RSS_ENGINE_NUM_BB 127
92
93/* TPA constants */
94#define ETH_TPA_MAX_AGGS_NUM 64
95#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
96#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
97#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
98
99/* Control frame check constants */
100#define ETH_CTL_FRAME_ETH_TYPE_NUM 4
101
102struct eth_tx_1st_bd_flags {
103 u8 bitfields;
104#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
105#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
106#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
107#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
108#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
109#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
110#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
111#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
112#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
113#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
114#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
115#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
116#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
117#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
118#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
119#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
120};
121
122/* The parsing information data fo rthe first tx bd of a given packet. */
123struct eth_tx_data_1st_bd {
124 __le16 vlan;
125 u8 nbds;
126 struct eth_tx_1st_bd_flags bd_flags;
127 __le16 bitfields;
128#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
129#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
130#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
131#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
132#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
133#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
134};
135
136/* The parsing information data for the second tx bd of a given packet. */
137struct eth_tx_data_2nd_bd {
138 __le16 tunn_ip_size;
139 __le16 bitfields1;
140#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
141#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
142#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
143#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
144#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
145#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
146#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
147#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
148#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
149#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
150#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
151#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
152#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
153#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
154#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
155#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
156#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
157#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
158#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
159#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
160 __le16 bitfields2;
161#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
162#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
163#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
164#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
165};
166
167/* Firmware data for L2-EDPM packet. */
168struct eth_edpm_fw_data {
169 struct eth_tx_data_1st_bd data_1st_bd;
170 struct eth_tx_data_2nd_bd data_2nd_bd;
171 __le32 reserved;
172};
173
174struct eth_fast_path_cqe_fw_debug {
175 __le16 reserved2;
176};
177
178/* tunneling parsing flags */
179struct eth_tunnel_parsing_flags {
180 u8 flags;
181#define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
182#define ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0
183#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1
184#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
185#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3
186#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3
187#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1
188#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5
189#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1
190#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6
191#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1
192#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
193};
194
195/* PMD flow control bits */
196struct eth_pmd_flow_flags {
197 u8 flags;
198#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1
199#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
200#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1
201#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
202#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
203#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
204};
205
206/* Regular ETH Rx FP CQE. */
207struct eth_fast_path_rx_reg_cqe {
208 u8 type;
209 u8 bitfields;
210#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
211#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
212#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
213#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
214#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
215#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
216 __le16 pkt_len;
217 struct parsing_and_err_flags pars_flags;
218 __le16 vlan_tag;
219 __le32 rss_hash;
220 __le16 len_on_first_bd;
221 u8 placement_offset;
222 struct eth_tunnel_parsing_flags tunnel_pars_flags;
223 u8 bd_num;
224 u8 reserved[9];
225 struct eth_fast_path_cqe_fw_debug fw_debug;
226 u8 reserved1[3];
227 struct eth_pmd_flow_flags pmd_flags;
228};
229
230/* TPA-continue ETH Rx FP CQE. */
231struct eth_fast_path_rx_tpa_cont_cqe {
232 u8 type;
233 u8 tpa_agg_index;
234 __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
235 u8 reserved;
236 u8 reserved1;
237 __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
238 u8 reserved3[3];
239 struct eth_pmd_flow_flags pmd_flags;
240};
241
242/* TPA-end ETH Rx FP CQE. */
243struct eth_fast_path_rx_tpa_end_cqe {
244 u8 type;
245 u8 tpa_agg_index;
246 __le16 total_packet_len;
247 u8 num_of_bds;
248 u8 end_reason;
249 __le16 num_of_coalesced_segs;
250 __le32 ts_delta;
251 __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
252 __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE];
253 __le16 reserved1;
254 u8 reserved2;
255 struct eth_pmd_flow_flags pmd_flags;
256};
257
258/* TPA-start ETH Rx FP CQE. */
259struct eth_fast_path_rx_tpa_start_cqe {
260 u8 type;
261 u8 bitfields;
262#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
263#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
264#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
265#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
266#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
267#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
268 __le16 seg_len;
269 struct parsing_and_err_flags pars_flags;
270 __le16 vlan_tag;
271 __le32 rss_hash;
272 __le16 len_on_first_bd;
273 u8 placement_offset;
274 struct eth_tunnel_parsing_flags tunnel_pars_flags;
275 u8 tpa_agg_index;
276 u8 header_len;
277 __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
278 struct eth_fast_path_cqe_fw_debug fw_debug;
279 u8 reserved;
280 struct eth_pmd_flow_flags pmd_flags;
281};
282
283/* The L4 pseudo checksum mode for Ethernet */
284enum eth_l4_pseudo_checksum_mode {
285 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH,
286 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH,
287 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
288};
289
290struct eth_rx_bd {
291 struct regpair addr;
292};
293
294/* regular ETH Rx SP CQE */
295struct eth_slow_path_rx_cqe {
296 u8 type;
297 u8 ramrod_cmd_id;
298 u8 error_flag;
299 u8 reserved[25];
300 __le16 echo;
301 u8 reserved1;
302 struct eth_pmd_flow_flags pmd_flags;
303};
304
305/* union for all ETH Rx CQE types */
306union eth_rx_cqe {
307 struct eth_fast_path_rx_reg_cqe fast_path_regular;
308 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
309 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
310 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
311 struct eth_slow_path_rx_cqe slow_path;
312};
313
314/* ETH Rx CQE type */
315enum eth_rx_cqe_type {
316 ETH_RX_CQE_TYPE_UNUSED,
317 ETH_RX_CQE_TYPE_REGULAR,
318 ETH_RX_CQE_TYPE_SLOW_PATH,
319 ETH_RX_CQE_TYPE_TPA_START,
320 ETH_RX_CQE_TYPE_TPA_CONT,
321 ETH_RX_CQE_TYPE_TPA_END,
322 MAX_ETH_RX_CQE_TYPE
323};
324
325struct eth_rx_pmd_cqe {
326 union eth_rx_cqe cqe;
327 u8 reserved[ETH_RX_CQE_GAP];
328};
329
330enum eth_rx_tunn_type {
331 ETH_RX_NO_TUNN,
332 ETH_RX_TUNN_GENEVE,
333 ETH_RX_TUNN_GRE,
334 ETH_RX_TUNN_VXLAN,
335 MAX_ETH_RX_TUNN_TYPE
336};
337
338/* Aggregation end reason. */
339enum eth_tpa_end_reason {
340 ETH_AGG_END_UNUSED,
341 ETH_AGG_END_SP_UPDATE,
342 ETH_AGG_END_MAX_LEN,
343 ETH_AGG_END_LAST_SEG,
344 ETH_AGG_END_TIMEOUT,
345 ETH_AGG_END_NOT_CONSISTENT,
346 ETH_AGG_END_OUT_OF_ORDER,
347 ETH_AGG_END_NON_TPA_SEG,
348 MAX_ETH_TPA_END_REASON
349};
350
351/* The first tx bd of a given packet */
352struct eth_tx_1st_bd {
353 struct regpair addr;
354 __le16 nbytes;
355 struct eth_tx_data_1st_bd data;
356};
357
358/* The second tx bd of a given packet */
359struct eth_tx_2nd_bd {
360 struct regpair addr;
361 __le16 nbytes;
362 struct eth_tx_data_2nd_bd data;
363};
364
365/* The parsing information data for the third tx bd of a given packet. */
366struct eth_tx_data_3rd_bd {
367 __le16 lso_mss;
368 __le16 bitfields;
369#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
370#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
371#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
372#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
373#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
374#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
375#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
376#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
377 u8 tunn_l4_hdr_start_offset_w;
378 u8 tunn_hdr_size_w;
379};
380
381/* The third tx bd of a given packet */
382struct eth_tx_3rd_bd {
383 struct regpair addr;
384 __le16 nbytes;
385 struct eth_tx_data_3rd_bd data;
386};
387
388/* Complementary information for the regular tx bd of a given packet. */
389struct eth_tx_data_bd {
390 __le16 reserved0;
391 __le16 bitfields;
392#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
393#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
394#define ETH_TX_DATA_BD_START_BD_MASK 0x1
395#define ETH_TX_DATA_BD_START_BD_SHIFT 8
396#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
397#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
398 __le16 reserved3;
399};
400
401/* The common non-special TX BD ring element */
402struct eth_tx_bd {
403 struct regpair addr;
404 __le16 nbytes;
405 struct eth_tx_data_bd data;
406};
407
408union eth_tx_bd_types {
409 struct eth_tx_1st_bd first_bd;
410 struct eth_tx_2nd_bd second_bd;
411 struct eth_tx_3rd_bd third_bd;
412 struct eth_tx_bd reg_bd;
413};
414
415/* Mstorm Queue Zone */
416enum eth_tx_tunn_type {
417 ETH_TX_TUNN_GENEVE,
418 ETH_TX_TUNN_TTAG,
419 ETH_TX_TUNN_GRE,
420 ETH_TX_TUNN_VXLAN,
421 MAX_ETH_TX_TUNN_TYPE
422};
423
424/* Ystorm Queue Zone */
425struct xstorm_eth_queue_zone {
426 struct coalescing_timeset int_coalescing_timeset;
427 u8 reserved[7];
428};
429
430/* ETH doorbell data */
431struct eth_db_data {
432 u8 params;
433#define ETH_DB_DATA_DEST_MASK 0x3
434#define ETH_DB_DATA_DEST_SHIFT 0
435#define ETH_DB_DATA_AGG_CMD_MASK 0x3
436#define ETH_DB_DATA_AGG_CMD_SHIFT 2
437#define ETH_DB_DATA_BYPASS_EN_MASK 0x1
438#define ETH_DB_DATA_BYPASS_EN_SHIFT 4
439#define ETH_DB_DATA_RESERVED_MASK 0x1
440#define ETH_DB_DATA_RESERVED_SHIFT 5
441#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
442#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
443 u8 agg_flags;
444 __le16 bd_prod;
445};
446
447#endif /* __ETH_COMMON__ */