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1/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved. 2 * Copyright (C) 2015 Linaro Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13#ifndef __QCOM_SCM_H 14#define __QCOM_SCM_H 15 16#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF)) 17#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0 18#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1 19#define QCOM_SCM_HDCP_MAX_REQ_CNT 5 20 21struct qcom_scm_hdcp_req { 22 u32 addr; 23 u32 val; 24}; 25 26#if IS_ENABLED(CONFIG_QCOM_SCM) 27extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus); 28extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus); 29extern bool qcom_scm_is_available(void); 30extern bool qcom_scm_hdcp_available(void); 31extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, 32 u32 *resp); 33extern bool qcom_scm_pas_supported(u32 peripheral); 34extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, 35 size_t size); 36extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, 37 phys_addr_t size); 38extern int qcom_scm_pas_auth_and_reset(u32 peripheral); 39extern int qcom_scm_pas_shutdown(u32 peripheral); 40extern void qcom_scm_cpu_power_down(u32 flags); 41extern u32 qcom_scm_get_version(void); 42extern int qcom_scm_set_remote_state(u32 state, u32 id); 43#else 44static inline 45int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) 46{ 47 return -ENODEV; 48} 49static inline 50int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) 51{ 52 return -ENODEV; 53} 54static inline bool qcom_scm_is_available(void) { return false; } 55static inline bool qcom_scm_hdcp_available(void) { return false; } 56static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, 57 u32 *resp) { return -ENODEV; } 58static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; } 59static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, 60 size_t size) { return -ENODEV; } 61static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, 62 phys_addr_t size) { return -ENODEV; } 63static inline int 64qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; } 65static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; } 66static inline void qcom_scm_cpu_power_down(u32 flags) {} 67static inline u32 qcom_scm_get_version(void) { return 0; } 68static inline u32 69qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; } 70#endif 71#endif