Linux kernel mirror (for testing)
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linux
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38#include <linux/mlx5/mlx5_ifc.h>
39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
62#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
63#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
64#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
65#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
66#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
67
68/* insert a value to a struct */
69#define MLX5_SET(typ, p, fld, v) do { \
70 u32 _v = v; \
71 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
72 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
73 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
74 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
75 << __mlx5_dw_bit_off(typ, fld))); \
76} while (0)
77
78#define MLX5_SET_TO_ONES(typ, p, fld) do { \
79 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
80 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
81 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
82 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
83 << __mlx5_dw_bit_off(typ, fld))); \
84} while (0)
85
86#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
87__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
88__mlx5_mask(typ, fld))
89
90#define MLX5_GET_PR(typ, p, fld) ({ \
91 u32 ___t = MLX5_GET(typ, p, fld); \
92 pr_debug(#fld " = 0x%x\n", ___t); \
93 ___t; \
94})
95
96#define __MLX5_SET64(typ, p, fld, v) do { \
97 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
98 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
99} while (0)
100
101#define MLX5_SET64(typ, p, fld, v) do { \
102 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
103 __MLX5_SET64(typ, p, fld, v); \
104} while (0)
105
106#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
107 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
108 __MLX5_SET64(typ, p, fld[idx], v); \
109} while (0)
110
111#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
112
113#define MLX5_GET64_PR(typ, p, fld) ({ \
114 u64 ___t = MLX5_GET64(typ, p, fld); \
115 pr_debug(#fld " = 0x%llx\n", ___t); \
116 ___t; \
117})
118
119/* Big endian getters */
120#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
121 __mlx5_64_off(typ, fld)))
122
123#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
124 type_t tmp; \
125 switch (sizeof(tmp)) { \
126 case sizeof(u8): \
127 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
128 break; \
129 case sizeof(u16): \
130 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
131 break; \
132 case sizeof(u32): \
133 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
134 break; \
135 case sizeof(u64): \
136 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
137 break; \
138 } \
139 tmp; \
140 })
141
142enum mlx5_inline_modes {
143 MLX5_INLINE_MODE_NONE,
144 MLX5_INLINE_MODE_L2,
145 MLX5_INLINE_MODE_IP,
146 MLX5_INLINE_MODE_TCP_UDP,
147};
148
149enum {
150 MLX5_MAX_COMMANDS = 32,
151 MLX5_CMD_DATA_BLOCK_SIZE = 512,
152 MLX5_PCI_CMD_XPORT = 7,
153 MLX5_MKEY_BSF_OCTO_SIZE = 4,
154 MLX5_MAX_PSVS = 4,
155};
156
157enum {
158 MLX5_EXTENDED_UD_AV = 0x80000000,
159};
160
161enum {
162 MLX5_CQ_STATE_ARMED = 9,
163 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
164 MLX5_CQ_STATE_FIRED = 0xa,
165};
166
167enum {
168 MLX5_STAT_RATE_OFFSET = 5,
169};
170
171enum {
172 MLX5_INLINE_SEG = 0x80000000,
173};
174
175enum {
176 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
177};
178
179enum {
180 MLX5_MIN_PKEY_TABLE_SIZE = 128,
181 MLX5_MAX_LOG_PKEY_TABLE = 5,
182};
183
184enum {
185 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
186};
187
188enum {
189 MLX5_PFAULT_SUBTYPE_WQE = 0,
190 MLX5_PFAULT_SUBTYPE_RDMA = 1,
191};
192
193enum {
194 MLX5_PERM_LOCAL_READ = 1 << 2,
195 MLX5_PERM_LOCAL_WRITE = 1 << 3,
196 MLX5_PERM_REMOTE_READ = 1 << 4,
197 MLX5_PERM_REMOTE_WRITE = 1 << 5,
198 MLX5_PERM_ATOMIC = 1 << 6,
199 MLX5_PERM_UMR_EN = 1 << 7,
200};
201
202enum {
203 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
204 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
205 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
206 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
207 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
208};
209
210enum {
211 MLX5_EN_RD = (u64)1,
212 MLX5_EN_WR = (u64)2
213};
214
215enum {
216 MLX5_ADAPTER_PAGE_SHIFT = 12,
217 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
218};
219
220enum {
221 MLX5_BFREGS_PER_UAR = 4,
222 MLX5_MAX_UARS = 1 << 8,
223 MLX5_NON_FP_BFREGS_PER_UAR = 2,
224 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
225 MLX5_NON_FP_BFREGS_PER_UAR,
226 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
227 MLX5_NON_FP_BFREGS_PER_UAR,
228 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
229 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
230};
231
232enum {
233 MLX5_MKEY_MASK_LEN = 1ull << 0,
234 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
235 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
236 MLX5_MKEY_MASK_PD = 1ull << 7,
237 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
238 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
239 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
240 MLX5_MKEY_MASK_KEY = 1ull << 13,
241 MLX5_MKEY_MASK_QPN = 1ull << 14,
242 MLX5_MKEY_MASK_LR = 1ull << 17,
243 MLX5_MKEY_MASK_LW = 1ull << 18,
244 MLX5_MKEY_MASK_RR = 1ull << 19,
245 MLX5_MKEY_MASK_RW = 1ull << 20,
246 MLX5_MKEY_MASK_A = 1ull << 21,
247 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
248 MLX5_MKEY_MASK_FREE = 1ull << 29,
249};
250
251enum {
252 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
253
254 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
255 MLX5_UMR_CHECK_FREE = (2 << 5),
256
257 MLX5_UMR_INLINE = (1 << 7),
258};
259
260#define MLX5_UMR_MTT_ALIGNMENT 0x40
261#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
262#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
263
264#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
265
266enum {
267 MLX5_EVENT_QUEUE_TYPE_QP = 0,
268 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
269 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
270};
271
272enum mlx5_event {
273 MLX5_EVENT_TYPE_COMP = 0x0,
274
275 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
276 MLX5_EVENT_TYPE_COMM_EST = 0x02,
277 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
278 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
279 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
280
281 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
282 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
283 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
284 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
285 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
286 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
287
288 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
289 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
290 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
291 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
292 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
293 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
294
295 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
296 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
297
298 MLX5_EVENT_TYPE_CMD = 0x0a,
299 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
300
301 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
302 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
303};
304
305enum {
306 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
307 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
308 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
309 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
310 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
311 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
312 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
313};
314
315enum {
316 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
317 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
318 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
319 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
320 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
321 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
322 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
323 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
324 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
325 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
326 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
327 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
328};
329
330enum {
331 MLX5_ROCE_VERSION_1 = 0,
332 MLX5_ROCE_VERSION_2 = 2,
333};
334
335enum {
336 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
337 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
338};
339
340enum {
341 MLX5_ROCE_L3_TYPE_IPV4 = 0,
342 MLX5_ROCE_L3_TYPE_IPV6 = 1,
343};
344
345enum {
346 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
347 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
348};
349
350enum {
351 MLX5_OPCODE_NOP = 0x00,
352 MLX5_OPCODE_SEND_INVAL = 0x01,
353 MLX5_OPCODE_RDMA_WRITE = 0x08,
354 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
355 MLX5_OPCODE_SEND = 0x0a,
356 MLX5_OPCODE_SEND_IMM = 0x0b,
357 MLX5_OPCODE_LSO = 0x0e,
358 MLX5_OPCODE_RDMA_READ = 0x10,
359 MLX5_OPCODE_ATOMIC_CS = 0x11,
360 MLX5_OPCODE_ATOMIC_FA = 0x12,
361 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
362 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
363 MLX5_OPCODE_BIND_MW = 0x18,
364 MLX5_OPCODE_CONFIG_CMD = 0x1f,
365
366 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
367 MLX5_RECV_OPCODE_SEND = 0x01,
368 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
369 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
370
371 MLX5_CQE_OPCODE_ERROR = 0x1e,
372 MLX5_CQE_OPCODE_RESIZE = 0x16,
373
374 MLX5_OPCODE_SET_PSV = 0x20,
375 MLX5_OPCODE_GET_PSV = 0x21,
376 MLX5_OPCODE_CHECK_PSV = 0x22,
377 MLX5_OPCODE_RGET_PSV = 0x26,
378 MLX5_OPCODE_RCHECK_PSV = 0x27,
379
380 MLX5_OPCODE_UMR = 0x25,
381
382};
383
384enum {
385 MLX5_SET_PORT_RESET_QKEY = 0,
386 MLX5_SET_PORT_GUID0 = 16,
387 MLX5_SET_PORT_NODE_GUID = 17,
388 MLX5_SET_PORT_SYS_GUID = 18,
389 MLX5_SET_PORT_GID_TABLE = 19,
390 MLX5_SET_PORT_PKEY_TABLE = 20,
391};
392
393enum {
394 MLX5_BW_NO_LIMIT = 0,
395 MLX5_100_MBPS_UNIT = 3,
396 MLX5_GBPS_UNIT = 4,
397};
398
399enum {
400 MLX5_MAX_PAGE_SHIFT = 31
401};
402
403enum {
404 MLX5_CAP_OFF_CMDIF_CSUM = 46,
405};
406
407enum {
408 /*
409 * Max wqe size for rdma read is 512 bytes, so this
410 * limits our max_sge_rd as the wqe needs to fit:
411 * - ctrl segment (16 bytes)
412 * - rdma segment (16 bytes)
413 * - scatter elements (16 bytes each)
414 */
415 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
416};
417
418enum mlx5_odp_transport_cap_bits {
419 MLX5_ODP_SUPPORT_SEND = 1 << 31,
420 MLX5_ODP_SUPPORT_RECV = 1 << 30,
421 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
422 MLX5_ODP_SUPPORT_READ = 1 << 28,
423};
424
425struct mlx5_odp_caps {
426 char reserved[0x10];
427 struct {
428 __be32 rc_odp_caps;
429 __be32 uc_odp_caps;
430 __be32 ud_odp_caps;
431 } per_transport_caps;
432 char reserved2[0xe4];
433};
434
435struct mlx5_cmd_layout {
436 u8 type;
437 u8 rsvd0[3];
438 __be32 inlen;
439 __be64 in_ptr;
440 __be32 in[4];
441 __be32 out[4];
442 __be64 out_ptr;
443 __be32 outlen;
444 u8 token;
445 u8 sig;
446 u8 rsvd1;
447 u8 status_own;
448};
449
450struct health_buffer {
451 __be32 assert_var[5];
452 __be32 rsvd0[3];
453 __be32 assert_exit_ptr;
454 __be32 assert_callra;
455 __be32 rsvd1[2];
456 __be32 fw_ver;
457 __be32 hw_id;
458 __be32 rsvd2;
459 u8 irisc_index;
460 u8 synd;
461 __be16 ext_synd;
462};
463
464struct mlx5_init_seg {
465 __be32 fw_rev;
466 __be32 cmdif_rev_fw_sub;
467 __be32 rsvd0[2];
468 __be32 cmdq_addr_h;
469 __be32 cmdq_addr_l_sz;
470 __be32 cmd_dbell;
471 __be32 rsvd1[120];
472 __be32 initializing;
473 struct health_buffer health;
474 __be32 rsvd2[880];
475 __be32 internal_timer_h;
476 __be32 internal_timer_l;
477 __be32 rsvd3[2];
478 __be32 health_counter;
479 __be32 rsvd4[1019];
480 __be64 ieee1588_clk;
481 __be32 ieee1588_clk_type;
482 __be32 clr_intx;
483};
484
485struct mlx5_eqe_comp {
486 __be32 reserved[6];
487 __be32 cqn;
488};
489
490struct mlx5_eqe_qp_srq {
491 __be32 reserved1[5];
492 u8 type;
493 u8 reserved2[3];
494 __be32 qp_srq_n;
495};
496
497struct mlx5_eqe_cq_err {
498 __be32 cqn;
499 u8 reserved1[7];
500 u8 syndrome;
501};
502
503struct mlx5_eqe_port_state {
504 u8 reserved0[8];
505 u8 port;
506};
507
508struct mlx5_eqe_gpio {
509 __be32 reserved0[2];
510 __be64 gpio_event;
511};
512
513struct mlx5_eqe_congestion {
514 u8 type;
515 u8 rsvd0;
516 u8 congestion_level;
517};
518
519struct mlx5_eqe_stall_vl {
520 u8 rsvd0[3];
521 u8 port_vl;
522};
523
524struct mlx5_eqe_cmd {
525 __be32 vector;
526 __be32 rsvd[6];
527};
528
529struct mlx5_eqe_page_req {
530 u8 rsvd0[2];
531 __be16 func_id;
532 __be32 num_pages;
533 __be32 rsvd1[5];
534};
535
536struct mlx5_eqe_page_fault {
537 __be32 bytes_committed;
538 union {
539 struct {
540 u16 reserved1;
541 __be16 wqe_index;
542 u16 reserved2;
543 __be16 packet_length;
544 __be32 token;
545 u8 reserved4[8];
546 __be32 pftype_wq;
547 } __packed wqe;
548 struct {
549 __be32 r_key;
550 u16 reserved1;
551 __be16 packet_length;
552 __be32 rdma_op_len;
553 __be64 rdma_va;
554 __be32 pftype_token;
555 } __packed rdma;
556 } __packed;
557} __packed;
558
559struct mlx5_eqe_vport_change {
560 u8 rsvd0[2];
561 __be16 vport_num;
562 __be32 rsvd1[6];
563} __packed;
564
565struct mlx5_eqe_port_module {
566 u8 reserved_at_0[1];
567 u8 module;
568 u8 reserved_at_2[1];
569 u8 module_status;
570 u8 reserved_at_4[2];
571 u8 error_type;
572} __packed;
573
574struct mlx5_eqe_pps {
575 u8 rsvd0[3];
576 u8 pin;
577 u8 rsvd1[4];
578 union {
579 struct {
580 __be32 time_sec;
581 __be32 time_nsec;
582 };
583 struct {
584 __be64 time_stamp;
585 };
586 };
587 u8 rsvd2[12];
588} __packed;
589
590union ev_data {
591 __be32 raw[7];
592 struct mlx5_eqe_cmd cmd;
593 struct mlx5_eqe_comp comp;
594 struct mlx5_eqe_qp_srq qp_srq;
595 struct mlx5_eqe_cq_err cq_err;
596 struct mlx5_eqe_port_state port;
597 struct mlx5_eqe_gpio gpio;
598 struct mlx5_eqe_congestion cong;
599 struct mlx5_eqe_stall_vl stall_vl;
600 struct mlx5_eqe_page_req req_pages;
601 struct mlx5_eqe_page_fault page_fault;
602 struct mlx5_eqe_vport_change vport_change;
603 struct mlx5_eqe_port_module port_module;
604 struct mlx5_eqe_pps pps;
605} __packed;
606
607struct mlx5_eqe {
608 u8 rsvd0;
609 u8 type;
610 u8 rsvd1;
611 u8 sub_type;
612 __be32 rsvd2[7];
613 union ev_data data;
614 __be16 rsvd3;
615 u8 signature;
616 u8 owner;
617} __packed;
618
619struct mlx5_cmd_prot_block {
620 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
621 u8 rsvd0[48];
622 __be64 next;
623 __be32 block_num;
624 u8 rsvd1;
625 u8 token;
626 u8 ctrl_sig;
627 u8 sig;
628};
629
630enum {
631 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
632};
633
634struct mlx5_err_cqe {
635 u8 rsvd0[32];
636 __be32 srqn;
637 u8 rsvd1[18];
638 u8 vendor_err_synd;
639 u8 syndrome;
640 __be32 s_wqe_opcode_qpn;
641 __be16 wqe_counter;
642 u8 signature;
643 u8 op_own;
644};
645
646struct mlx5_cqe64 {
647 u8 outer_l3_tunneled;
648 u8 rsvd0;
649 __be16 wqe_id;
650 u8 lro_tcppsh_abort_dupack;
651 u8 lro_min_ttl;
652 __be16 lro_tcp_win;
653 __be32 lro_ack_seq_num;
654 __be32 rss_hash_result;
655 u8 rss_hash_type;
656 u8 ml_path;
657 u8 rsvd20[2];
658 __be16 check_sum;
659 __be16 slid;
660 __be32 flags_rqpn;
661 u8 hds_ip_ext;
662 u8 l4_l3_hdr_type;
663 __be16 vlan_info;
664 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
665 __be32 imm_inval_pkey;
666 u8 rsvd40[4];
667 __be32 byte_cnt;
668 __be32 timestamp_h;
669 __be32 timestamp_l;
670 __be32 sop_drop_qpn;
671 __be16 wqe_counter;
672 u8 signature;
673 u8 op_own;
674};
675
676struct mlx5_mini_cqe8 {
677 union {
678 __be32 rx_hash_result;
679 struct {
680 __be16 checksum;
681 __be16 rsvd;
682 };
683 struct {
684 __be16 wqe_counter;
685 u8 s_wqe_opcode;
686 u8 reserved;
687 } s_wqe_info;
688 };
689 __be32 byte_cnt;
690};
691
692enum {
693 MLX5_NO_INLINE_DATA,
694 MLX5_INLINE_DATA32_SEG,
695 MLX5_INLINE_DATA64_SEG,
696 MLX5_COMPRESSED,
697};
698
699enum {
700 MLX5_CQE_FORMAT_CSUM = 0x1,
701};
702
703#define MLX5_MINI_CQE_ARRAY_SIZE 8
704
705static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
706{
707 return (cqe->op_own >> 2) & 0x3;
708}
709
710static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
711{
712 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
713}
714
715static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
716{
717 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
718}
719
720static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
721{
722 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
723}
724
725static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
726{
727 return cqe->outer_l3_tunneled & 0x1;
728}
729
730static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
731{
732 return !!(cqe->l4_l3_hdr_type & 0x1);
733}
734
735static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
736{
737 u32 hi, lo;
738
739 hi = be32_to_cpu(cqe->timestamp_h);
740 lo = be32_to_cpu(cqe->timestamp_l);
741
742 return (u64)lo | ((u64)hi << 32);
743}
744
745struct mpwrq_cqe_bc {
746 __be16 filler_consumed_strides;
747 __be16 byte_cnt;
748};
749
750static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
751{
752 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
753
754 return be16_to_cpu(bc->byte_cnt);
755}
756
757static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
758{
759 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
760}
761
762static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
763{
764 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
765
766 return mpwrq_get_cqe_bc_consumed_strides(bc);
767}
768
769static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
770{
771 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
772
773 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
774}
775
776static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
777{
778 return be16_to_cpu(cqe->wqe_counter);
779}
780
781enum {
782 CQE_L4_HDR_TYPE_NONE = 0x0,
783 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
784 CQE_L4_HDR_TYPE_UDP = 0x2,
785 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
786 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
787};
788
789enum {
790 CQE_RSS_HTYPE_IP = 0x3 << 6,
791 CQE_RSS_HTYPE_L4 = 0x3 << 2,
792};
793
794enum {
795 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
796 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
797 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
798};
799
800enum {
801 CQE_L2_OK = 1 << 0,
802 CQE_L3_OK = 1 << 1,
803 CQE_L4_OK = 1 << 2,
804};
805
806struct mlx5_sig_err_cqe {
807 u8 rsvd0[16];
808 __be32 expected_trans_sig;
809 __be32 actual_trans_sig;
810 __be32 expected_reftag;
811 __be32 actual_reftag;
812 __be16 syndrome;
813 u8 rsvd22[2];
814 __be32 mkey;
815 __be64 err_offset;
816 u8 rsvd30[8];
817 __be32 qpn;
818 u8 rsvd38[2];
819 u8 signature;
820 u8 op_own;
821};
822
823struct mlx5_wqe_srq_next_seg {
824 u8 rsvd0[2];
825 __be16 next_wqe_index;
826 u8 signature;
827 u8 rsvd1[11];
828};
829
830union mlx5_ext_cqe {
831 struct ib_grh grh;
832 u8 inl[64];
833};
834
835struct mlx5_cqe128 {
836 union mlx5_ext_cqe inl_grh;
837 struct mlx5_cqe64 cqe64;
838};
839
840enum {
841 MLX5_MKEY_STATUS_FREE = 1 << 6,
842};
843
844enum {
845 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
846 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
847 MLX5_MKEY_BSF_EN = 1 << 30,
848 MLX5_MKEY_LEN64 = 1 << 31,
849};
850
851struct mlx5_mkey_seg {
852 /* This is a two bit field occupying bits 31-30.
853 * bit 31 is always 0,
854 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
855 */
856 u8 status;
857 u8 pcie_control;
858 u8 flags;
859 u8 version;
860 __be32 qpn_mkey7_0;
861 u8 rsvd1[4];
862 __be32 flags_pd;
863 __be64 start_addr;
864 __be64 len;
865 __be32 bsfs_octo_size;
866 u8 rsvd2[16];
867 __be32 xlt_oct_size;
868 u8 rsvd3[3];
869 u8 log2_page_size;
870 u8 rsvd4[4];
871};
872
873#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
874
875enum {
876 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
877};
878
879enum {
880 VPORT_STATE_DOWN = 0x0,
881 VPORT_STATE_UP = 0x1,
882};
883
884enum {
885 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
886 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
887 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
888};
889
890enum {
891 MLX5_L3_PROT_TYPE_IPV4 = 0,
892 MLX5_L3_PROT_TYPE_IPV6 = 1,
893};
894
895enum {
896 MLX5_L4_PROT_TYPE_TCP = 0,
897 MLX5_L4_PROT_TYPE_UDP = 1,
898};
899
900enum {
901 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
902 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
903 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
904 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
905 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
906};
907
908enum {
909 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
910 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
911 MLX5_MATCH_INNER_HEADERS = 1 << 2,
912
913};
914
915enum {
916 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
917 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
918};
919
920enum {
921 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
922 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
923 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
924};
925
926enum mlx5_list_type {
927 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
928 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
929 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
930};
931
932enum {
933 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
934 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
935};
936
937enum mlx5_wol_mode {
938 MLX5_WOL_DISABLE = 0,
939 MLX5_WOL_SECURED_MAGIC = 1 << 1,
940 MLX5_WOL_MAGIC = 1 << 2,
941 MLX5_WOL_ARP = 1 << 3,
942 MLX5_WOL_BROADCAST = 1 << 4,
943 MLX5_WOL_MULTICAST = 1 << 5,
944 MLX5_WOL_UNICAST = 1 << 6,
945 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
946};
947
948/* MLX5 DEV CAPs */
949
950/* TODO: EAT.ME */
951enum mlx5_cap_mode {
952 HCA_CAP_OPMOD_GET_MAX = 0,
953 HCA_CAP_OPMOD_GET_CUR = 1,
954};
955
956enum mlx5_cap_type {
957 MLX5_CAP_GENERAL = 0,
958 MLX5_CAP_ETHERNET_OFFLOADS,
959 MLX5_CAP_ODP,
960 MLX5_CAP_ATOMIC,
961 MLX5_CAP_ROCE,
962 MLX5_CAP_IPOIB_OFFLOADS,
963 MLX5_CAP_EOIB_OFFLOADS,
964 MLX5_CAP_FLOW_TABLE,
965 MLX5_CAP_ESWITCH_FLOW_TABLE,
966 MLX5_CAP_ESWITCH,
967 MLX5_CAP_RESERVED,
968 MLX5_CAP_VECTOR_CALC,
969 MLX5_CAP_QOS,
970 /* NUM OF CAP Types */
971 MLX5_CAP_NUM
972};
973
974enum mlx5_pcam_reg_groups {
975 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
976};
977
978enum mlx5_pcam_feature_groups {
979 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
980};
981
982enum mlx5_mcam_reg_groups {
983 MLX5_MCAM_REGS_FIRST_128 = 0x0,
984};
985
986enum mlx5_mcam_feature_groups {
987 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
988};
989
990/* GET Dev Caps macros */
991#define MLX5_CAP_GEN(mdev, cap) \
992 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
993
994#define MLX5_CAP_GEN_MAX(mdev, cap) \
995 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
996
997#define MLX5_CAP_ETH(mdev, cap) \
998 MLX5_GET(per_protocol_networking_offload_caps,\
999 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1000
1001#define MLX5_CAP_ETH_MAX(mdev, cap) \
1002 MLX5_GET(per_protocol_networking_offload_caps,\
1003 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1004
1005#define MLX5_CAP_ROCE(mdev, cap) \
1006 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
1007
1008#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1009 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
1010
1011#define MLX5_CAP_ATOMIC(mdev, cap) \
1012 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
1013
1014#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1015 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
1016
1017#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1018 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1019
1020#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1021 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1022
1023#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1024 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1025
1026#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1027 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1028
1029#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1030 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1031
1032#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
1033 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1034
1035#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1036 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1037
1038#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1039 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1040
1041#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1042 MLX5_GET(flow_table_eswitch_cap, \
1043 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1044
1045#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1046 MLX5_GET(flow_table_eswitch_cap, \
1047 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1048
1049#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1050 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1051
1052#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1053 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1054
1055#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1056 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1057
1058#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1059 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1060
1061#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1062 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1063
1064#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1065 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1066
1067#define MLX5_CAP_ESW(mdev, cap) \
1068 MLX5_GET(e_switch_cap, \
1069 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1070
1071#define MLX5_CAP_ESW_MAX(mdev, cap) \
1072 MLX5_GET(e_switch_cap, \
1073 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
1074
1075#define MLX5_CAP_ODP(mdev, cap)\
1076 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1077
1078#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1079 MLX5_GET(vector_calc_cap, \
1080 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
1081
1082#define MLX5_CAP_QOS(mdev, cap)\
1083 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1084
1085#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1086 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1087
1088#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1089 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1090
1091enum {
1092 MLX5_CMD_STAT_OK = 0x0,
1093 MLX5_CMD_STAT_INT_ERR = 0x1,
1094 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1095 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1096 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1097 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1098 MLX5_CMD_STAT_RES_BUSY = 0x6,
1099 MLX5_CMD_STAT_LIM_ERR = 0x8,
1100 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1101 MLX5_CMD_STAT_IX_ERR = 0xa,
1102 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1103 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1104 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1105 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1106 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1107 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1108};
1109
1110enum {
1111 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1112 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1113 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1114 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1115 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1116 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1117 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1118 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1119 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1120 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1121};
1122
1123enum {
1124 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1125};
1126
1127static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1128{
1129 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1130 return 0;
1131 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1132}
1133
1134#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1135#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1136#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1137#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1138 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1139 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1140
1141#endif /* MLX5_DEVICE_H */