tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Exynos5 SoC series Power Management Unit (PMU) register offsets
3 * and bit definitions.
4 *
5 * Copyright (C) 2014 Samsung Electronics Co., Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_
13#define _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_
14
15/* Exynos5 PMU register definitions */
16#define EXYNOS5_HDMI_PHY_CONTROL (0x700)
17#define EXYNOS5_USBDRD_PHY_CONTROL (0x704)
18
19/* Exynos5250 specific register definitions */
20#define EXYNOS5_USBHOST_PHY_CONTROL (0x708)
21#define EXYNOS5_EFNAND_PHY_CONTROL (0x70c)
22#define EXYNOS5_MIPI_PHY0_CONTROL (0x710)
23#define EXYNOS5_MIPI_PHY1_CONTROL (0x714)
24#define EXYNOS5_ADC_PHY_CONTROL (0x718)
25#define EXYNOS5_MTCADC_PHY_CONTROL (0x71c)
26#define EXYNOS5_DPTX_PHY_CONTROL (0x720)
27#define EXYNOS5_SATA_PHY_CONTROL (0x724)
28
29/* Exynos5420 specific register definitions */
30#define EXYNOS5420_USBDRD1_PHY_CONTROL (0x708)
31#define EXYNOS5420_USBHOST_PHY_CONTROL (0x70c)
32#define EXYNOS5420_MIPI_PHY0_CONTROL (0x714)
33#define EXYNOS5420_MIPI_PHY1_CONTROL (0x718)
34#define EXYNOS5420_MIPI_PHY2_CONTROL (0x71c)
35#define EXYNOS5420_ADC_PHY_CONTROL (0x720)
36#define EXYNOS5420_MTCADC_PHY_CONTROL (0x724)
37#define EXYNOS5420_DPTX_PHY_CONTROL (0x728)
38
39/* Exynos5433 specific register definitions */
40#define EXYNOS5433_USBHOST30_PHY_CONTROL (0x728)
41#define EXYNOS5433_MIPI_PHY0_CONTROL (0x710)
42#define EXYNOS5433_MIPI_PHY1_CONTROL (0x714)
43#define EXYNOS5433_MIPI_PHY2_CONTROL (0x718)
44
45#define EXYNOS5_PHY_ENABLE BIT(0)
46#define EXYNOS5_MIPI_PHY_S_RESETN BIT(1)
47#define EXYNOS5_MIPI_PHY_M_RESETN BIT(2)
48
49#define EXYNOS5433_PAD_RETENTION_AUD_OPTION (0x3028)
50#define EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR BIT(28)
51
52#endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */