tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Author: Daniel Thompson <daniel.thompson@linaro.org>
3 *
4 * Inspired by clk-asm9260.c .
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/clk-provider.h>
20#include <linux/err.h>
21#include <linux/io.h>
22#include <linux/iopoll.h>
23#include <linux/ioport.h>
24#include <linux/slab.h>
25#include <linux/spinlock.h>
26#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/regmap.h>
29#include <linux/mfd/syscon.h>
30
31/*
32 * Include list of clocks wich are not derived from system clock (SYSCLOCK)
33 * The index of these clocks is the secondary index of DT bindings
34 *
35 */
36#include <dt-bindings/clock/stm32fx-clock.h>
37
38#define STM32F4_RCC_CR 0x00
39#define STM32F4_RCC_PLLCFGR 0x04
40#define STM32F4_RCC_CFGR 0x08
41#define STM32F4_RCC_AHB1ENR 0x30
42#define STM32F4_RCC_AHB2ENR 0x34
43#define STM32F4_RCC_AHB3ENR 0x38
44#define STM32F4_RCC_APB1ENR 0x40
45#define STM32F4_RCC_APB2ENR 0x44
46#define STM32F4_RCC_BDCR 0x70
47#define STM32F4_RCC_CSR 0x74
48#define STM32F4_RCC_PLLI2SCFGR 0x84
49#define STM32F4_RCC_PLLSAICFGR 0x88
50#define STM32F4_RCC_DCKCFGR 0x8c
51#define STM32F7_RCC_DCKCFGR2 0x90
52
53#define NONE -1
54#define NO_IDX NONE
55#define NO_MUX NONE
56#define NO_GATE NONE
57
58struct stm32f4_gate_data {
59 u8 offset;
60 u8 bit_idx;
61 const char *name;
62 const char *parent_name;
63 unsigned long flags;
64};
65
66static const struct stm32f4_gate_data stm32f429_gates[] __initconst = {
67 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
68 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
69 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
70 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
71 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
72 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
73 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
74 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
75 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
76 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
77 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
78 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
79 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
80 { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
81 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
82 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
83 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
84 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
85 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
86 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
87 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
88 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
89 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
90
91 { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
92 { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
93 { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
94 { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
95 { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
96
97 { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
98 CLK_IGNORE_UNUSED },
99
100 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
101 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
102 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
103 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
104 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
105 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
106 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
107 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
108 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
109 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
110 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
111 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
112 { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
113 { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
114 { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
115 { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
116 { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
117 { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
118 { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
119 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
120 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
121 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
122 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
123 { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
124 { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },
125
126 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
127 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
128 { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" },
129 { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" },
130 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
131 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
132 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
133 { STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" },
134 { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
135 { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
136 { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
137 { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
138 { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
139 { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
140 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
141 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
142 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
143 { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
144};
145
146static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
147 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
148 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
149 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
150 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
151 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
152 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
153 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
154 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
155 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
156 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
157 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
158 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
159 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
160 { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
161 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
162 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
163 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
164 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
165 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
166 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
167 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
168 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
169 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
170
171 { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
172 { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
173 { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
174 { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
175 { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
176
177 { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
178 CLK_IGNORE_UNUSED },
179 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
180 CLK_IGNORE_UNUSED },
181
182 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
183 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
184 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
185 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
186 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
187 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
188 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
189 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
190 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
191 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
192 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
193 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
194 { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
195 { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
196 { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
197 { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
198 { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
199 { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
200 { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
201 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
202 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
203 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
204 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
205 { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
206 { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },
207
208 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
209 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
210 { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" },
211 { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" },
212 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
213 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
214 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
215 { STM32F4_RCC_APB2ENR, 11, "sdio", "sdmux" },
216 { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
217 { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
218 { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
219 { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
220 { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
221 { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
222 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
223 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
224 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
225 { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
226};
227
228static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
229 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
230 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
231 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
232 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
233 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
234 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
235 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
236 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
237 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
238 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
239 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
240 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
241 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
242 { STM32F4_RCC_AHB1ENR, 20, "dtcmram", "ahb_div" },
243 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
244 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
245 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
246 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
247 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
248 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
249 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
250 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
251 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
252
253 { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
254 { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
255 { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
256 { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
257 { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
258
259 { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
260 CLK_IGNORE_UNUSED },
261 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
262 CLK_IGNORE_UNUSED },
263
264 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
265 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
266 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
267 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
268 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
269 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
270 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
271 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
272 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
273 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
274 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
275 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
276 { STM32F4_RCC_APB1ENR, 16, "spdifrx", "apb1_div" },
277 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
278 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
279 { STM32F4_RCC_APB1ENR, 27, "cec", "apb1_div" },
280 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
281 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
282
283 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
284 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
285 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
286 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
287 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
288 { STM32F4_RCC_APB2ENR, 11, "sdmmc", "sdmux" },
289 { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
290 { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
291 { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
292 { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
293 { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
294 { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
295 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
296 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
297 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
298 { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" },
299 { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
300};
301
302/*
303 * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
304 * have gate bits associated with them. Its combined hweight is 71.
305 */
306#define MAX_GATE_MAP 3
307
308static const u64 stm32f42xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
309 0x0000000000000001ull,
310 0x04777f33f6fec9ffull };
311
312static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
313 0x0000000000000003ull,
314 0x0c777f33f6fec9ffull };
315
316static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
317 0x0000000000000003ull,
318 0x04f77f033e01c9ffull };
319
320static const u64 *stm32f4_gate_map;
321
322static struct clk_hw **clks;
323
324static DEFINE_SPINLOCK(stm32f4_clk_lock);
325static void __iomem *base;
326
327static struct regmap *pdrm;
328
329static int stm32fx_end_primary_clk;
330
331/*
332 * "Multiplier" device for APBx clocks.
333 *
334 * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
335 * mode, they also tap out the one of the low order state bits to run the
336 * timers. ST datasheets represent this feature as a (conditional) clock
337 * multiplier.
338 */
339struct clk_apb_mul {
340 struct clk_hw hw;
341 u8 bit_idx;
342};
343
344#define to_clk_apb_mul(_hw) container_of(_hw, struct clk_apb_mul, hw)
345
346static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw,
347 unsigned long parent_rate)
348{
349 struct clk_apb_mul *am = to_clk_apb_mul(hw);
350
351 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
352 return parent_rate * 2;
353
354 return parent_rate;
355}
356
357static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,
358 unsigned long *prate)
359{
360 struct clk_apb_mul *am = to_clk_apb_mul(hw);
361 unsigned long mult = 1;
362
363 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
364 mult = 2;
365
366 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
367 unsigned long best_parent = rate / mult;
368
369 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
370 }
371
372 return *prate * mult;
373}
374
375static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate,
376 unsigned long parent_rate)
377{
378 /*
379 * We must report success but we can do so unconditionally because
380 * clk_apb_mul_round_rate returns values that ensure this call is a
381 * nop.
382 */
383
384 return 0;
385}
386
387static const struct clk_ops clk_apb_mul_factor_ops = {
388 .round_rate = clk_apb_mul_round_rate,
389 .set_rate = clk_apb_mul_set_rate,
390 .recalc_rate = clk_apb_mul_recalc_rate,
391};
392
393static struct clk *clk_register_apb_mul(struct device *dev, const char *name,
394 const char *parent_name,
395 unsigned long flags, u8 bit_idx)
396{
397 struct clk_apb_mul *am;
398 struct clk_init_data init;
399 struct clk *clk;
400
401 am = kzalloc(sizeof(*am), GFP_KERNEL);
402 if (!am)
403 return ERR_PTR(-ENOMEM);
404
405 am->bit_idx = bit_idx;
406 am->hw.init = &init;
407
408 init.name = name;
409 init.ops = &clk_apb_mul_factor_ops;
410 init.flags = flags;
411 init.parent_names = &parent_name;
412 init.num_parents = 1;
413
414 clk = clk_register(dev, &am->hw);
415
416 if (IS_ERR(clk))
417 kfree(am);
418
419 return clk;
420}
421
422enum {
423 PLL,
424 PLL_I2S,
425 PLL_SAI,
426};
427
428static const struct clk_div_table pll_divp_table[] = {
429 { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 }
430};
431
432static const struct clk_div_table pll_divq_table[] = {
433 { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 },
434 { 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 }, { 12, 12 }, { 13, 13 },
435 { 14, 14 }, { 15, 15 },
436 { 0 }
437};
438
439static const struct clk_div_table pll_divr_table[] = {
440 { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 }
441};
442
443struct stm32f4_pll {
444 spinlock_t *lock;
445 struct clk_gate gate;
446 u8 offset;
447 u8 bit_rdy_idx;
448 u8 status;
449 u8 n_start;
450};
451
452#define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate)
453
454struct stm32f4_pll_post_div_data {
455 int idx;
456 u8 pll_num;
457 const char *name;
458 const char *parent;
459 u8 flag;
460 u8 offset;
461 u8 shift;
462 u8 width;
463 u8 flag_div;
464 const struct clk_div_table *div_table;
465};
466
467struct stm32f4_vco_data {
468 const char *vco_name;
469 u8 offset;
470 u8 bit_idx;
471 u8 bit_rdy_idx;
472};
473
474static const struct stm32f4_vco_data vco_data[] = {
475 { "vco", STM32F4_RCC_PLLCFGR, 24, 25 },
476 { "vco-i2s", STM32F4_RCC_PLLI2SCFGR, 26, 27 },
477 { "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 },
478};
479
480
481static const struct clk_div_table post_divr_table[] = {
482 { 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 }, { 0 }
483};
484
485#define MAX_POST_DIV 3
486static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = {
487 { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q",
488 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
489
490 { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q",
491 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
492
493 { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
494 STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
495};
496
497struct stm32f4_div_data {
498 u8 shift;
499 u8 width;
500 u8 flag_div;
501 const struct clk_div_table *div_table;
502};
503
504#define MAX_PLL_DIV 3
505static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = {
506 { 16, 2, 0, pll_divp_table },
507 { 24, 4, 0, pll_divq_table },
508 { 28, 3, 0, pll_divr_table },
509};
510
511struct stm32f4_pll_data {
512 u8 pll_num;
513 u8 n_start;
514 const char *div_name[MAX_PLL_DIV];
515};
516
517static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = {
518 { PLL, 192, { "pll", "pll48", NULL } },
519 { PLL_I2S, 192, { NULL, "plli2s-q", "plli2s-r" } },
520 { PLL_SAI, 49, { NULL, "pllsai-q", "pllsai-r" } },
521};
522
523static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
524 { PLL, 50, { "pll", "pll-q", NULL } },
525 { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
526 { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
527};
528
529static int stm32f4_pll_is_enabled(struct clk_hw *hw)
530{
531 return clk_gate_ops.is_enabled(hw);
532}
533
534static int stm32f4_pll_enable(struct clk_hw *hw)
535{
536 struct clk_gate *gate = to_clk_gate(hw);
537 struct stm32f4_pll *pll = to_stm32f4_pll(gate);
538 int ret = 0;
539 unsigned long reg;
540
541 ret = clk_gate_ops.enable(hw);
542
543 ret = readl_relaxed_poll_timeout_atomic(base + STM32F4_RCC_CR, reg,
544 reg & (1 << pll->bit_rdy_idx), 0, 10000);
545
546 return ret;
547}
548
549static void stm32f4_pll_disable(struct clk_hw *hw)
550{
551 clk_gate_ops.disable(hw);
552}
553
554static unsigned long stm32f4_pll_recalc(struct clk_hw *hw,
555 unsigned long parent_rate)
556{
557 struct clk_gate *gate = to_clk_gate(hw);
558 struct stm32f4_pll *pll = to_stm32f4_pll(gate);
559 unsigned long n;
560
561 n = (readl(base + pll->offset) >> 6) & 0x1ff;
562
563 return parent_rate * n;
564}
565
566static long stm32f4_pll_round_rate(struct clk_hw *hw, unsigned long rate,
567 unsigned long *prate)
568{
569 struct clk_gate *gate = to_clk_gate(hw);
570 struct stm32f4_pll *pll = to_stm32f4_pll(gate);
571 unsigned long n;
572
573 n = rate / *prate;
574
575 if (n < pll->n_start)
576 n = pll->n_start;
577 else if (n > 432)
578 n = 432;
579
580 return *prate * n;
581}
582
583static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate,
584 unsigned long parent_rate)
585{
586 struct clk_gate *gate = to_clk_gate(hw);
587 struct stm32f4_pll *pll = to_stm32f4_pll(gate);
588
589 unsigned long n;
590 unsigned long val;
591 int pll_state;
592
593 pll_state = stm32f4_pll_is_enabled(hw);
594
595 if (pll_state)
596 stm32f4_pll_disable(hw);
597
598 n = rate / parent_rate;
599
600 val = readl(base + pll->offset) & ~(0x1ff << 6);
601
602 writel(val | ((n & 0x1ff) << 6), base + pll->offset);
603
604 if (pll_state)
605 stm32f4_pll_enable(hw);
606
607 return 0;
608}
609
610static const struct clk_ops stm32f4_pll_gate_ops = {
611 .enable = stm32f4_pll_enable,
612 .disable = stm32f4_pll_disable,
613 .is_enabled = stm32f4_pll_is_enabled,
614 .recalc_rate = stm32f4_pll_recalc,
615 .round_rate = stm32f4_pll_round_rate,
616 .set_rate = stm32f4_pll_set_rate,
617};
618
619struct stm32f4_pll_div {
620 struct clk_divider div;
621 struct clk_hw *hw_pll;
622};
623
624#define to_pll_div_clk(_div) container_of(_div, struct stm32f4_pll_div, div)
625
626static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw,
627 unsigned long parent_rate)
628{
629 return clk_divider_ops.recalc_rate(hw, parent_rate);
630}
631
632static long stm32f4_pll_div_round_rate(struct clk_hw *hw, unsigned long rate,
633 unsigned long *prate)
634{
635 return clk_divider_ops.round_rate(hw, rate, prate);
636}
637
638static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
639 unsigned long parent_rate)
640{
641 int pll_state, ret;
642
643 struct clk_divider *div = to_clk_divider(hw);
644 struct stm32f4_pll_div *pll_div = to_pll_div_clk(div);
645
646 pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll);
647
648 if (pll_state)
649 stm32f4_pll_disable(pll_div->hw_pll);
650
651 ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
652
653 if (pll_state)
654 stm32f4_pll_enable(pll_div->hw_pll);
655
656 return ret;
657}
658
659static const struct clk_ops stm32f4_pll_div_ops = {
660 .recalc_rate = stm32f4_pll_div_recalc_rate,
661 .round_rate = stm32f4_pll_div_round_rate,
662 .set_rate = stm32f4_pll_div_set_rate,
663};
664
665static struct clk_hw *clk_register_pll_div(const char *name,
666 const char *parent_name, unsigned long flags,
667 void __iomem *reg, u8 shift, u8 width,
668 u8 clk_divider_flags, const struct clk_div_table *table,
669 struct clk_hw *pll_hw, spinlock_t *lock)
670{
671 struct stm32f4_pll_div *pll_div;
672 struct clk_hw *hw;
673 struct clk_init_data init;
674 int ret;
675
676 /* allocate the divider */
677 pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL);
678 if (!pll_div)
679 return ERR_PTR(-ENOMEM);
680
681 init.name = name;
682 init.ops = &stm32f4_pll_div_ops;
683 init.flags = flags;
684 init.parent_names = (parent_name ? &parent_name : NULL);
685 init.num_parents = (parent_name ? 1 : 0);
686
687 /* struct clk_divider assignments */
688 pll_div->div.reg = reg;
689 pll_div->div.shift = shift;
690 pll_div->div.width = width;
691 pll_div->div.flags = clk_divider_flags;
692 pll_div->div.lock = lock;
693 pll_div->div.table = table;
694 pll_div->div.hw.init = &init;
695
696 pll_div->hw_pll = pll_hw;
697
698 /* register the clock */
699 hw = &pll_div->div.hw;
700 ret = clk_hw_register(NULL, hw);
701 if (ret) {
702 kfree(pll_div);
703 hw = ERR_PTR(ret);
704 }
705
706 return hw;
707}
708
709static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc,
710 const struct stm32f4_pll_data *data, spinlock_t *lock)
711{
712 struct stm32f4_pll *pll;
713 struct clk_init_data init = { NULL };
714 void __iomem *reg;
715 struct clk_hw *pll_hw;
716 int ret;
717 int i;
718 const struct stm32f4_vco_data *vco;
719
720
721 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
722 if (!pll)
723 return ERR_PTR(-ENOMEM);
724
725 vco = &vco_data[data->pll_num];
726
727 init.name = vco->vco_name;
728 init.ops = &stm32f4_pll_gate_ops;
729 init.flags = CLK_SET_RATE_GATE;
730 init.parent_names = &pllsrc;
731 init.num_parents = 1;
732
733 pll->gate.lock = lock;
734 pll->gate.reg = base + STM32F4_RCC_CR;
735 pll->gate.bit_idx = vco->bit_idx;
736 pll->gate.hw.init = &init;
737
738 pll->offset = vco->offset;
739 pll->n_start = data->n_start;
740 pll->bit_rdy_idx = vco->bit_rdy_idx;
741 pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1;
742
743 reg = base + pll->offset;
744
745 pll_hw = &pll->gate.hw;
746 ret = clk_hw_register(NULL, pll_hw);
747 if (ret) {
748 kfree(pll);
749 return ERR_PTR(ret);
750 }
751
752 for (i = 0; i < MAX_PLL_DIV; i++)
753 if (data->div_name[i])
754 clk_register_pll_div(data->div_name[i],
755 vco->vco_name,
756 0,
757 reg,
758 div_data[i].shift,
759 div_data[i].width,
760 div_data[i].flag_div,
761 div_data[i].div_table,
762 pll_hw,
763 lock);
764 return pll_hw;
765}
766
767/*
768 * Converts the primary and secondary indices (as they appear in DT) to an
769 * offset into our struct clock array.
770 */
771static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
772{
773 u64 table[MAX_GATE_MAP];
774
775 if (primary == 1) {
776 if (WARN_ON(secondary >= stm32fx_end_primary_clk))
777 return -EINVAL;
778 return secondary;
779 }
780
781 memcpy(table, stm32f4_gate_map, sizeof(table));
782
783 /* only bits set in table can be used as indices */
784 if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) ||
785 0 == (table[BIT_ULL_WORD(secondary)] &
786 BIT_ULL_MASK(secondary))))
787 return -EINVAL;
788
789 /* mask out bits above our current index */
790 table[BIT_ULL_WORD(secondary)] &=
791 GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0);
792
793 return stm32fx_end_primary_clk - 1 + hweight64(table[0]) +
794 (BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) +
795 (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0);
796}
797
798static struct clk_hw *
799stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data)
800{
801 int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]);
802
803 if (i < 0)
804 return ERR_PTR(-EINVAL);
805
806 return clks[i];
807}
808
809#define to_rgclk(_rgate) container_of(_rgate, struct stm32_rgate, gate)
810
811static inline void disable_power_domain_write_protection(void)
812{
813 if (pdrm)
814 regmap_update_bits(pdrm, 0x00, (1 << 8), (1 << 8));
815}
816
817static inline void enable_power_domain_write_protection(void)
818{
819 if (pdrm)
820 regmap_update_bits(pdrm, 0x00, (1 << 8), (0 << 8));
821}
822
823static inline void sofware_reset_backup_domain(void)
824{
825 unsigned long val;
826
827 val = readl(base + STM32F4_RCC_BDCR);
828 writel(val | BIT(16), base + STM32F4_RCC_BDCR);
829 writel(val & ~BIT(16), base + STM32F4_RCC_BDCR);
830}
831
832struct stm32_rgate {
833 struct clk_gate gate;
834 u8 bit_rdy_idx;
835};
836
837#define RTC_TIMEOUT 1000000
838
839static int rgclk_enable(struct clk_hw *hw)
840{
841 struct clk_gate *gate = to_clk_gate(hw);
842 struct stm32_rgate *rgate = to_rgclk(gate);
843 u32 reg;
844 int ret;
845
846 disable_power_domain_write_protection();
847
848 clk_gate_ops.enable(hw);
849
850 ret = readl_relaxed_poll_timeout_atomic(gate->reg, reg,
851 reg & rgate->bit_rdy_idx, 1000, RTC_TIMEOUT);
852
853 enable_power_domain_write_protection();
854 return ret;
855}
856
857static void rgclk_disable(struct clk_hw *hw)
858{
859 clk_gate_ops.disable(hw);
860}
861
862static int rgclk_is_enabled(struct clk_hw *hw)
863{
864 return clk_gate_ops.is_enabled(hw);
865}
866
867static const struct clk_ops rgclk_ops = {
868 .enable = rgclk_enable,
869 .disable = rgclk_disable,
870 .is_enabled = rgclk_is_enabled,
871};
872
873static struct clk_hw *clk_register_rgate(struct device *dev, const char *name,
874 const char *parent_name, unsigned long flags,
875 void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx,
876 u8 clk_gate_flags, spinlock_t *lock)
877{
878 struct stm32_rgate *rgate;
879 struct clk_init_data init = { NULL };
880 struct clk_hw *hw;
881 int ret;
882
883 rgate = kzalloc(sizeof(*rgate), GFP_KERNEL);
884 if (!rgate)
885 return ERR_PTR(-ENOMEM);
886
887 init.name = name;
888 init.ops = &rgclk_ops;
889 init.flags = flags;
890 init.parent_names = &parent_name;
891 init.num_parents = 1;
892
893 rgate->bit_rdy_idx = bit_rdy_idx;
894
895 rgate->gate.lock = lock;
896 rgate->gate.reg = reg;
897 rgate->gate.bit_idx = bit_idx;
898 rgate->gate.hw.init = &init;
899
900 hw = &rgate->gate.hw;
901 ret = clk_hw_register(dev, hw);
902 if (ret) {
903 kfree(rgate);
904 hw = ERR_PTR(ret);
905 }
906
907 return hw;
908}
909
910static int cclk_gate_enable(struct clk_hw *hw)
911{
912 int ret;
913
914 disable_power_domain_write_protection();
915
916 ret = clk_gate_ops.enable(hw);
917
918 enable_power_domain_write_protection();
919
920 return ret;
921}
922
923static void cclk_gate_disable(struct clk_hw *hw)
924{
925 disable_power_domain_write_protection();
926
927 clk_gate_ops.disable(hw);
928
929 enable_power_domain_write_protection();
930}
931
932static int cclk_gate_is_enabled(struct clk_hw *hw)
933{
934 return clk_gate_ops.is_enabled(hw);
935}
936
937static const struct clk_ops cclk_gate_ops = {
938 .enable = cclk_gate_enable,
939 .disable = cclk_gate_disable,
940 .is_enabled = cclk_gate_is_enabled,
941};
942
943static u8 cclk_mux_get_parent(struct clk_hw *hw)
944{
945 return clk_mux_ops.get_parent(hw);
946}
947
948static int cclk_mux_set_parent(struct clk_hw *hw, u8 index)
949{
950 int ret;
951
952 disable_power_domain_write_protection();
953
954 sofware_reset_backup_domain();
955
956 ret = clk_mux_ops.set_parent(hw, index);
957
958 enable_power_domain_write_protection();
959
960 return ret;
961}
962
963static const struct clk_ops cclk_mux_ops = {
964 .get_parent = cclk_mux_get_parent,
965 .set_parent = cclk_mux_set_parent,
966};
967
968static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
969 const char * const *parent_names, int num_parents,
970 void __iomem *reg, u8 bit_idx, u8 shift, unsigned long flags,
971 spinlock_t *lock)
972{
973 struct clk_hw *hw;
974 struct clk_gate *gate;
975 struct clk_mux *mux;
976
977 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
978 if (!gate) {
979 hw = ERR_PTR(-EINVAL);
980 goto fail;
981 }
982
983 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
984 if (!mux) {
985 kfree(gate);
986 hw = ERR_PTR(-EINVAL);
987 goto fail;
988 }
989
990 gate->reg = reg;
991 gate->bit_idx = bit_idx;
992 gate->flags = 0;
993 gate->lock = lock;
994
995 mux->reg = reg;
996 mux->shift = shift;
997 mux->mask = 3;
998 mux->flags = 0;
999
1000 hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
1001 &mux->hw, &cclk_mux_ops,
1002 NULL, NULL,
1003 &gate->hw, &cclk_gate_ops,
1004 flags);
1005
1006 if (IS_ERR(hw)) {
1007 kfree(gate);
1008 kfree(mux);
1009 }
1010
1011fail:
1012 return hw;
1013}
1014
1015static const char *sys_parents[] __initdata = { "hsi", NULL, "pll" };
1016
1017static const struct clk_div_table ahb_div_table[] = {
1018 { 0x0, 1 }, { 0x1, 1 }, { 0x2, 1 }, { 0x3, 1 },
1019 { 0x4, 1 }, { 0x5, 1 }, { 0x6, 1 }, { 0x7, 1 },
1020 { 0x8, 2 }, { 0x9, 4 }, { 0xa, 8 }, { 0xb, 16 },
1021 { 0xc, 64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 },
1022 { 0 },
1023};
1024
1025static const struct clk_div_table apb_div_table[] = {
1026 { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
1027 { 4, 2 }, { 5, 4 }, { 6, 8 }, { 7, 16 },
1028 { 0 },
1029};
1030
1031static const char *rtc_parents[4] = {
1032 "no-clock", "lse", "lsi", "hse-rtc"
1033};
1034
1035static const char *lcd_parent[1] = { "pllsai-r-div" };
1036
1037static const char *i2s_parents[2] = { "plli2s-r", NULL };
1038
1039static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL,
1040 "no-clock" };
1041
1042static const char *pll48_parents[2] = { "pll-q", "pllsai-p" };
1043
1044static const char *sdmux_parents[2] = { "pll48", "sys" };
1045
1046static const char *hdmi_parents[2] = { "lse", "hsi_div488" };
1047
1048static const char *spdif_parent[1] = { "plli2s-p" };
1049
1050static const char *lptim_parent[4] = { "apb1_mul", "lsi", "hsi", "lse" };
1051
1052static const char *uart_parents1[4] = { "apb2_div", "sys", "hsi", "lse" };
1053static const char *uart_parents2[4] = { "apb1_div", "sys", "hsi", "lse" };
1054
1055static const char *i2c_parents[4] = { "apb1_div", "sys", "hsi", "no-clock" };
1056
1057struct stm32_aux_clk {
1058 int idx;
1059 const char *name;
1060 const char * const *parent_names;
1061 int num_parents;
1062 int offset_mux;
1063 u8 shift;
1064 u8 mask;
1065 int offset_gate;
1066 u8 bit_idx;
1067 unsigned long flags;
1068};
1069
1070struct stm32f4_clk_data {
1071 const struct stm32f4_gate_data *gates_data;
1072 const u64 *gates_map;
1073 int gates_num;
1074 const struct stm32f4_pll_data *pll_data;
1075 const struct stm32_aux_clk *aux_clk;
1076 int aux_clk_num;
1077 int end_primary;
1078};
1079
1080static const struct stm32_aux_clk stm32f429_aux_clk[] = {
1081 {
1082 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1083 NO_MUX, 0, 0,
1084 STM32F4_RCC_APB2ENR, 26,
1085 CLK_SET_RATE_PARENT
1086 },
1087 {
1088 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1089 STM32F4_RCC_CFGR, 23, 1,
1090 NO_GATE, 0,
1091 CLK_SET_RATE_PARENT
1092 },
1093 {
1094 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1095 STM32F4_RCC_DCKCFGR, 20, 3,
1096 STM32F4_RCC_APB2ENR, 22,
1097 CLK_SET_RATE_PARENT
1098 },
1099 {
1100 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1101 STM32F4_RCC_DCKCFGR, 22, 3,
1102 STM32F4_RCC_APB2ENR, 22,
1103 CLK_SET_RATE_PARENT
1104 },
1105};
1106
1107static const struct stm32_aux_clk stm32f469_aux_clk[] = {
1108 {
1109 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1110 NO_MUX, 0, 0,
1111 STM32F4_RCC_APB2ENR, 26,
1112 CLK_SET_RATE_PARENT
1113 },
1114 {
1115 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1116 STM32F4_RCC_CFGR, 23, 1,
1117 NO_GATE, 0,
1118 CLK_SET_RATE_PARENT
1119 },
1120 {
1121 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1122 STM32F4_RCC_DCKCFGR, 20, 3,
1123 STM32F4_RCC_APB2ENR, 22,
1124 CLK_SET_RATE_PARENT
1125 },
1126 {
1127 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1128 STM32F4_RCC_DCKCFGR, 22, 3,
1129 STM32F4_RCC_APB2ENR, 22,
1130 CLK_SET_RATE_PARENT
1131 },
1132 {
1133 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1134 STM32F4_RCC_DCKCFGR, 27, 1,
1135 NO_GATE, 0,
1136 0
1137 },
1138 {
1139 NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1140 STM32F4_RCC_DCKCFGR, 28, 1,
1141 NO_GATE, 0,
1142 0
1143 },
1144};
1145
1146static const struct stm32_aux_clk stm32f746_aux_clk[] = {
1147 {
1148 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1149 NO_MUX, 0, 0,
1150 STM32F4_RCC_APB2ENR, 26,
1151 CLK_SET_RATE_PARENT
1152 },
1153 {
1154 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1155 STM32F4_RCC_CFGR, 23, 1,
1156 NO_GATE, 0,
1157 CLK_SET_RATE_PARENT
1158 },
1159 {
1160 CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents),
1161 STM32F4_RCC_DCKCFGR, 20, 3,
1162 STM32F4_RCC_APB2ENR, 22,
1163 CLK_SET_RATE_PARENT
1164 },
1165 {
1166 CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents),
1167 STM32F4_RCC_DCKCFGR, 22, 3,
1168 STM32F4_RCC_APB2ENR, 23,
1169 CLK_SET_RATE_PARENT
1170 },
1171 {
1172 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1173 STM32F7_RCC_DCKCFGR2, 27, 1,
1174 NO_GATE, 0,
1175 0
1176 },
1177 {
1178 NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1179 STM32F7_RCC_DCKCFGR2, 28, 1,
1180 NO_GATE, 0,
1181 0
1182 },
1183 {
1184 CLK_HDMI_CEC, "hdmi-cec",
1185 hdmi_parents, ARRAY_SIZE(hdmi_parents),
1186 STM32F7_RCC_DCKCFGR2, 26, 1,
1187 NO_GATE, 0,
1188 0
1189 },
1190 {
1191 CLK_SPDIF, "spdif-rx",
1192 spdif_parent, ARRAY_SIZE(spdif_parent),
1193 STM32F7_RCC_DCKCFGR2, 22, 3,
1194 STM32F4_RCC_APB2ENR, 23,
1195 CLK_SET_RATE_PARENT
1196 },
1197 {
1198 CLK_USART1, "usart1",
1199 uart_parents1, ARRAY_SIZE(uart_parents1),
1200 STM32F7_RCC_DCKCFGR2, 0, 3,
1201 STM32F4_RCC_APB2ENR, 4,
1202 CLK_SET_RATE_PARENT,
1203 },
1204 {
1205 CLK_USART2, "usart2",
1206 uart_parents2, ARRAY_SIZE(uart_parents1),
1207 STM32F7_RCC_DCKCFGR2, 2, 3,
1208 STM32F4_RCC_APB1ENR, 17,
1209 CLK_SET_RATE_PARENT,
1210 },
1211 {
1212 CLK_USART3, "usart3",
1213 uart_parents2, ARRAY_SIZE(uart_parents1),
1214 STM32F7_RCC_DCKCFGR2, 4, 3,
1215 STM32F4_RCC_APB1ENR, 18,
1216 CLK_SET_RATE_PARENT,
1217 },
1218 {
1219 CLK_UART4, "uart4",
1220 uart_parents2, ARRAY_SIZE(uart_parents1),
1221 STM32F7_RCC_DCKCFGR2, 6, 3,
1222 STM32F4_RCC_APB1ENR, 19,
1223 CLK_SET_RATE_PARENT,
1224 },
1225 {
1226 CLK_UART5, "uart5",
1227 uart_parents2, ARRAY_SIZE(uart_parents1),
1228 STM32F7_RCC_DCKCFGR2, 8, 3,
1229 STM32F4_RCC_APB1ENR, 20,
1230 CLK_SET_RATE_PARENT,
1231 },
1232 {
1233 CLK_USART6, "usart6",
1234 uart_parents1, ARRAY_SIZE(uart_parents1),
1235 STM32F7_RCC_DCKCFGR2, 10, 3,
1236 STM32F4_RCC_APB2ENR, 5,
1237 CLK_SET_RATE_PARENT,
1238 },
1239
1240 {
1241 CLK_UART7, "uart7",
1242 uart_parents2, ARRAY_SIZE(uart_parents1),
1243 STM32F7_RCC_DCKCFGR2, 12, 3,
1244 STM32F4_RCC_APB1ENR, 30,
1245 CLK_SET_RATE_PARENT,
1246 },
1247 {
1248 CLK_UART8, "uart8",
1249 uart_parents2, ARRAY_SIZE(uart_parents1),
1250 STM32F7_RCC_DCKCFGR2, 14, 3,
1251 STM32F4_RCC_APB1ENR, 31,
1252 CLK_SET_RATE_PARENT,
1253 },
1254 {
1255 CLK_I2C1, "i2c1",
1256 i2c_parents, ARRAY_SIZE(i2c_parents),
1257 STM32F7_RCC_DCKCFGR2, 16, 3,
1258 STM32F4_RCC_APB1ENR, 21,
1259 CLK_SET_RATE_PARENT,
1260 },
1261 {
1262 CLK_I2C2, "i2c2",
1263 i2c_parents, ARRAY_SIZE(i2c_parents),
1264 STM32F7_RCC_DCKCFGR2, 18, 3,
1265 STM32F4_RCC_APB1ENR, 22,
1266 CLK_SET_RATE_PARENT,
1267 },
1268 {
1269 CLK_I2C3, "i2c3",
1270 i2c_parents, ARRAY_SIZE(i2c_parents),
1271 STM32F7_RCC_DCKCFGR2, 20, 3,
1272 STM32F4_RCC_APB1ENR, 23,
1273 CLK_SET_RATE_PARENT,
1274 },
1275 {
1276 CLK_I2C4, "i2c4",
1277 i2c_parents, ARRAY_SIZE(i2c_parents),
1278 STM32F7_RCC_DCKCFGR2, 22, 3,
1279 STM32F4_RCC_APB1ENR, 24,
1280 CLK_SET_RATE_PARENT,
1281 },
1282
1283 {
1284 CLK_LPTIMER, "lptim1",
1285 lptim_parent, ARRAY_SIZE(lptim_parent),
1286 STM32F7_RCC_DCKCFGR2, 24, 3,
1287 STM32F4_RCC_APB1ENR, 9,
1288 CLK_SET_RATE_PARENT
1289 },
1290};
1291
1292static const struct stm32f4_clk_data stm32f429_clk_data = {
1293 .end_primary = END_PRIMARY_CLK,
1294 .gates_data = stm32f429_gates,
1295 .gates_map = stm32f42xx_gate_map,
1296 .gates_num = ARRAY_SIZE(stm32f429_gates),
1297 .pll_data = stm32f429_pll,
1298 .aux_clk = stm32f429_aux_clk,
1299 .aux_clk_num = ARRAY_SIZE(stm32f429_aux_clk),
1300};
1301
1302static const struct stm32f4_clk_data stm32f469_clk_data = {
1303 .end_primary = END_PRIMARY_CLK,
1304 .gates_data = stm32f469_gates,
1305 .gates_map = stm32f46xx_gate_map,
1306 .gates_num = ARRAY_SIZE(stm32f469_gates),
1307 .pll_data = stm32f469_pll,
1308 .aux_clk = stm32f469_aux_clk,
1309 .aux_clk_num = ARRAY_SIZE(stm32f469_aux_clk),
1310};
1311
1312static const struct stm32f4_clk_data stm32f746_clk_data = {
1313 .end_primary = END_PRIMARY_CLK_F7,
1314 .gates_data = stm32f746_gates,
1315 .gates_map = stm32f746_gate_map,
1316 .gates_num = ARRAY_SIZE(stm32f746_gates),
1317 .pll_data = stm32f469_pll,
1318 .aux_clk = stm32f746_aux_clk,
1319 .aux_clk_num = ARRAY_SIZE(stm32f746_aux_clk),
1320};
1321
1322static const struct of_device_id stm32f4_of_match[] = {
1323 {
1324 .compatible = "st,stm32f42xx-rcc",
1325 .data = &stm32f429_clk_data
1326 },
1327 {
1328 .compatible = "st,stm32f469-rcc",
1329 .data = &stm32f469_clk_data
1330 },
1331 {
1332 .compatible = "st,stm32f746-rcc",
1333 .data = &stm32f746_clk_data
1334 },
1335 {}
1336};
1337
1338static struct clk_hw *stm32_register_aux_clk(const char *name,
1339 const char * const *parent_names, int num_parents,
1340 int offset_mux, u8 shift, u8 mask,
1341 int offset_gate, u8 bit_idx,
1342 unsigned long flags, spinlock_t *lock)
1343{
1344 struct clk_hw *hw;
1345 struct clk_gate *gate = NULL;
1346 struct clk_mux *mux = NULL;
1347 struct clk_hw *mux_hw = NULL, *gate_hw = NULL;
1348 const struct clk_ops *mux_ops = NULL, *gate_ops = NULL;
1349
1350 if (offset_gate != NO_GATE) {
1351 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1352 if (!gate) {
1353 hw = ERR_PTR(-EINVAL);
1354 goto fail;
1355 }
1356
1357 gate->reg = base + offset_gate;
1358 gate->bit_idx = bit_idx;
1359 gate->flags = 0;
1360 gate->lock = lock;
1361 gate_hw = &gate->hw;
1362 gate_ops = &clk_gate_ops;
1363 }
1364
1365 if (offset_mux != NO_MUX) {
1366 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
1367 if (!mux) {
1368 hw = ERR_PTR(-EINVAL);
1369 goto fail;
1370 }
1371
1372 mux->reg = base + offset_mux;
1373 mux->shift = shift;
1374 mux->mask = mask;
1375 mux->flags = 0;
1376 mux_hw = &mux->hw;
1377 mux_ops = &clk_mux_ops;
1378 }
1379
1380 if (mux_hw == NULL && gate_hw == NULL) {
1381 hw = ERR_PTR(-EINVAL);
1382 goto fail;
1383 }
1384
1385 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
1386 mux_hw, mux_ops,
1387 NULL, NULL,
1388 gate_hw, gate_ops,
1389 flags);
1390
1391fail:
1392 if (IS_ERR(hw)) {
1393 kfree(gate);
1394 kfree(mux);
1395 }
1396
1397 return hw;
1398}
1399
1400static void __init stm32f4_rcc_init(struct device_node *np)
1401{
1402 const char *hse_clk, *i2s_in_clk;
1403 int n;
1404 const struct of_device_id *match;
1405 const struct stm32f4_clk_data *data;
1406 unsigned long pllcfgr;
1407 const char *pllsrc;
1408 unsigned long pllm;
1409
1410 base = of_iomap(np, 0);
1411 if (!base) {
1412 pr_err("%s: unable to map resource", np->name);
1413 return;
1414 }
1415
1416 pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1417 if (IS_ERR(pdrm)) {
1418 pdrm = NULL;
1419 pr_warn("%s: Unable to get syscfg\n", __func__);
1420 }
1421
1422 match = of_match_node(stm32f4_of_match, np);
1423 if (WARN_ON(!match))
1424 return;
1425
1426 data = match->data;
1427
1428 stm32fx_end_primary_clk = data->end_primary;
1429
1430 clks = kmalloc_array(data->gates_num + stm32fx_end_primary_clk,
1431 sizeof(*clks), GFP_KERNEL);
1432 if (!clks)
1433 goto fail;
1434
1435 stm32f4_gate_map = data->gates_map;
1436
1437 hse_clk = of_clk_get_parent_name(np, 0);
1438
1439 i2s_in_clk = of_clk_get_parent_name(np, 1);
1440
1441 i2s_parents[1] = i2s_in_clk;
1442 sai_parents[2] = i2s_in_clk;
1443
1444 clks[CLK_HSI] = clk_hw_register_fixed_rate_with_accuracy(NULL, "hsi",
1445 NULL, 0, 16000000, 160000);
1446
1447 pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
1448 pllsrc = pllcfgr & BIT(22) ? hse_clk : "hsi";
1449 pllm = pllcfgr & 0x3f;
1450
1451 clk_hw_register_fixed_factor(NULL, "vco_in", pllsrc,
1452 0, 1, pllm);
1453
1454 stm32f4_rcc_register_pll("vco_in", &data->pll_data[0],
1455 &stm32f4_clk_lock);
1456
1457 clks[PLL_VCO_I2S] = stm32f4_rcc_register_pll("vco_in",
1458 &data->pll_data[1], &stm32f4_clk_lock);
1459
1460 clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in",
1461 &data->pll_data[2], &stm32f4_clk_lock);
1462
1463 for (n = 0; n < MAX_POST_DIV; n++) {
1464 const struct stm32f4_pll_post_div_data *post_div;
1465 struct clk_hw *hw;
1466
1467 post_div = &post_div_data[n];
1468
1469 hw = clk_register_pll_div(post_div->name,
1470 post_div->parent,
1471 post_div->flag,
1472 base + post_div->offset,
1473 post_div->shift,
1474 post_div->width,
1475 post_div->flag_div,
1476 post_div->div_table,
1477 clks[post_div->pll_num],
1478 &stm32f4_clk_lock);
1479
1480 if (post_div->idx != NO_IDX)
1481 clks[post_div->idx] = hw;
1482 }
1483
1484 sys_parents[1] = hse_clk;
1485
1486 clks[CLK_SYSCLK] = clk_hw_register_mux_table(
1487 NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,
1488 base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
1489
1490 clk_register_divider_table(NULL, "ahb_div", "sys",
1491 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1492 4, 4, 0, ahb_div_table, &stm32f4_clk_lock);
1493
1494 clk_register_divider_table(NULL, "apb1_div", "ahb_div",
1495 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1496 10, 3, 0, apb_div_table, &stm32f4_clk_lock);
1497 clk_register_apb_mul(NULL, "apb1_mul", "apb1_div",
1498 CLK_SET_RATE_PARENT, 12);
1499
1500 clk_register_divider_table(NULL, "apb2_div", "ahb_div",
1501 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1502 13, 3, 0, apb_div_table, &stm32f4_clk_lock);
1503 clk_register_apb_mul(NULL, "apb2_mul", "apb2_div",
1504 CLK_SET_RATE_PARENT, 15);
1505
1506 clks[SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick", "ahb_div",
1507 0, 1, 8);
1508 clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div",
1509 0, 1, 1);
1510
1511 for (n = 0; n < data->gates_num; n++) {
1512 const struct stm32f4_gate_data *gd;
1513 unsigned int secondary;
1514 int idx;
1515
1516 gd = &data->gates_data[n];
1517 secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +
1518 gd->bit_idx;
1519 idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
1520
1521 if (idx < 0)
1522 goto fail;
1523
1524 clks[idx] = clk_hw_register_gate(
1525 NULL, gd->name, gd->parent_name, gd->flags,
1526 base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
1527
1528 if (IS_ERR(clks[idx])) {
1529 pr_err("%s: Unable to register leaf clock %s\n",
1530 np->full_name, gd->name);
1531 goto fail;
1532 }
1533 }
1534
1535 clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
1536 base + STM32F4_RCC_CSR, 0, 2, 0, &stm32f4_clk_lock);
1537
1538 if (IS_ERR(clks[CLK_LSI])) {
1539 pr_err("Unable to register lsi clock\n");
1540 goto fail;
1541 }
1542
1543 clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
1544 base + STM32F4_RCC_BDCR, 0, 2, 0, &stm32f4_clk_lock);
1545
1546 if (IS_ERR(clks[CLK_LSE])) {
1547 pr_err("Unable to register lse clock\n");
1548 goto fail;
1549 }
1550
1551 clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",
1552 0, base + STM32F4_RCC_CFGR, 16, 5, 0,
1553 &stm32f4_clk_lock);
1554
1555 if (IS_ERR(clks[CLK_HSE_RTC])) {
1556 pr_err("Unable to register hse-rtc clock\n");
1557 goto fail;
1558 }
1559
1560 clks[CLK_RTC] = stm32_register_cclk(NULL, "rtc", rtc_parents, 4,
1561 base + STM32F4_RCC_BDCR, 15, 8, 0, &stm32f4_clk_lock);
1562
1563 if (IS_ERR(clks[CLK_RTC])) {
1564 pr_err("Unable to register rtc clock\n");
1565 goto fail;
1566 }
1567
1568 for (n = 0; n < data->aux_clk_num; n++) {
1569 const struct stm32_aux_clk *aux_clk;
1570 struct clk_hw *hw;
1571
1572 aux_clk = &data->aux_clk[n];
1573
1574 hw = stm32_register_aux_clk(aux_clk->name,
1575 aux_clk->parent_names, aux_clk->num_parents,
1576 aux_clk->offset_mux, aux_clk->shift,
1577 aux_clk->mask, aux_clk->offset_gate,
1578 aux_clk->bit_idx, aux_clk->flags,
1579 &stm32f4_clk_lock);
1580
1581 if (IS_ERR(hw)) {
1582 pr_warn("Unable to register %s clk\n", aux_clk->name);
1583 continue;
1584 }
1585
1586 if (aux_clk->idx != NO_IDX)
1587 clks[aux_clk->idx] = hw;
1588 }
1589
1590 if (of_device_is_compatible(np, "st,stm32f746-rcc"))
1591
1592 clk_hw_register_fixed_factor(NULL, "hsi_div488", "hsi", 0,
1593 1, 488);
1594
1595 of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
1596 return;
1597fail:
1598 kfree(clks);
1599 iounmap(base);
1600}
1601CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
1602CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
1603CLK_OF_DECLARE_DRIVER(stm32f746_rcc, "st,stm32f746-rcc", stm32f4_rcc_init);