tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/dts-v1/;
2
3/include/ "skeleton.dtsi"
4
5#include <dt-bindings/interrupt-controller/irq.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/qcom,gcc-msm8660.h>
8#include <dt-bindings/soc/qcom,gsbi.h>
9
10/ {
11 model = "Qualcomm MSM8660";
12 compatible = "qcom,msm8660";
13 interrupt-parent = <&intc>;
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 compatible = "qcom,scorpion";
21 enable-method = "qcom,gcc-msm8660";
22 device_type = "cpu";
23 reg = <0>;
24 next-level-cache = <&L2>;
25 };
26
27 cpu@1 {
28 compatible = "qcom,scorpion";
29 enable-method = "qcom,gcc-msm8660";
30 device_type = "cpu";
31 reg = <1>;
32 next-level-cache = <&L2>;
33 };
34
35 L2: l2-cache {
36 compatible = "cache";
37 cache-level = <2>;
38 };
39 };
40
41 cpu-pmu {
42 compatible = "qcom,scorpion-mp-pmu";
43 interrupts = <1 9 0x304>;
44 };
45
46 clocks {
47 cxo_board {
48 compatible = "fixed-clock";
49 #clock-cells = <0>;
50 clock-frequency = <19200000>;
51 };
52
53 pxo_board {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <27000000>;
57 };
58
59 sleep_clk {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <32768>;
63 };
64 };
65
66 soc: soc {
67 #address-cells = <1>;
68 #size-cells = <1>;
69 ranges;
70 compatible = "simple-bus";
71
72 intc: interrupt-controller@2080000 {
73 compatible = "qcom,msm-8660-qgic";
74 interrupt-controller;
75 #interrupt-cells = <3>;
76 reg = < 0x02080000 0x1000 >,
77 < 0x02081000 0x1000 >;
78 };
79
80 timer@2000000 {
81 compatible = "qcom,scss-timer", "qcom,msm-timer";
82 interrupts = <1 0 0x301>,
83 <1 1 0x301>,
84 <1 2 0x301>;
85 reg = <0x02000000 0x100>;
86 clock-frequency = <27000000>,
87 <32768>;
88 cpu-offset = <0x40000>;
89 };
90
91 tlmm: pinctrl@800000 {
92 compatible = "qcom,msm8660-pinctrl";
93 reg = <0x800000 0x4000>;
94
95 gpio-controller;
96 #gpio-cells = <2>;
97 interrupts = <0 16 0x4>;
98 interrupt-controller;
99 #interrupt-cells = <2>;
100
101 };
102
103 gcc: clock-controller@900000 {
104 compatible = "qcom,gcc-msm8660";
105 #clock-cells = <1>;
106 #reset-cells = <1>;
107 reg = <0x900000 0x4000>;
108 };
109
110 gsbi12: gsbi@19c00000 {
111 compatible = "qcom,gsbi-v1.0.0";
112 cell-index = <12>;
113 reg = <0x19c00000 0x100>;
114 clocks = <&gcc GSBI12_H_CLK>;
115 clock-names = "iface";
116 #address-cells = <1>;
117 #size-cells = <1>;
118 ranges;
119
120 syscon-tcsr = <&tcsr>;
121
122 gsbi12_serial: serial@19c40000 {
123 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
124 reg = <0x19c40000 0x1000>,
125 <0x19c00000 0x1000>;
126 interrupts = <0 195 IRQ_TYPE_NONE>;
127 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
128 clock-names = "core", "iface";
129 status = "disabled";
130 };
131
132 gsbi12_i2c: i2c@19c80000 {
133 compatible = "qcom,i2c-qup-v1.1.1";
134 reg = <0x19c80000 0x1000>;
135 interrupts = <0 196 IRQ_TYPE_NONE>;
136 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
137 clock-names = "core", "iface";
138 #address-cells = <1>;
139 #size-cells = <0>;
140 status = "disabled";
141 };
142 };
143
144 external-bus@1a100000 {
145 compatible = "qcom,msm8660-ebi2";
146 #address-cells = <2>;
147 #size-cells = <1>;
148 ranges = <0 0x0 0x1a800000 0x00800000>,
149 <1 0x0 0x1b000000 0x00800000>,
150 <2 0x0 0x1b800000 0x00800000>,
151 <3 0x0 0x1d000000 0x08000000>,
152 <4 0x0 0x1c800000 0x00800000>,
153 <5 0x0 0x1c000000 0x00800000>;
154 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
155 reg-names = "ebi2", "xmem";
156 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
157 clock-names = "ebi2x", "ebi2";
158 status = "disabled";
159 };
160
161 qcom,ssbi@500000 {
162 compatible = "qcom,ssbi";
163 reg = <0x500000 0x1000>;
164 qcom,controller-type = "pmic-arbiter";
165
166 pm8058: pmic@0 {
167 compatible = "qcom,pm8058";
168 interrupt-parent = <&tlmm>;
169 interrupts = <88 8>;
170 #interrupt-cells = <2>;
171 interrupt-controller;
172 #address-cells = <1>;
173 #size-cells = <0>;
174
175 pm8058_gpio: gpio@150 {
176 compatible = "qcom,pm8058-gpio",
177 "qcom,ssbi-gpio";
178 reg = <0x150>;
179 interrupt-parent = <&pm8058>;
180 interrupts = <192 IRQ_TYPE_NONE>,
181 <193 IRQ_TYPE_NONE>,
182 <194 IRQ_TYPE_NONE>,
183 <195 IRQ_TYPE_NONE>,
184 <196 IRQ_TYPE_NONE>,
185 <197 IRQ_TYPE_NONE>,
186 <198 IRQ_TYPE_NONE>,
187 <199 IRQ_TYPE_NONE>,
188 <200 IRQ_TYPE_NONE>,
189 <201 IRQ_TYPE_NONE>,
190 <202 IRQ_TYPE_NONE>,
191 <203 IRQ_TYPE_NONE>,
192 <204 IRQ_TYPE_NONE>,
193 <205 IRQ_TYPE_NONE>,
194 <206 IRQ_TYPE_NONE>,
195 <207 IRQ_TYPE_NONE>,
196 <208 IRQ_TYPE_NONE>,
197 <209 IRQ_TYPE_NONE>,
198 <210 IRQ_TYPE_NONE>,
199 <211 IRQ_TYPE_NONE>,
200 <212 IRQ_TYPE_NONE>,
201 <213 IRQ_TYPE_NONE>,
202 <214 IRQ_TYPE_NONE>,
203 <215 IRQ_TYPE_NONE>,
204 <216 IRQ_TYPE_NONE>,
205 <217 IRQ_TYPE_NONE>,
206 <218 IRQ_TYPE_NONE>,
207 <219 IRQ_TYPE_NONE>,
208 <220 IRQ_TYPE_NONE>,
209 <221 IRQ_TYPE_NONE>,
210 <222 IRQ_TYPE_NONE>,
211 <223 IRQ_TYPE_NONE>,
212 <224 IRQ_TYPE_NONE>,
213 <225 IRQ_TYPE_NONE>,
214 <226 IRQ_TYPE_NONE>,
215 <227 IRQ_TYPE_NONE>,
216 <228 IRQ_TYPE_NONE>,
217 <229 IRQ_TYPE_NONE>,
218 <230 IRQ_TYPE_NONE>,
219 <231 IRQ_TYPE_NONE>,
220 <232 IRQ_TYPE_NONE>,
221 <233 IRQ_TYPE_NONE>,
222 <234 IRQ_TYPE_NONE>,
223 <235 IRQ_TYPE_NONE>;
224 gpio-controller;
225 #gpio-cells = <2>;
226
227 };
228
229 pm8058_mpps: mpps@50 {
230 compatible = "qcom,pm8058-mpp",
231 "qcom,ssbi-mpp";
232 reg = <0x50>;
233 gpio-controller;
234 #gpio-cells = <2>;
235 interrupt-parent = <&pm8058>;
236 interrupts =
237 <128 IRQ_TYPE_NONE>,
238 <129 IRQ_TYPE_NONE>,
239 <130 IRQ_TYPE_NONE>,
240 <131 IRQ_TYPE_NONE>,
241 <132 IRQ_TYPE_NONE>,
242 <133 IRQ_TYPE_NONE>,
243 <134 IRQ_TYPE_NONE>,
244 <135 IRQ_TYPE_NONE>,
245 <136 IRQ_TYPE_NONE>,
246 <137 IRQ_TYPE_NONE>,
247 <138 IRQ_TYPE_NONE>,
248 <139 IRQ_TYPE_NONE>;
249 };
250
251 pwrkey@1c {
252 compatible = "qcom,pm8058-pwrkey";
253 reg = <0x1c>;
254 interrupt-parent = <&pm8058>;
255 interrupts = <50 1>, <51 1>;
256 debounce = <15625>;
257 pull-up;
258 };
259
260 keypad@148 {
261 compatible = "qcom,pm8058-keypad";
262 reg = <0x148>;
263 interrupt-parent = <&pm8058>;
264 interrupts = <74 1>, <75 1>;
265 debounce = <15>;
266 scan-delay = <32>;
267 row-hold = <91500>;
268 };
269
270 rtc@1e8 {
271 compatible = "qcom,pm8058-rtc";
272 reg = <0x1e8>;
273 interrupt-parent = <&pm8058>;
274 interrupts = <39 1>;
275 allow-set-time;
276 };
277
278 vibrator@4a {
279 compatible = "qcom,pm8058-vib";
280 reg = <0x4a>;
281 };
282 };
283 };
284
285 l2cc: clock-controller@2082000 {
286 compatible = "syscon";
287 reg = <0x02082000 0x1000>;
288 };
289
290 rpm: rpm@104000 {
291 compatible = "qcom,rpm-msm8660";
292 reg = <0x00104000 0x1000>;
293 qcom,ipc = <&l2cc 0x8 2>;
294
295 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
296 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
297 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
298 interrupt-names = "ack", "err", "wakeup";
299 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
300 clock-names = "ram";
301
302 rpmcc: clock-controller {
303 compatible = "qcom,rpmcc-apq8660", "qcom,rpmcc";
304 #clock-cells = <1>;
305 };
306
307 pm8901-regulators {
308 compatible = "qcom,rpm-pm8901-regulators";
309
310 pm8901_l0: l0 {};
311 pm8901_l1: l1 {};
312 pm8901_l2: l2 {};
313 pm8901_l3: l3 {};
314 pm8901_l4: l4 {};
315 pm8901_l5: l5 {};
316 pm8901_l6: l6 {};
317
318 /* S0 and S1 Handled as SAW regulators by SPM */
319 pm8901_s2: s2 {};
320 pm8901_s3: s3 {};
321 pm8901_s4: s4 {};
322
323 pm8901_lvs0: lvs0 {};
324 pm8901_lvs1: lvs1 {};
325 pm8901_lvs2: lvs2 {};
326 pm8901_lvs3: lvs3 {};
327
328 pm8901_mvs: mvs {};
329 };
330
331 pm8058-regulators {
332 compatible = "qcom,rpm-pm8058-regulators";
333
334 pm8058_l0: l0 {};
335 pm8058_l1: l1 {};
336 pm8058_l2: l2 {};
337 pm8058_l3: l3 {};
338 pm8058_l4: l4 {};
339 pm8058_l5: l5 {};
340 pm8058_l6: l6 {};
341 pm8058_l7: l7 {};
342 pm8058_l8: l8 {};
343 pm8058_l9: l9 {};
344 pm8058_l10: l10 {};
345 pm8058_l11: l11 {};
346 pm8058_l12: l12 {};
347 pm8058_l13: l13 {};
348 pm8058_l14: l14 {};
349 pm8058_l15: l15 {};
350 pm8058_l16: l16 {};
351 pm8058_l17: l17 {};
352 pm8058_l18: l18 {};
353 pm8058_l19: l19 {};
354 pm8058_l20: l20 {};
355 pm8058_l21: l21 {};
356 pm8058_l22: l22 {};
357 pm8058_l23: l23 {};
358 pm8058_l24: l24 {};
359 pm8058_l25: l25 {};
360
361 pm8058_s0: s0 {};
362 pm8058_s1: s1 {};
363 pm8058_s2: s2 {};
364 pm8058_s3: s3 {};
365 pm8058_s4: s4 {};
366
367 pm8058_lvs0: lvs0 {};
368 pm8058_lvs1: lvs1 {};
369
370 pm8058_ncp: ncp {};
371 };
372 };
373
374 amba {
375 compatible = "simple-bus";
376 #address-cells = <1>;
377 #size-cells = <1>;
378 ranges;
379 sdcc1: sdcc@12400000 {
380 status = "disabled";
381 compatible = "arm,pl18x", "arm,primecell";
382 arm,primecell-periphid = <0x00051180>;
383 reg = <0x12400000 0x8000>;
384 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
385 interrupt-names = "cmd_irq";
386 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
387 clock-names = "mclk", "apb_pclk";
388 bus-width = <8>;
389 max-frequency = <48000000>;
390 non-removable;
391 cap-sd-highspeed;
392 cap-mmc-highspeed;
393 };
394
395 sdcc3: sdcc@12180000 {
396 compatible = "arm,pl18x", "arm,primecell";
397 arm,primecell-periphid = <0x00051180>;
398 status = "disabled";
399 reg = <0x12180000 0x8000>;
400 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
401 interrupt-names = "cmd_irq";
402 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
403 clock-names = "mclk", "apb_pclk";
404 bus-width = <4>;
405 cap-sd-highspeed;
406 cap-mmc-highspeed;
407 max-frequency = <48000000>;
408 no-1-8-v;
409 };
410
411 sdcc5: sdcc@12200000 {
412 compatible = "arm,pl18x", "arm,primecell";
413 arm,primecell-periphid = <0x00051180>;
414 status = "disabled";
415 reg = <0x12200000 0x8000>;
416 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
417 interrupt-names = "cmd_irq";
418 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
419 clock-names = "mclk", "apb_pclk";
420 bus-width = <4>;
421 cap-sd-highspeed;
422 cap-mmc-highspeed;
423 max-frequency = <48000000>;
424 };
425 };
426
427 tcsr: syscon@1a400000 {
428 compatible = "qcom,tcsr-msm8660", "syscon";
429 reg = <0x1a400000 0x100>;
430 };
431 };
432
433};