tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6sx-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include "imx6sx-pinfunc.h"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 /*
19 * The decompressor and also some bootloaders rely on a
20 * pre-existing /chosen node to be available to insert the
21 * command line and merge other ATAGS info.
22 * Also for U-Boot there must be a pre-existing /memory node.
23 */
24 chosen {};
25 memory { device_type = "memory"; reg = <0 0>; };
26
27 aliases {
28 can0 = &flexcan1;
29 can1 = &flexcan2;
30 ethernet0 = &fec1;
31 ethernet1 = &fec2;
32 gpio0 = &gpio1;
33 gpio1 = &gpio2;
34 gpio2 = &gpio3;
35 gpio3 = &gpio4;
36 gpio4 = &gpio5;
37 gpio5 = &gpio6;
38 gpio6 = &gpio7;
39 i2c0 = &i2c1;
40 i2c1 = &i2c2;
41 i2c2 = &i2c3;
42 i2c3 = &i2c4;
43 mmc0 = &usdhc1;
44 mmc1 = &usdhc2;
45 mmc2 = &usdhc3;
46 mmc3 = &usdhc4;
47 serial0 = &uart1;
48 serial1 = &uart2;
49 serial2 = &uart3;
50 serial3 = &uart4;
51 serial4 = &uart5;
52 serial5 = &uart6;
53 spi0 = &ecspi1;
54 spi1 = &ecspi2;
55 spi2 = &ecspi3;
56 spi3 = &ecspi4;
57 spi4 = &ecspi5;
58 usbphy0 = &usbphy1;
59 usbphy1 = &usbphy2;
60 };
61
62 cpus {
63 #address-cells = <1>;
64 #size-cells = <0>;
65
66 cpu0: cpu@0 {
67 compatible = "arm,cortex-a9";
68 device_type = "cpu";
69 reg = <0>;
70 next-level-cache = <&L2>;
71 operating-points = <
72 /* kHz uV */
73 996000 1250000
74 792000 1175000
75 396000 1075000
76 198000 975000
77 >;
78 fsl,soc-operating-points = <
79 /* ARM kHz SOC uV */
80 996000 1175000
81 792000 1175000
82 396000 1175000
83 198000 1175000
84 >;
85 clock-latency = <61036>; /* two CLK32 periods */
86 clocks = <&clks IMX6SX_CLK_ARM>,
87 <&clks IMX6SX_CLK_PLL2_PFD2>,
88 <&clks IMX6SX_CLK_STEP>,
89 <&clks IMX6SX_CLK_PLL1_SW>,
90 <&clks IMX6SX_CLK_PLL1_SYS>;
91 clock-names = "arm", "pll2_pfd2_396m", "step",
92 "pll1_sw", "pll1_sys";
93 arm-supply = <®_arm>;
94 soc-supply = <®_soc>;
95 };
96 };
97
98 intc: interrupt-controller@00a01000 {
99 compatible = "arm,cortex-a9-gic";
100 #interrupt-cells = <3>;
101 interrupt-controller;
102 reg = <0x00a01000 0x1000>,
103 <0x00a00100 0x100>;
104 interrupt-parent = <&intc>;
105 };
106
107 clocks {
108 #address-cells = <1>;
109 #size-cells = <0>;
110
111 ckil: clock@0 {
112 compatible = "fixed-clock";
113 reg = <0>;
114 #clock-cells = <0>;
115 clock-frequency = <32768>;
116 clock-output-names = "ckil";
117 };
118
119 osc: clock@1 {
120 compatible = "fixed-clock";
121 reg = <1>;
122 #clock-cells = <0>;
123 clock-frequency = <24000000>;
124 clock-output-names = "osc";
125 };
126
127 ipp_di0: clock@2 {
128 compatible = "fixed-clock";
129 reg = <2>;
130 #clock-cells = <0>;
131 clock-frequency = <0>;
132 clock-output-names = "ipp_di0";
133 };
134
135 ipp_di1: clock@3 {
136 compatible = "fixed-clock";
137 reg = <3>;
138 #clock-cells = <0>;
139 clock-frequency = <0>;
140 clock-output-names = "ipp_di1";
141 };
142 };
143
144 soc {
145 #address-cells = <1>;
146 #size-cells = <1>;
147 compatible = "simple-bus";
148 interrupt-parent = <&gpc>;
149 ranges;
150
151 pmu {
152 compatible = "arm,cortex-a9-pmu";
153 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
154 };
155
156 ocram: sram@00900000 {
157 compatible = "mmio-sram";
158 reg = <0x00900000 0x20000>;
159 clocks = <&clks IMX6SX_CLK_OCRAM>;
160 };
161
162 L2: l2-cache@00a02000 {
163 compatible = "arm,pl310-cache";
164 reg = <0x00a02000 0x1000>;
165 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
166 cache-unified;
167 cache-level = <2>;
168 arm,tag-latency = <4 2 3>;
169 arm,data-latency = <4 2 3>;
170 };
171
172 gpu: gpu@01800000 {
173 compatible = "vivante,gc";
174 reg = <0x01800000 0x4000>;
175 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clks IMX6SX_CLK_GPU>,
177 <&clks IMX6SX_CLK_GPU>,
178 <&clks IMX6SX_CLK_GPU>;
179 clock-names = "bus", "core", "shader";
180 };
181
182 dma_apbh: dma-apbh@01804000 {
183 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
184 reg = <0x01804000 0x2000>;
185 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
189 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
190 #dma-cells = <1>;
191 dma-channels = <4>;
192 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
193 };
194
195 gpmi: gpmi-nand@01806000{
196 compatible = "fsl,imx6sx-gpmi-nand";
197 #address-cells = <1>;
198 #size-cells = <1>;
199 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
200 reg-names = "gpmi-nand", "bch";
201 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-names = "bch";
203 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
204 <&clks IMX6SX_CLK_GPMI_APB>,
205 <&clks IMX6SX_CLK_GPMI_BCH>,
206 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
207 <&clks IMX6SX_CLK_PER1_BCH>;
208 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
209 "gpmi_bch_apb", "per1_bch";
210 dmas = <&dma_apbh 0>;
211 dma-names = "rx-tx";
212 status = "disabled";
213 };
214
215 aips1: aips-bus@02000000 {
216 compatible = "fsl,aips-bus", "simple-bus";
217 #address-cells = <1>;
218 #size-cells = <1>;
219 reg = <0x02000000 0x100000>;
220 ranges;
221
222 spba-bus@02000000 {
223 compatible = "fsl,spba-bus", "simple-bus";
224 #address-cells = <1>;
225 #size-cells = <1>;
226 reg = <0x02000000 0x40000>;
227 ranges;
228
229 spdif: spdif@02004000 {
230 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
231 reg = <0x02004000 0x4000>;
232 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
233 dmas = <&sdma 14 18 0>,
234 <&sdma 15 18 0>;
235 dma-names = "rx", "tx";
236 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
237 <&clks IMX6SX_CLK_OSC>,
238 <&clks IMX6SX_CLK_SPDIF>,
239 <&clks 0>, <&clks 0>, <&clks 0>,
240 <&clks IMX6SX_CLK_IPG>,
241 <&clks 0>, <&clks 0>,
242 <&clks IMX6SX_CLK_SPBA>;
243 clock-names = "core", "rxtx0",
244 "rxtx1", "rxtx2",
245 "rxtx3", "rxtx4",
246 "rxtx5", "rxtx6",
247 "rxtx7", "spba";
248 status = "disabled";
249 };
250
251 ecspi1: ecspi@02008000 {
252 #address-cells = <1>;
253 #size-cells = <0>;
254 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
255 reg = <0x02008000 0x4000>;
256 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clks IMX6SX_CLK_ECSPI1>,
258 <&clks IMX6SX_CLK_ECSPI1>;
259 clock-names = "ipg", "per";
260 status = "disabled";
261 };
262
263 ecspi2: ecspi@0200c000 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
267 reg = <0x0200c000 0x4000>;
268 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clks IMX6SX_CLK_ECSPI2>,
270 <&clks IMX6SX_CLK_ECSPI2>;
271 clock-names = "ipg", "per";
272 status = "disabled";
273 };
274
275 ecspi3: ecspi@02010000 {
276 #address-cells = <1>;
277 #size-cells = <0>;
278 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
279 reg = <0x02010000 0x4000>;
280 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&clks IMX6SX_CLK_ECSPI3>,
282 <&clks IMX6SX_CLK_ECSPI3>;
283 clock-names = "ipg", "per";
284 status = "disabled";
285 };
286
287 ecspi4: ecspi@02014000 {
288 #address-cells = <1>;
289 #size-cells = <0>;
290 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
291 reg = <0x02014000 0x4000>;
292 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clks IMX6SX_CLK_ECSPI4>,
294 <&clks IMX6SX_CLK_ECSPI4>;
295 clock-names = "ipg", "per";
296 status = "disabled";
297 };
298
299 uart1: serial@02020000 {
300 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
301 reg = <0x02020000 0x4000>;
302 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&clks IMX6SX_CLK_UART_IPG>,
304 <&clks IMX6SX_CLK_UART_SERIAL>;
305 clock-names = "ipg", "per";
306 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
307 dma-names = "rx", "tx";
308 status = "disabled";
309 };
310
311 esai: esai@02024000 {
312 reg = <0x02024000 0x4000>;
313 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
315 <&clks IMX6SX_CLK_ESAI_MEM>,
316 <&clks IMX6SX_CLK_ESAI_EXTAL>,
317 <&clks IMX6SX_CLK_ESAI_IPG>,
318 <&clks IMX6SX_CLK_SPBA>;
319 clock-names = "core", "mem", "extal",
320 "fsys", "spba";
321 status = "disabled";
322 };
323
324 ssi1: ssi@02028000 {
325 #sound-dai-cells = <0>;
326 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
327 reg = <0x02028000 0x4000>;
328 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
330 <&clks IMX6SX_CLK_SSI1>;
331 clock-names = "ipg", "baud";
332 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
333 dma-names = "rx", "tx";
334 fsl,fifo-depth = <15>;
335 status = "disabled";
336 };
337
338 ssi2: ssi@0202c000 {
339 #sound-dai-cells = <0>;
340 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
341 reg = <0x0202c000 0x4000>;
342 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
344 <&clks IMX6SX_CLK_SSI2>;
345 clock-names = "ipg", "baud";
346 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
347 dma-names = "rx", "tx";
348 fsl,fifo-depth = <15>;
349 status = "disabled";
350 };
351
352 ssi3: ssi@02030000 {
353 #sound-dai-cells = <0>;
354 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
355 reg = <0x02030000 0x4000>;
356 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
358 <&clks IMX6SX_CLK_SSI3>;
359 clock-names = "ipg", "baud";
360 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
361 dma-names = "rx", "tx";
362 fsl,fifo-depth = <15>;
363 status = "disabled";
364 };
365
366 asrc: asrc@02034000 {
367 reg = <0x02034000 0x4000>;
368 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
370 <&clks IMX6SX_CLK_ASRC_IPG>,
371 <&clks IMX6SX_CLK_SPDIF>,
372 <&clks IMX6SX_CLK_SPBA>;
373 clock-names = "mem", "ipg", "asrck", "spba";
374 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
375 <&sdma 19 20 1>, <&sdma 20 20 1>,
376 <&sdma 21 20 1>, <&sdma 22 20 1>;
377 dma-names = "rxa", "rxb", "rxc",
378 "txa", "txb", "txc";
379 status = "okay";
380 };
381 };
382
383 pwm1: pwm@02080000 {
384 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
385 reg = <0x02080000 0x4000>;
386 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks IMX6SX_CLK_PWM1>,
388 <&clks IMX6SX_CLK_PWM1>;
389 clock-names = "ipg", "per";
390 #pwm-cells = <2>;
391 };
392
393 pwm2: pwm@02084000 {
394 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
395 reg = <0x02084000 0x4000>;
396 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&clks IMX6SX_CLK_PWM2>,
398 <&clks IMX6SX_CLK_PWM2>;
399 clock-names = "ipg", "per";
400 #pwm-cells = <2>;
401 };
402
403 pwm3: pwm@02088000 {
404 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
405 reg = <0x02088000 0x4000>;
406 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&clks IMX6SX_CLK_PWM3>,
408 <&clks IMX6SX_CLK_PWM3>;
409 clock-names = "ipg", "per";
410 #pwm-cells = <2>;
411 };
412
413 pwm4: pwm@0208c000 {
414 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
415 reg = <0x0208c000 0x4000>;
416 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&clks IMX6SX_CLK_PWM4>,
418 <&clks IMX6SX_CLK_PWM4>;
419 clock-names = "ipg", "per";
420 #pwm-cells = <2>;
421 };
422
423 flexcan1: can@02090000 {
424 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
425 reg = <0x02090000 0x4000>;
426 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
428 <&clks IMX6SX_CLK_CAN1_SERIAL>;
429 clock-names = "ipg", "per";
430 status = "disabled";
431 };
432
433 flexcan2: can@02094000 {
434 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
435 reg = <0x02094000 0x4000>;
436 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
438 <&clks IMX6SX_CLK_CAN2_SERIAL>;
439 clock-names = "ipg", "per";
440 status = "disabled";
441 };
442
443 gpt: gpt@02098000 {
444 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
445 reg = <0x02098000 0x4000>;
446 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
448 <&clks IMX6SX_CLK_GPT_3M>;
449 clock-names = "ipg", "per";
450 };
451
452 gpio1: gpio@0209c000 {
453 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
454 reg = <0x0209c000 0x4000>;
455 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
461 gpio-ranges = <&iomuxc 0 5 26>;
462 };
463
464 gpio2: gpio@020a0000 {
465 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
466 reg = <0x020a0000 0x4000>;
467 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
469 gpio-controller;
470 #gpio-cells = <2>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
473 gpio-ranges = <&iomuxc 0 31 20>;
474 };
475
476 gpio3: gpio@020a4000 {
477 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
478 reg = <0x020a4000 0x4000>;
479 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
481 gpio-controller;
482 #gpio-cells = <2>;
483 interrupt-controller;
484 #interrupt-cells = <2>;
485 gpio-ranges = <&iomuxc 0 51 29>;
486 };
487
488 gpio4: gpio@020a8000 {
489 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
490 reg = <0x020a8000 0x4000>;
491 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
493 gpio-controller;
494 #gpio-cells = <2>;
495 interrupt-controller;
496 #interrupt-cells = <2>;
497 gpio-ranges = <&iomuxc 0 80 32>;
498 };
499
500 gpio5: gpio@020ac000 {
501 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
502 reg = <0x020ac000 0x4000>;
503 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
505 gpio-controller;
506 #gpio-cells = <2>;
507 interrupt-controller;
508 #interrupt-cells = <2>;
509 gpio-ranges = <&iomuxc 0 112 24>;
510 };
511
512 gpio6: gpio@020b0000 {
513 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
514 reg = <0x020b0000 0x4000>;
515 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
517 gpio-controller;
518 #gpio-cells = <2>;
519 interrupt-controller;
520 #interrupt-cells = <2>;
521 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
522 };
523
524 gpio7: gpio@020b4000 {
525 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
526 reg = <0x020b4000 0x4000>;
527 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
529 gpio-controller;
530 #gpio-cells = <2>;
531 interrupt-controller;
532 #interrupt-cells = <2>;
533 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
534 };
535
536 kpp: kpp@020b8000 {
537 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
538 reg = <0x020b8000 0x4000>;
539 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&clks IMX6SX_CLK_DUMMY>;
541 status = "disabled";
542 };
543
544 wdog1: wdog@020bc000 {
545 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
546 reg = <0x020bc000 0x4000>;
547 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&clks IMX6SX_CLK_DUMMY>;
549 };
550
551 wdog2: wdog@020c0000 {
552 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
553 reg = <0x020c0000 0x4000>;
554 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&clks IMX6SX_CLK_DUMMY>;
556 status = "disabled";
557 };
558
559 clks: ccm@020c4000 {
560 compatible = "fsl,imx6sx-ccm";
561 reg = <0x020c4000 0x4000>;
562 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
564 #clock-cells = <1>;
565 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
566 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
567 };
568
569 anatop: anatop@020c8000 {
570 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
571 "syscon", "simple-bus";
572 reg = <0x020c8000 0x1000>;
573 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
576
577 regulator-1p1 {
578 compatible = "fsl,anatop-regulator";
579 regulator-name = "vdd1p1";
580 regulator-min-microvolt = <800000>;
581 regulator-max-microvolt = <1375000>;
582 regulator-always-on;
583 anatop-reg-offset = <0x110>;
584 anatop-vol-bit-shift = <8>;
585 anatop-vol-bit-width = <5>;
586 anatop-min-bit-val = <4>;
587 anatop-min-voltage = <800000>;
588 anatop-max-voltage = <1375000>;
589 };
590
591 regulator-3p0 {
592 compatible = "fsl,anatop-regulator";
593 regulator-name = "vdd3p0";
594 regulator-min-microvolt = <2800000>;
595 regulator-max-microvolt = <3150000>;
596 regulator-always-on;
597 anatop-reg-offset = <0x120>;
598 anatop-vol-bit-shift = <8>;
599 anatop-vol-bit-width = <5>;
600 anatop-min-bit-val = <0>;
601 anatop-min-voltage = <2625000>;
602 anatop-max-voltage = <3400000>;
603 };
604
605 regulator-2p5 {
606 compatible = "fsl,anatop-regulator";
607 regulator-name = "vdd2p5";
608 regulator-min-microvolt = <2100000>;
609 regulator-max-microvolt = <2875000>;
610 regulator-always-on;
611 anatop-reg-offset = <0x130>;
612 anatop-vol-bit-shift = <8>;
613 anatop-vol-bit-width = <5>;
614 anatop-min-bit-val = <0>;
615 anatop-min-voltage = <2100000>;
616 anatop-max-voltage = <2875000>;
617 };
618
619 reg_arm: regulator-vddcore {
620 compatible = "fsl,anatop-regulator";
621 regulator-name = "vddarm";
622 regulator-min-microvolt = <725000>;
623 regulator-max-microvolt = <1450000>;
624 regulator-always-on;
625 anatop-reg-offset = <0x140>;
626 anatop-vol-bit-shift = <0>;
627 anatop-vol-bit-width = <5>;
628 anatop-delay-reg-offset = <0x170>;
629 anatop-delay-bit-shift = <24>;
630 anatop-delay-bit-width = <2>;
631 anatop-min-bit-val = <1>;
632 anatop-min-voltage = <725000>;
633 anatop-max-voltage = <1450000>;
634 };
635
636 reg_pcie: regulator-vddpcie {
637 compatible = "fsl,anatop-regulator";
638 regulator-name = "vddpcie";
639 regulator-min-microvolt = <725000>;
640 regulator-max-microvolt = <1450000>;
641 anatop-reg-offset = <0x140>;
642 anatop-vol-bit-shift = <9>;
643 anatop-vol-bit-width = <5>;
644 anatop-delay-reg-offset = <0x170>;
645 anatop-delay-bit-shift = <26>;
646 anatop-delay-bit-width = <2>;
647 anatop-min-bit-val = <1>;
648 anatop-min-voltage = <725000>;
649 anatop-max-voltage = <1450000>;
650 };
651
652 reg_soc: regulator-vddsoc {
653 compatible = "fsl,anatop-regulator";
654 regulator-name = "vddsoc";
655 regulator-min-microvolt = <725000>;
656 regulator-max-microvolt = <1450000>;
657 regulator-always-on;
658 anatop-reg-offset = <0x140>;
659 anatop-vol-bit-shift = <18>;
660 anatop-vol-bit-width = <5>;
661 anatop-delay-reg-offset = <0x170>;
662 anatop-delay-bit-shift = <28>;
663 anatop-delay-bit-width = <2>;
664 anatop-min-bit-val = <1>;
665 anatop-min-voltage = <725000>;
666 anatop-max-voltage = <1450000>;
667 };
668 };
669
670 tempmon: tempmon {
671 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
672 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
673 fsl,tempmon = <&anatop>;
674 fsl,tempmon-data = <&ocotp>;
675 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
676 };
677
678 usbphy1: usbphy@020c9000 {
679 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
680 reg = <0x020c9000 0x1000>;
681 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&clks IMX6SX_CLK_USBPHY1>;
683 fsl,anatop = <&anatop>;
684 };
685
686 usbphy2: usbphy@020ca000 {
687 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
688 reg = <0x020ca000 0x1000>;
689 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&clks IMX6SX_CLK_USBPHY2>;
691 fsl,anatop = <&anatop>;
692 };
693
694 snvs: snvs@020cc000 {
695 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
696 reg = <0x020cc000 0x4000>;
697
698 snvs_rtc: snvs-rtc-lp {
699 compatible = "fsl,sec-v4.0-mon-rtc-lp";
700 regmap = <&snvs>;
701 offset = <0x34>;
702 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
703 };
704
705 snvs_poweroff: snvs-poweroff {
706 compatible = "syscon-poweroff";
707 regmap = <&snvs>;
708 offset = <0x38>;
709 mask = <0x60>;
710 status = "disabled";
711 };
712
713 snvs_pwrkey: snvs-powerkey {
714 compatible = "fsl,sec-v4.0-pwrkey";
715 regmap = <&snvs>;
716 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
717 linux,keycode = <KEY_POWER>;
718 wakeup-source;
719 };
720 };
721
722 epit1: epit@020d0000 {
723 reg = <0x020d0000 0x4000>;
724 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
725 };
726
727 epit2: epit@020d4000 {
728 reg = <0x020d4000 0x4000>;
729 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
730 };
731
732 src: src@020d8000 {
733 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
734 reg = <0x020d8000 0x4000>;
735 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
737 #reset-cells = <1>;
738 };
739
740 gpc: gpc@020dc000 {
741 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
742 reg = <0x020dc000 0x4000>;
743 interrupt-controller;
744 #interrupt-cells = <3>;
745 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
746 interrupt-parent = <&intc>;
747 };
748
749 iomuxc: iomuxc@020e0000 {
750 compatible = "fsl,imx6sx-iomuxc";
751 reg = <0x020e0000 0x4000>;
752 };
753
754 gpr: iomuxc-gpr@020e4000 {
755 compatible = "fsl,imx6sx-iomuxc-gpr",
756 "fsl,imx6q-iomuxc-gpr", "syscon";
757 reg = <0x020e4000 0x4000>;
758 };
759
760 sdma: sdma@020ec000 {
761 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
762 reg = <0x020ec000 0x4000>;
763 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&clks IMX6SX_CLK_SDMA>,
765 <&clks IMX6SX_CLK_SDMA>;
766 clock-names = "ipg", "ahb";
767 #dma-cells = <3>;
768 /* imx6sx reuses imx6q sdma firmware */
769 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
770 };
771 };
772
773 aips2: aips-bus@02100000 {
774 compatible = "fsl,aips-bus", "simple-bus";
775 #address-cells = <1>;
776 #size-cells = <1>;
777 reg = <0x02100000 0x100000>;
778 ranges;
779
780 crypto: caam@2100000 {
781 compatible = "fsl,sec-v4.0";
782 fsl,sec-era = <4>;
783 #address-cells = <1>;
784 #size-cells = <1>;
785 reg = <0x2100000 0x10000>;
786 ranges = <0 0x2100000 0x10000>;
787 interrupt-parent = <&intc>;
788 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
789 <&clks IMX6SX_CLK_CAAM_ACLK>,
790 <&clks IMX6SX_CLK_CAAM_IPG>,
791 <&clks IMX6SX_CLK_EIM_SLOW>;
792 clock-names = "mem", "aclk", "ipg", "emi_slow";
793
794 sec_jr0: jr0@1000 {
795 compatible = "fsl,sec-v4.0-job-ring";
796 reg = <0x1000 0x1000>;
797 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
798 };
799
800 sec_jr1: jr1@2000 {
801 compatible = "fsl,sec-v4.0-job-ring";
802 reg = <0x2000 0x1000>;
803 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
804 };
805 };
806
807 usbotg1: usb@02184000 {
808 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
809 reg = <0x02184000 0x200>;
810 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&clks IMX6SX_CLK_USBOH3>;
812 fsl,usbphy = <&usbphy1>;
813 fsl,usbmisc = <&usbmisc 0>;
814 fsl,anatop = <&anatop>;
815 ahb-burst-config = <0x0>;
816 tx-burst-size-dword = <0x10>;
817 rx-burst-size-dword = <0x10>;
818 status = "disabled";
819 };
820
821 usbotg2: usb@02184200 {
822 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
823 reg = <0x02184200 0x200>;
824 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&clks IMX6SX_CLK_USBOH3>;
826 fsl,usbphy = <&usbphy2>;
827 fsl,usbmisc = <&usbmisc 1>;
828 ahb-burst-config = <0x0>;
829 tx-burst-size-dword = <0x10>;
830 rx-burst-size-dword = <0x10>;
831 status = "disabled";
832 };
833
834 usbh: usb@02184400 {
835 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
836 reg = <0x02184400 0x200>;
837 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&clks IMX6SX_CLK_USBOH3>;
839 fsl,usbmisc = <&usbmisc 2>;
840 phy_type = "hsic";
841 fsl,anatop = <&anatop>;
842 dr_mode = "host";
843 ahb-burst-config = <0x0>;
844 tx-burst-size-dword = <0x10>;
845 rx-burst-size-dword = <0x10>;
846 status = "disabled";
847 };
848
849 usbmisc: usbmisc@02184800 {
850 #index-cells = <1>;
851 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
852 reg = <0x02184800 0x200>;
853 clocks = <&clks IMX6SX_CLK_USBOH3>;
854 };
855
856 fec1: ethernet@02188000 {
857 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
858 reg = <0x02188000 0x4000>;
859 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
860 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&clks IMX6SX_CLK_ENET>,
862 <&clks IMX6SX_CLK_ENET_AHB>,
863 <&clks IMX6SX_CLK_ENET_PTP>,
864 <&clks IMX6SX_CLK_ENET_REF>,
865 <&clks IMX6SX_CLK_ENET_PTP>;
866 clock-names = "ipg", "ahb", "ptp",
867 "enet_clk_ref", "enet_out";
868 fsl,num-tx-queues=<3>;
869 fsl,num-rx-queues=<3>;
870 status = "disabled";
871 };
872
873 mlb: mlb@0218c000 {
874 reg = <0x0218c000 0x4000>;
875 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
876 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
877 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
878 clocks = <&clks IMX6SX_CLK_MLB>;
879 status = "disabled";
880 };
881
882 usdhc1: usdhc@02190000 {
883 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
884 reg = <0x02190000 0x4000>;
885 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&clks IMX6SX_CLK_USDHC1>,
887 <&clks IMX6SX_CLK_USDHC1>,
888 <&clks IMX6SX_CLK_USDHC1>;
889 clock-names = "ipg", "ahb", "per";
890 bus-width = <4>;
891 status = "disabled";
892 };
893
894 usdhc2: usdhc@02194000 {
895 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
896 reg = <0x02194000 0x4000>;
897 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&clks IMX6SX_CLK_USDHC2>,
899 <&clks IMX6SX_CLK_USDHC2>,
900 <&clks IMX6SX_CLK_USDHC2>;
901 clock-names = "ipg", "ahb", "per";
902 bus-width = <4>;
903 status = "disabled";
904 };
905
906 usdhc3: usdhc@02198000 {
907 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
908 reg = <0x02198000 0x4000>;
909 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
910 clocks = <&clks IMX6SX_CLK_USDHC3>,
911 <&clks IMX6SX_CLK_USDHC3>,
912 <&clks IMX6SX_CLK_USDHC3>;
913 clock-names = "ipg", "ahb", "per";
914 bus-width = <4>;
915 status = "disabled";
916 };
917
918 usdhc4: usdhc@0219c000 {
919 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
920 reg = <0x0219c000 0x4000>;
921 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
922 clocks = <&clks IMX6SX_CLK_USDHC4>,
923 <&clks IMX6SX_CLK_USDHC4>,
924 <&clks IMX6SX_CLK_USDHC4>;
925 clock-names = "ipg", "ahb", "per";
926 bus-width = <4>;
927 status = "disabled";
928 };
929
930 i2c1: i2c@021a0000 {
931 #address-cells = <1>;
932 #size-cells = <0>;
933 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
934 reg = <0x021a0000 0x4000>;
935 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clks IMX6SX_CLK_I2C1>;
937 status = "disabled";
938 };
939
940 i2c2: i2c@021a4000 {
941 #address-cells = <1>;
942 #size-cells = <0>;
943 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
944 reg = <0x021a4000 0x4000>;
945 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&clks IMX6SX_CLK_I2C2>;
947 status = "disabled";
948 };
949
950 i2c3: i2c@021a8000 {
951 #address-cells = <1>;
952 #size-cells = <0>;
953 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
954 reg = <0x021a8000 0x4000>;
955 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&clks IMX6SX_CLK_I2C3>;
957 status = "disabled";
958 };
959
960 mmdc: mmdc@021b0000 {
961 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
962 reg = <0x021b0000 0x4000>;
963 };
964
965 fec2: ethernet@021b4000 {
966 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
967 reg = <0x021b4000 0x4000>;
968 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
970 clocks = <&clks IMX6SX_CLK_ENET>,
971 <&clks IMX6SX_CLK_ENET_AHB>,
972 <&clks IMX6SX_CLK_ENET_PTP>,
973 <&clks IMX6SX_CLK_ENET2_REF_125M>,
974 <&clks IMX6SX_CLK_ENET_PTP>;
975 clock-names = "ipg", "ahb", "ptp",
976 "enet_clk_ref", "enet_out";
977 status = "disabled";
978 };
979
980 weim: weim@021b8000 {
981 #address-cells = <2>;
982 #size-cells = <1>;
983 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
984 reg = <0x021b8000 0x4000>;
985 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
986 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
987 fsl,weim-cs-gpr = <&gpr>;
988 status = "disabled";
989 };
990
991 ocotp: ocotp@021bc000 {
992 compatible = "fsl,imx6sx-ocotp", "syscon";
993 reg = <0x021bc000 0x4000>;
994 clocks = <&clks IMX6SX_CLK_OCOTP>;
995 };
996
997 sai1: sai@021d4000 {
998 compatible = "fsl,imx6sx-sai";
999 reg = <0x021d4000 0x4000>;
1000 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1002 <&clks IMX6SX_CLK_SAI1>,
1003 <&clks 0>, <&clks 0>;
1004 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1005 dma-names = "rx", "tx";
1006 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1007 status = "disabled";
1008 };
1009
1010 audmux: audmux@021d8000 {
1011 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1012 reg = <0x021d8000 0x4000>;
1013 status = "disabled";
1014 };
1015
1016 sai2: sai@021dc000 {
1017 compatible = "fsl,imx6sx-sai";
1018 reg = <0x021dc000 0x4000>;
1019 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1021 <&clks IMX6SX_CLK_SAI2>,
1022 <&clks 0>, <&clks 0>;
1023 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1024 dma-names = "rx", "tx";
1025 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1026 status = "disabled";
1027 };
1028
1029 qspi1: qspi@021e0000 {
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1032 compatible = "fsl,imx6sx-qspi";
1033 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1034 reg-names = "QuadSPI", "QuadSPI-memory";
1035 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&clks IMX6SX_CLK_QSPI1>,
1037 <&clks IMX6SX_CLK_QSPI1>;
1038 clock-names = "qspi_en", "qspi";
1039 status = "disabled";
1040 };
1041
1042 qspi2: qspi@021e4000 {
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1045 compatible = "fsl,imx6sx-qspi";
1046 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1047 reg-names = "QuadSPI", "QuadSPI-memory";
1048 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&clks IMX6SX_CLK_QSPI2>,
1050 <&clks IMX6SX_CLK_QSPI2>;
1051 clock-names = "qspi_en", "qspi";
1052 status = "disabled";
1053 };
1054
1055 uart2: serial@021e8000 {
1056 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1057 reg = <0x021e8000 0x4000>;
1058 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1060 <&clks IMX6SX_CLK_UART_SERIAL>;
1061 clock-names = "ipg", "per";
1062 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1063 dma-names = "rx", "tx";
1064 status = "disabled";
1065 };
1066
1067 uart3: serial@021ec000 {
1068 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1069 reg = <0x021ec000 0x4000>;
1070 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1071 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1072 <&clks IMX6SX_CLK_UART_SERIAL>;
1073 clock-names = "ipg", "per";
1074 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1075 dma-names = "rx", "tx";
1076 status = "disabled";
1077 };
1078
1079 uart4: serial@021f0000 {
1080 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1081 reg = <0x021f0000 0x4000>;
1082 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1083 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1084 <&clks IMX6SX_CLK_UART_SERIAL>;
1085 clock-names = "ipg", "per";
1086 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1087 dma-names = "rx", "tx";
1088 status = "disabled";
1089 };
1090
1091 uart5: serial@021f4000 {
1092 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1093 reg = <0x021f4000 0x4000>;
1094 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1095 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1096 <&clks IMX6SX_CLK_UART_SERIAL>;
1097 clock-names = "ipg", "per";
1098 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1099 dma-names = "rx", "tx";
1100 status = "disabled";
1101 };
1102
1103 i2c4: i2c@021f8000 {
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1106 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1107 reg = <0x021f8000 0x4000>;
1108 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1109 clocks = <&clks IMX6SX_CLK_I2C4>;
1110 status = "disabled";
1111 };
1112 };
1113
1114 aips3: aips-bus@02200000 {
1115 compatible = "fsl,aips-bus", "simple-bus";
1116 #address-cells = <1>;
1117 #size-cells = <1>;
1118 reg = <0x02200000 0x100000>;
1119 ranges;
1120
1121 spba-bus@02200000 {
1122 compatible = "fsl,spba-bus", "simple-bus";
1123 #address-cells = <1>;
1124 #size-cells = <1>;
1125 reg = <0x02240000 0x40000>;
1126 ranges;
1127
1128 csi1: csi@02214000 {
1129 reg = <0x02214000 0x4000>;
1130 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1131 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1132 <&clks IMX6SX_CLK_CSI>,
1133 <&clks IMX6SX_CLK_DCIC1>;
1134 clock-names = "disp-axi", "csi_mclk", "dcic";
1135 status = "disabled";
1136 };
1137
1138 pxp: pxp@02218000 {
1139 reg = <0x02218000 0x4000>;
1140 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1141 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1142 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1143 clock-names = "pxp-axi", "disp-axi";
1144 status = "disabled";
1145 };
1146
1147 csi2: csi@0221c000 {
1148 reg = <0x0221c000 0x4000>;
1149 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1151 <&clks IMX6SX_CLK_CSI>,
1152 <&clks IMX6SX_CLK_DCIC2>;
1153 clock-names = "disp-axi", "csi_mclk", "dcic";
1154 status = "disabled";
1155 };
1156
1157 lcdif1: lcdif@02220000 {
1158 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1159 reg = <0x02220000 0x4000>;
1160 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1161 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1162 <&clks IMX6SX_CLK_LCDIF_APB>,
1163 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1164 clock-names = "pix", "axi", "disp_axi";
1165 status = "disabled";
1166 };
1167
1168 lcdif2: lcdif@02224000 {
1169 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1170 reg = <0x02224000 0x4000>;
1171 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1172 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1173 <&clks IMX6SX_CLK_LCDIF_APB>,
1174 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1175 clock-names = "pix", "axi", "disp_axi";
1176 status = "disabled";
1177 };
1178
1179 vadc: vadc@02228000 {
1180 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1181 reg-names = "vadc-vafe", "vadc-vdec";
1182 clocks = <&clks IMX6SX_CLK_VADC>,
1183 <&clks IMX6SX_CLK_CSI>;
1184 clock-names = "vadc", "csi";
1185 status = "disabled";
1186 };
1187 };
1188
1189 adc1: adc@02280000 {
1190 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1191 reg = <0x02280000 0x4000>;
1192 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&clks IMX6SX_CLK_IPG>;
1194 clock-names = "adc";
1195 fsl,adck-max-frequency = <30000000>, <40000000>,
1196 <20000000>;
1197 status = "disabled";
1198 };
1199
1200 adc2: adc@02284000 {
1201 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1202 reg = <0x02284000 0x4000>;
1203 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1204 clocks = <&clks IMX6SX_CLK_IPG>;
1205 clock-names = "adc";
1206 fsl,adck-max-frequency = <30000000>, <40000000>,
1207 <20000000>;
1208 status = "disabled";
1209 };
1210
1211 wdog3: wdog@02288000 {
1212 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1213 reg = <0x02288000 0x4000>;
1214 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1215 clocks = <&clks IMX6SX_CLK_DUMMY>;
1216 status = "disabled";
1217 };
1218
1219 ecspi5: ecspi@0228c000 {
1220 #address-cells = <1>;
1221 #size-cells = <0>;
1222 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1223 reg = <0x0228c000 0x4000>;
1224 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1225 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1226 <&clks IMX6SX_CLK_ECSPI5>;
1227 clock-names = "ipg", "per";
1228 status = "disabled";
1229 };
1230
1231 uart6: serial@022a0000 {
1232 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1233 reg = <0x022a0000 0x4000>;
1234 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1235 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1236 <&clks IMX6SX_CLK_UART_SERIAL>;
1237 clock-names = "ipg", "per";
1238 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1239 dma-names = "rx", "tx";
1240 status = "disabled";
1241 };
1242
1243 pwm5: pwm@022a4000 {
1244 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1245 reg = <0x022a4000 0x4000>;
1246 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1247 clocks = <&clks IMX6SX_CLK_PWM5>,
1248 <&clks IMX6SX_CLK_PWM5>;
1249 clock-names = "ipg", "per";
1250 #pwm-cells = <2>;
1251 };
1252
1253 pwm6: pwm@022a8000 {
1254 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1255 reg = <0x022a8000 0x4000>;
1256 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1257 clocks = <&clks IMX6SX_CLK_PWM6>,
1258 <&clks IMX6SX_CLK_PWM6>;
1259 clock-names = "ipg", "per";
1260 #pwm-cells = <2>;
1261 };
1262
1263 pwm7: pwm@022ac000 {
1264 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1265 reg = <0x022ac000 0x4000>;
1266 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1267 clocks = <&clks IMX6SX_CLK_PWM7>,
1268 <&clks IMX6SX_CLK_PWM7>;
1269 clock-names = "ipg", "per";
1270 #pwm-cells = <2>;
1271 };
1272
1273 pwm8: pwm@0022b0000 {
1274 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1275 reg = <0x0022b0000 0x4000>;
1276 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&clks IMX6SX_CLK_PWM8>,
1278 <&clks IMX6SX_CLK_PWM8>;
1279 clock-names = "ipg", "per";
1280 #pwm-cells = <2>;
1281 };
1282 };
1283
1284 pcie: pcie@0x08000000 {
1285 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1286 reg = <0x08ffc000 0x4000>; /* DBI */
1287 #address-cells = <3>;
1288 #size-cells = <2>;
1289 device_type = "pci";
1290 /* configuration space */
1291 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1292 /* downstream I/O */
1293 0x81000000 0 0 0x08f80000 0 0x00010000
1294 /* non-prefetchable memory */
1295 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1296 num-lanes = <1>;
1297 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1299 <&clks IMX6SX_CLK_PCIE_AXI>,
1300 <&clks IMX6SX_CLK_LVDS1_OUT>,
1301 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1302 clock-names = "pcie_ref_125m", "pcie_axi",
1303 "lvds_gate", "display_axi";
1304 status = "disabled";
1305 };
1306 };
1307
1308 gpu-subsystem {
1309 compatible = "fsl,imx-gpu-subsystem";
1310 cores = <&gpu>;
1311 };
1312};