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1Device tree bindings for GPMC connected NANDs
2
3GPMC connected NAND (found on OMAP boards) are represented as child nodes of
4the GPMC controller with a name of "nand".
5
6All timing relevant properties as well as generic gpmc child properties are
7explained in a separate documents - please refer to
8Documentation/devicetree/bindings/bus/ti-gpmc.txt
9
10For NAND specific properties such as ECC modes or bus width, please refer to
11Documentation/devicetree/bindings/mtd/nand.txt
12
13
14Required properties:
15
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
18 NAND I/O space
19 - interrupt-parent: must point to gpmc node
20 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
21
22Optional properties:
23
24 - nand-bus-width: Set this numeric value to 16 if the hardware
25 is wired that way. If not specified, a bus
26 width of 8 is assumed.
27
28 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
29 "sw" 1-bit Hamming ecc code via software
30 "hw" <deprecated> use "ham1" instead
31 "hw-romcode" <deprecated> use "ham1" instead
32 "ham1" 1-bit Hamming ecc code
33 "bch4" 4-bit BCH ecc code
34 "bch8" 8-bit BCH ecc code
35 "bch16" 16-bit BCH ECC code
36 Refer below "How to select correct ECC scheme for your device ?"
37
38 - ti,nand-xfer-type: A string setting the data transfer type. One of:
39
40 "prefetch-polled" Prefetch polled mode (default)
41 "polled" Polled mode, without prefetch
42 "prefetch-dma" Prefetch enabled DMA mode
43 "prefetch-irq" Prefetch enabled irq mode
44
45 - elm_id: <deprecated> use "ti,elm-id" instead
46 - ti,elm-id: Specifies phandle of the ELM devicetree node.
47 ELM is an on-chip hardware engine on TI SoC which is used for
48 locating ECC errors for BCHx algorithms. SoC devices which have
49 ELM hardware engines should specify this device node in .dtsi
50 Using ELM for ECC error correction frees some CPU cycles.
51 - rb-gpios: GPIO specifier for the ready/busy# pin.
52
53For inline partition table parsing (optional):
54
55 - #address-cells: should be set to 1
56 - #size-cells: should be set to 1
57
58Example for an AM33xx board:
59
60 gpmc: gpmc@50000000 {
61 compatible = "ti,am3352-gpmc";
62 ti,hwmods = "gpmc";
63 reg = <0x50000000 0x36c>;
64 interrupts = <100>;
65 gpmc,num-cs = <8>;
66 gpmc,num-waitpins = <2>;
67 #address-cells = <2>;
68 #size-cells = <1>;
69 ranges = <0 0 0x08000000 0x1000000>; /* CS0 space, 16MB */
70 elm_id = <&elm>;
71 interrupt-controller;
72 #interrupt-cells = <2>;
73
74 nand@0,0 {
75 compatible = "ti,omap2-nand";
76 reg = <0 0 4>; /* CS0, offset 0, NAND I/O window 4 */
77 interrupt-parent = <&gpmc>;
78 interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE NONE>;
79 nand-bus-width = <16>;
80 ti,nand-ecc-opt = "bch8";
81 ti,nand-xfer-type = "polled";
82 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
83
84 gpmc,sync-clk-ps = <0>;
85 gpmc,cs-on-ns = <0>;
86 gpmc,cs-rd-off-ns = <44>;
87 gpmc,cs-wr-off-ns = <44>;
88 gpmc,adv-on-ns = <6>;
89 gpmc,adv-rd-off-ns = <34>;
90 gpmc,adv-wr-off-ns = <44>;
91 gpmc,we-off-ns = <40>;
92 gpmc,oe-off-ns = <54>;
93 gpmc,access-ns = <64>;
94 gpmc,rd-cycle-ns = <82>;
95 gpmc,wr-cycle-ns = <82>;
96 gpmc,wr-access-ns = <40>;
97 gpmc,wr-data-mux-bus-ns = <0>;
98
99 #address-cells = <1>;
100 #size-cells = <1>;
101
102 /* partitions go here */
103 };
104 };
105
106How to select correct ECC scheme for your device ?
107--------------------------------------------------
108Higher ECC scheme usually means better protection against bit-flips and
109increased system lifetime. However, selection of ECC scheme is dependent
110on various other factors also like;
111
112(1) support of built in hardware engines.
113 Some legacy OMAP SoC do not have ELM harware engine, so those SoC cannot
114 support ecc-schemes with hardware error-correction (BCHx_HW). However
115 such SoC can use ecc-schemes with software library for error-correction
116 (BCHx_HW_DETECTION_SW). The error correction capability with software
117 library remains equivalent to their hardware counter-part, but there is
118 slight CPU penalty when too many bit-flips are detected during reads.
119
120(2) Device parameters like OOBSIZE.
121 Other factor which governs the selection of ecc-scheme is oob-size.
122 Higher ECC schemes require more OOB/Spare area to store ECC syndrome,
123 so the device should have enough free bytes available its OOB/Spare
124 area to accommodate ECC for entire page. In general following expression
125 helps in determining if given device can accommodate ECC syndrome:
126 "2 + (PAGESIZE / 512) * ECC_BYTES" >= OOBSIZE"
127 where
128 OOBSIZE number of bytes in OOB/spare area
129 PAGESIZE number of bytes in main-area of device page
130 ECC_BYTES number of ECC bytes generated to protect
131 512 bytes of data, which is:
132 '3' for HAM1_xx ecc schemes
133 '7' for BCH4_xx ecc schemes
134 '14' for BCH8_xx ecc schemes
135 '26' for BCH16_xx ecc schemes
136
137 Example(a): For a device with PAGESIZE = 2048 and OOBSIZE = 64 and
138 trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
139 Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
140 which is greater than capacity of NAND device (OOBSIZE=64)
141 Hence, BCH16 cannot be supported on given device. But it can
142 probably use lower ecc-schemes like BCH8.
143
144 Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 and
145 trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
146 Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
147 which can be accommodated in the OOB/Spare area of this device
148 (OOBSIZE=128). So this device can use BCH16 ecc-scheme.