tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2014-2016 Rafał Miłecki <rafal@milecki.pl>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/delay.h>
15#include <linux/bcma/bcma.h>
16#include <linux/spi/spi.h>
17
18#include "spi-bcm53xx.h"
19
20#define BCM53XXSPI_MAX_SPI_BAUD 13500000 /* 216 MHz? */
21#define BCM53XXSPI_FLASH_WINDOW SZ_32M
22
23/* The longest observed required wait was 19 ms */
24#define BCM53XXSPI_SPE_TIMEOUT_MS 80
25
26struct bcm53xxspi {
27 struct bcma_device *core;
28 struct spi_master *master;
29 void __iomem *mmio_base;
30
31 size_t read_offset;
32 bool bspi; /* Boot SPI mode with memory mapping */
33};
34
35static inline u32 bcm53xxspi_read(struct bcm53xxspi *b53spi, u16 offset)
36{
37 return bcma_read32(b53spi->core, offset);
38}
39
40static inline void bcm53xxspi_write(struct bcm53xxspi *b53spi, u16 offset,
41 u32 value)
42{
43 bcma_write32(b53spi->core, offset, value);
44}
45
46static void bcm53xxspi_disable_bspi(struct bcm53xxspi *b53spi)
47{
48 struct device *dev = &b53spi->core->dev;
49 unsigned long deadline;
50 u32 tmp;
51
52 if (!b53spi->bspi)
53 return;
54
55 tmp = bcm53xxspi_read(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL);
56 if (tmp & 0x1)
57 return;
58
59 deadline = jiffies + usecs_to_jiffies(200);
60 do {
61 tmp = bcm53xxspi_read(b53spi, B53SPI_BSPI_BUSY_STATUS);
62 if (!(tmp & 0x1)) {
63 bcm53xxspi_write(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL,
64 0x1);
65 ndelay(200);
66 b53spi->bspi = false;
67 return;
68 }
69 udelay(1);
70 } while (!time_after_eq(jiffies, deadline));
71
72 dev_warn(dev, "Timeout disabling BSPI\n");
73}
74
75static void bcm53xxspi_enable_bspi(struct bcm53xxspi *b53spi)
76{
77 u32 tmp;
78
79 if (b53spi->bspi)
80 return;
81
82 tmp = bcm53xxspi_read(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL);
83 if (!(tmp & 0x1))
84 return;
85
86 bcm53xxspi_write(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL, 0x0);
87 b53spi->bspi = true;
88}
89
90static inline unsigned int bcm53xxspi_calc_timeout(size_t len)
91{
92 /* Do some magic calculation based on length and buad. Add 10% and 1. */
93 return (len * 9000 / BCM53XXSPI_MAX_SPI_BAUD * 110 / 100) + 1;
94}
95
96static int bcm53xxspi_wait(struct bcm53xxspi *b53spi, unsigned int timeout_ms)
97{
98 unsigned long deadline;
99 u32 tmp;
100
101 /* SPE bit has to be 0 before we read MSPI STATUS */
102 deadline = jiffies + msecs_to_jiffies(BCM53XXSPI_SPE_TIMEOUT_MS);
103 do {
104 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
105 if (!(tmp & B53SPI_MSPI_SPCR2_SPE))
106 break;
107 udelay(5);
108 } while (!time_after_eq(jiffies, deadline));
109
110 if (tmp & B53SPI_MSPI_SPCR2_SPE)
111 goto spi_timeout;
112
113 /* Check status */
114 deadline = jiffies + msecs_to_jiffies(timeout_ms);
115 do {
116 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_MSPI_STATUS);
117 if (tmp & B53SPI_MSPI_MSPI_STATUS_SPIF) {
118 bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0);
119 return 0;
120 }
121
122 cpu_relax();
123 udelay(100);
124 } while (!time_after_eq(jiffies, deadline));
125
126spi_timeout:
127 bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0);
128
129 pr_err("Timeout waiting for SPI to be ready!\n");
130
131 return -EBUSY;
132}
133
134static void bcm53xxspi_buf_write(struct bcm53xxspi *b53spi, u8 *w_buf,
135 size_t len, bool cont)
136{
137 u32 tmp;
138 int i;
139
140 for (i = 0; i < len; i++) {
141 /* Transmit Register File MSB */
142 bcm53xxspi_write(b53spi, B53SPI_MSPI_TXRAM + 4 * (i * 2),
143 (unsigned int)w_buf[i]);
144 }
145
146 for (i = 0; i < len; i++) {
147 tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
148 B53SPI_CDRAM_PCS_DSCK;
149 if (!cont && i == len - 1)
150 tmp &= ~B53SPI_CDRAM_CONT;
151 tmp &= ~0x1;
152 /* Command Register File */
153 bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp);
154 }
155
156 /* Set queue pointers */
157 bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
158 bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP, len - 1);
159
160 if (cont)
161 bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
162
163 /* Start SPI transfer */
164 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
165 tmp |= B53SPI_MSPI_SPCR2_SPE;
166 if (cont)
167 tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD;
168 bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp);
169
170 /* Wait for SPI to finish */
171 bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len));
172
173 if (!cont)
174 bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
175
176 b53spi->read_offset = len;
177}
178
179static void bcm53xxspi_buf_read(struct bcm53xxspi *b53spi, u8 *r_buf,
180 size_t len, bool cont)
181{
182 u32 tmp;
183 int i;
184
185 for (i = 0; i < b53spi->read_offset + len; i++) {
186 tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
187 B53SPI_CDRAM_PCS_DSCK;
188 if (!cont && i == b53spi->read_offset + len - 1)
189 tmp &= ~B53SPI_CDRAM_CONT;
190 tmp &= ~0x1;
191 /* Command Register File */
192 bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp);
193 }
194
195 /* Set queue pointers */
196 bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
197 bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP,
198 b53spi->read_offset + len - 1);
199
200 if (cont)
201 bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
202
203 /* Start SPI transfer */
204 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
205 tmp |= B53SPI_MSPI_SPCR2_SPE;
206 if (cont)
207 tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD;
208 bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp);
209
210 /* Wait for SPI to finish */
211 bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len));
212
213 if (!cont)
214 bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
215
216 for (i = 0; i < len; ++i) {
217 int offset = b53spi->read_offset + i;
218
219 /* Data stored in the transmit register file LSB */
220 r_buf[i] = (u8)bcm53xxspi_read(b53spi, B53SPI_MSPI_RXRAM + 4 * (1 + offset * 2));
221 }
222
223 b53spi->read_offset = 0;
224}
225
226static int bcm53xxspi_transfer_one(struct spi_master *master,
227 struct spi_device *spi,
228 struct spi_transfer *t)
229{
230 struct bcm53xxspi *b53spi = spi_master_get_devdata(master);
231 u8 *buf;
232 size_t left;
233
234 bcm53xxspi_disable_bspi(b53spi);
235
236 if (t->tx_buf) {
237 buf = (u8 *)t->tx_buf;
238 left = t->len;
239 while (left) {
240 size_t to_write = min_t(size_t, 16, left);
241 bool cont = left - to_write > 0;
242
243 bcm53xxspi_buf_write(b53spi, buf, to_write, cont);
244 left -= to_write;
245 buf += to_write;
246 }
247 }
248
249 if (t->rx_buf) {
250 buf = (u8 *)t->rx_buf;
251 left = t->len;
252 while (left) {
253 size_t to_read = min_t(size_t, 16 - b53spi->read_offset,
254 left);
255 bool cont = left - to_read > 0;
256
257 bcm53xxspi_buf_read(b53spi, buf, to_read, cont);
258 left -= to_read;
259 buf += to_read;
260 }
261 }
262
263 return 0;
264}
265
266static int bcm53xxspi_flash_read(struct spi_device *spi,
267 struct spi_flash_read_message *msg)
268{
269 struct bcm53xxspi *b53spi = spi_master_get_devdata(spi->master);
270 int ret = 0;
271
272 if (msg->from + msg->len > BCM53XXSPI_FLASH_WINDOW)
273 return -EINVAL;
274
275 bcm53xxspi_enable_bspi(b53spi);
276 memcpy_fromio(msg->buf, b53spi->mmio_base + msg->from, msg->len);
277 msg->retlen = msg->len;
278
279 return ret;
280}
281
282/**************************************************
283 * BCMA
284 **************************************************/
285
286static const struct bcma_device_id bcm53xxspi_bcma_tbl[] = {
287 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_QSPI, BCMA_ANY_REV, BCMA_ANY_CLASS),
288 {},
289};
290MODULE_DEVICE_TABLE(bcma, bcm53xxspi_bcma_tbl);
291
292static int bcm53xxspi_bcma_probe(struct bcma_device *core)
293{
294 struct device *dev = &core->dev;
295 struct bcm53xxspi *b53spi;
296 struct spi_master *master;
297 int err;
298
299 if (core->bus->drv_cc.core->id.rev != 42) {
300 pr_err("SPI on SoC with unsupported ChipCommon rev\n");
301 return -ENOTSUPP;
302 }
303
304 master = spi_alloc_master(dev, sizeof(*b53spi));
305 if (!master)
306 return -ENOMEM;
307
308 b53spi = spi_master_get_devdata(master);
309 b53spi->master = master;
310 b53spi->core = core;
311
312 if (core->addr_s[0])
313 b53spi->mmio_base = devm_ioremap(dev, core->addr_s[0],
314 BCM53XXSPI_FLASH_WINDOW);
315 b53spi->bspi = true;
316 bcm53xxspi_disable_bspi(b53spi);
317
318 master->dev.of_node = dev->of_node;
319 master->transfer_one = bcm53xxspi_transfer_one;
320 if (b53spi->mmio_base)
321 master->spi_flash_read = bcm53xxspi_flash_read;
322
323 bcma_set_drvdata(core, b53spi);
324
325 err = devm_spi_register_master(dev, master);
326 if (err) {
327 spi_master_put(master);
328 bcma_set_drvdata(core, NULL);
329 return err;
330 }
331
332 return 0;
333}
334
335static struct bcma_driver bcm53xxspi_bcma_driver = {
336 .name = KBUILD_MODNAME,
337 .id_table = bcm53xxspi_bcma_tbl,
338 .probe = bcm53xxspi_bcma_probe,
339};
340
341/**************************************************
342 * Init & exit
343 **************************************************/
344
345static int __init bcm53xxspi_module_init(void)
346{
347 int err = 0;
348
349 err = bcma_driver_register(&bcm53xxspi_bcma_driver);
350 if (err)
351 pr_err("Failed to register bcma driver: %d\n", err);
352
353 return err;
354}
355
356static void __exit bcm53xxspi_module_exit(void)
357{
358 bcma_driver_unregister(&bcm53xxspi_bcma_driver);
359}
360
361module_init(bcm53xxspi_module_init);
362module_exit(bcm53xxspi_module_exit);
363
364MODULE_DESCRIPTION("Broadcom BCM53xx SPI Controller driver");
365MODULE_AUTHOR("Rafał Miłecki <zajec5@gmail.com>");
366MODULE_LICENSE("GPL v2");