tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Driver for the Aardvark PCIe controller, used on Marvell Armada
3 * 3700.
4 *
5 * Copyright (C) 2016 Marvell
6 *
7 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/delay.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/irqdomain.h>
18#include <linux/kernel.h>
19#include <linux/pci.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/of_address.h>
23#include <linux/of_pci.h>
24
25/* PCIe core registers */
26#define PCIE_CORE_CMD_STATUS_REG 0x4
27#define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
28#define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
29#define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
30#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
31#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
32#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
33#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
34#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
35#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
36#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
37#define PCIE_CORE_LINK_TRAINING BIT(5)
38#define PCIE_CORE_LINK_WIDTH_SHIFT 20
39#define PCIE_CORE_ERR_CAPCTL_REG 0x118
40#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
41#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
42#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
43#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
44
45/* PIO registers base address and register offsets */
46#define PIO_BASE_ADDR 0x4000
47#define PIO_CTRL (PIO_BASE_ADDR + 0x0)
48#define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
49#define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
50#define PIO_STAT (PIO_BASE_ADDR + 0x4)
51#define PIO_COMPLETION_STATUS_SHIFT 7
52#define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
53#define PIO_COMPLETION_STATUS_OK 0
54#define PIO_COMPLETION_STATUS_UR 1
55#define PIO_COMPLETION_STATUS_CRS 2
56#define PIO_COMPLETION_STATUS_CA 4
57#define PIO_NON_POSTED_REQ BIT(0)
58#define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
59#define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
60#define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
61#define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
62#define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
63#define PIO_START (PIO_BASE_ADDR + 0x1c)
64#define PIO_ISR (PIO_BASE_ADDR + 0x20)
65#define PIO_ISRM (PIO_BASE_ADDR + 0x24)
66
67/* Aardvark Control registers */
68#define CONTROL_BASE_ADDR 0x4800
69#define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
70#define PCIE_GEN_SEL_MSK 0x3
71#define PCIE_GEN_SEL_SHIFT 0x0
72#define SPEED_GEN_1 0
73#define SPEED_GEN_2 1
74#define SPEED_GEN_3 2
75#define IS_RC_MSK 1
76#define IS_RC_SHIFT 2
77#define LANE_CNT_MSK 0x18
78#define LANE_CNT_SHIFT 0x3
79#define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
80#define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
81#define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
82#define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
83#define LINK_TRAINING_EN BIT(6)
84#define LEGACY_INTA BIT(28)
85#define LEGACY_INTB BIT(29)
86#define LEGACY_INTC BIT(30)
87#define LEGACY_INTD BIT(31)
88#define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
89#define HOT_RESET_GEN BIT(0)
90#define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
91#define PCIE_CORE_CTRL2_RESERVED 0x7
92#define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
93#define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
94#define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
95#define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
96#define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
97#define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
98#define PCIE_ISR0_MSI_INT_PENDING BIT(24)
99#define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
100#define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
101#define PCIE_ISR0_ALL_MASK GENMASK(26, 0)
102#define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
103#define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
104#define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
105#define PCIE_ISR1_FLUSH BIT(5)
106#define PCIE_ISR1_ALL_MASK GENMASK(5, 4)
107#define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
108#define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
109#define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
110#define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
111#define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
112
113/* PCIe window configuration */
114#define OB_WIN_BASE_ADDR 0x4c00
115#define OB_WIN_BLOCK_SIZE 0x20
116#define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
117 OB_WIN_BLOCK_SIZE * (win) + \
118 (offset))
119#define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
120#define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
121#define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
122#define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
123#define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
124#define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
125#define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
126
127/* PCIe window types */
128#define OB_PCIE_MEM 0x0
129#define OB_PCIE_IO 0x4
130
131/* LMI registers base address and register offsets */
132#define LMI_BASE_ADDR 0x6000
133#define CFG_REG (LMI_BASE_ADDR + 0x0)
134#define LTSSM_SHIFT 24
135#define LTSSM_MASK 0x3f
136#define LTSSM_L0 0x10
137#define RC_BAR_CONFIG 0x300
138
139/* PCIe core controller registers */
140#define CTRL_CORE_BASE_ADDR 0x18000
141#define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
142#define CTRL_MODE_SHIFT 0x0
143#define CTRL_MODE_MASK 0x1
144#define PCIE_CORE_MODE_DIRECT 0x0
145#define PCIE_CORE_MODE_COMMAND 0x1
146
147/* PCIe Central Interrupts Registers */
148#define CENTRAL_INT_BASE_ADDR 0x1b000
149#define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
150#define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
151#define PCIE_IRQ_CMDQ_INT BIT(0)
152#define PCIE_IRQ_MSI_STATUS_INT BIT(1)
153#define PCIE_IRQ_CMD_SENT_DONE BIT(3)
154#define PCIE_IRQ_DMA_INT BIT(4)
155#define PCIE_IRQ_IB_DXFERDONE BIT(5)
156#define PCIE_IRQ_OB_DXFERDONE BIT(6)
157#define PCIE_IRQ_OB_RXFERDONE BIT(7)
158#define PCIE_IRQ_COMPQ_INT BIT(12)
159#define PCIE_IRQ_DIR_RD_DDR_DET BIT(13)
160#define PCIE_IRQ_DIR_WR_DDR_DET BIT(14)
161#define PCIE_IRQ_CORE_INT BIT(16)
162#define PCIE_IRQ_CORE_INT_PIO BIT(17)
163#define PCIE_IRQ_DPMU_INT BIT(18)
164#define PCIE_IRQ_PCIE_MIS_INT BIT(19)
165#define PCIE_IRQ_MSI_INT1_DET BIT(20)
166#define PCIE_IRQ_MSI_INT2_DET BIT(21)
167#define PCIE_IRQ_RC_DBELL_DET BIT(22)
168#define PCIE_IRQ_EP_STATUS BIT(23)
169#define PCIE_IRQ_ALL_MASK 0xfff0fb
170#define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT
171
172/* Transaction types */
173#define PCIE_CONFIG_RD_TYPE0 0x8
174#define PCIE_CONFIG_RD_TYPE1 0x9
175#define PCIE_CONFIG_WR_TYPE0 0xa
176#define PCIE_CONFIG_WR_TYPE1 0xb
177
178/* PCI_BDF shifts 8bit, so we need extra 4bit shift */
179#define PCIE_BDF(dev) (dev << 4)
180#define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
181#define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
182#define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
183#define PCIE_CONF_REG(reg) ((reg) & 0xffc)
184#define PCIE_CONF_ADDR(bus, devfn, where) \
185 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
186 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
187
188#define PIO_TIMEOUT_MS 1
189
190#define LINK_WAIT_MAX_RETRIES 10
191#define LINK_WAIT_USLEEP_MIN 90000
192#define LINK_WAIT_USLEEP_MAX 100000
193
194#define LEGACY_IRQ_NUM 4
195#define MSI_IRQ_NUM 32
196
197struct advk_pcie {
198 struct platform_device *pdev;
199 void __iomem *base;
200 struct list_head resources;
201 struct irq_domain *irq_domain;
202 struct irq_chip irq_chip;
203 struct msi_controller msi;
204 struct irq_domain *msi_domain;
205 struct irq_chip msi_irq_chip;
206 DECLARE_BITMAP(msi_irq_in_use, MSI_IRQ_NUM);
207 struct mutex msi_used_lock;
208 u16 msi_msg;
209 int root_bus_nr;
210};
211
212static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
213{
214 writel(val, pcie->base + reg);
215}
216
217static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
218{
219 return readl(pcie->base + reg);
220}
221
222static int advk_pcie_link_up(struct advk_pcie *pcie)
223{
224 u32 val, ltssm_state;
225
226 val = advk_readl(pcie, CFG_REG);
227 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
228 return ltssm_state >= LTSSM_L0;
229}
230
231static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
232{
233 struct device *dev = &pcie->pdev->dev;
234 int retries;
235
236 /* check if the link is up or not */
237 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
238 if (advk_pcie_link_up(pcie)) {
239 dev_info(dev, "link up\n");
240 return 0;
241 }
242
243 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
244 }
245
246 dev_err(dev, "link never came up\n");
247 return -ETIMEDOUT;
248}
249
250/*
251 * Set PCIe address window register which could be used for memory
252 * mapping.
253 */
254static void advk_pcie_set_ob_win(struct advk_pcie *pcie,
255 u32 win_num, u32 match_ms,
256 u32 match_ls, u32 mask_ms,
257 u32 mask_ls, u32 remap_ms,
258 u32 remap_ls, u32 action)
259{
260 advk_writel(pcie, match_ls, OB_WIN_MATCH_LS(win_num));
261 advk_writel(pcie, match_ms, OB_WIN_MATCH_MS(win_num));
262 advk_writel(pcie, mask_ms, OB_WIN_MASK_MS(win_num));
263 advk_writel(pcie, mask_ls, OB_WIN_MASK_LS(win_num));
264 advk_writel(pcie, remap_ms, OB_WIN_REMAP_MS(win_num));
265 advk_writel(pcie, remap_ls, OB_WIN_REMAP_LS(win_num));
266 advk_writel(pcie, action, OB_WIN_ACTIONS(win_num));
267 advk_writel(pcie, match_ls | BIT(0), OB_WIN_MATCH_LS(win_num));
268}
269
270static void advk_pcie_setup_hw(struct advk_pcie *pcie)
271{
272 u32 reg;
273 int i;
274
275 /* Point PCIe unit MBUS decode windows to DRAM space */
276 for (i = 0; i < 8; i++)
277 advk_pcie_set_ob_win(pcie, i, 0, 0, 0, 0, 0, 0, 0);
278
279 /* Set to Direct mode */
280 reg = advk_readl(pcie, CTRL_CONFIG_REG);
281 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
282 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
283 advk_writel(pcie, reg, CTRL_CONFIG_REG);
284
285 /* Set PCI global control register to RC mode */
286 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
287 reg |= (IS_RC_MSK << IS_RC_SHIFT);
288 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
289
290 /* Set Advanced Error Capabilities and Control PF0 register */
291 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
292 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
293 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
294 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
295 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
296
297 /* Set PCIe Device Control and Status 1 PF0 register */
298 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
299 (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
300 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
301 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
302 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
303
304 /* Program PCIe Control 2 to disable strict ordering */
305 reg = PCIE_CORE_CTRL2_RESERVED |
306 PCIE_CORE_CTRL2_TD_ENABLE;
307 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
308
309 /* Set GEN2 */
310 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
311 reg &= ~PCIE_GEN_SEL_MSK;
312 reg |= SPEED_GEN_2;
313 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
314
315 /* Set lane X1 */
316 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
317 reg &= ~LANE_CNT_MSK;
318 reg |= LANE_COUNT_1;
319 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
320
321 /* Enable link training */
322 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
323 reg |= LINK_TRAINING_EN;
324 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
325
326 /* Enable MSI */
327 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
328 reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
329 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
330
331 /* Clear all interrupts */
332 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
333 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
334 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
335
336 /* Disable All ISR0/1 Sources */
337 reg = PCIE_ISR0_ALL_MASK;
338 reg &= ~PCIE_ISR0_MSI_INT_PENDING;
339 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
340
341 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
342
343 /* Unmask all MSI's */
344 advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
345
346 /* Enable summary interrupt for GIC SPI source */
347 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
348 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
349
350 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
351 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
352 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
353
354 /* Bypass the address window mapping for PIO */
355 reg = advk_readl(pcie, PIO_CTRL);
356 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
357 advk_writel(pcie, reg, PIO_CTRL);
358
359 /* Start link training */
360 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
361 reg |= PCIE_CORE_LINK_TRAINING;
362 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
363
364 advk_pcie_wait_for_link(pcie);
365
366 reg = PCIE_CORE_LINK_L0S_ENTRY |
367 (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
368 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
369
370 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
371 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
372 PCIE_CORE_CMD_IO_ACCESS_EN |
373 PCIE_CORE_CMD_MEM_IO_REQ_EN;
374 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
375}
376
377static void advk_pcie_check_pio_status(struct advk_pcie *pcie)
378{
379 struct device *dev = &pcie->pdev->dev;
380 u32 reg;
381 unsigned int status;
382 char *strcomp_status, *str_posted;
383
384 reg = advk_readl(pcie, PIO_STAT);
385 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
386 PIO_COMPLETION_STATUS_SHIFT;
387
388 if (!status)
389 return;
390
391 switch (status) {
392 case PIO_COMPLETION_STATUS_UR:
393 strcomp_status = "UR";
394 break;
395 case PIO_COMPLETION_STATUS_CRS:
396 strcomp_status = "CRS";
397 break;
398 case PIO_COMPLETION_STATUS_CA:
399 strcomp_status = "CA";
400 break;
401 default:
402 strcomp_status = "Unknown";
403 break;
404 }
405
406 if (reg & PIO_NON_POSTED_REQ)
407 str_posted = "Non-posted";
408 else
409 str_posted = "Posted";
410
411 dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
412 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
413}
414
415static int advk_pcie_wait_pio(struct advk_pcie *pcie)
416{
417 struct device *dev = &pcie->pdev->dev;
418 unsigned long timeout;
419
420 timeout = jiffies + msecs_to_jiffies(PIO_TIMEOUT_MS);
421
422 while (time_before(jiffies, timeout)) {
423 u32 start, isr;
424
425 start = advk_readl(pcie, PIO_START);
426 isr = advk_readl(pcie, PIO_ISR);
427 if (!start && isr)
428 return 0;
429 }
430
431 dev_err(dev, "config read/write timed out\n");
432 return -ETIMEDOUT;
433}
434
435static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
436 int where, int size, u32 *val)
437{
438 struct advk_pcie *pcie = bus->sysdata;
439 u32 reg;
440 int ret;
441
442 if (PCI_SLOT(devfn) != 0) {
443 *val = 0xffffffff;
444 return PCIBIOS_DEVICE_NOT_FOUND;
445 }
446
447 /* Start PIO */
448 advk_writel(pcie, 0, PIO_START);
449 advk_writel(pcie, 1, PIO_ISR);
450
451 /* Program the control register */
452 reg = advk_readl(pcie, PIO_CTRL);
453 reg &= ~PIO_CTRL_TYPE_MASK;
454 if (bus->number == pcie->root_bus_nr)
455 reg |= PCIE_CONFIG_RD_TYPE0;
456 else
457 reg |= PCIE_CONFIG_RD_TYPE1;
458 advk_writel(pcie, reg, PIO_CTRL);
459
460 /* Program the address registers */
461 reg = PCIE_BDF(devfn) | PCIE_CONF_REG(where);
462 advk_writel(pcie, reg, PIO_ADDR_LS);
463 advk_writel(pcie, 0, PIO_ADDR_MS);
464
465 /* Program the data strobe */
466 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
467
468 /* Start the transfer */
469 advk_writel(pcie, 1, PIO_START);
470
471 ret = advk_pcie_wait_pio(pcie);
472 if (ret < 0)
473 return PCIBIOS_SET_FAILED;
474
475 advk_pcie_check_pio_status(pcie);
476
477 /* Get the read result */
478 *val = advk_readl(pcie, PIO_RD_DATA);
479 if (size == 1)
480 *val = (*val >> (8 * (where & 3))) & 0xff;
481 else if (size == 2)
482 *val = (*val >> (8 * (where & 3))) & 0xffff;
483
484 return PCIBIOS_SUCCESSFUL;
485}
486
487static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
488 int where, int size, u32 val)
489{
490 struct advk_pcie *pcie = bus->sysdata;
491 u32 reg;
492 u32 data_strobe = 0x0;
493 int offset;
494 int ret;
495
496 if (PCI_SLOT(devfn) != 0)
497 return PCIBIOS_DEVICE_NOT_FOUND;
498
499 if (where % size)
500 return PCIBIOS_SET_FAILED;
501
502 /* Start PIO */
503 advk_writel(pcie, 0, PIO_START);
504 advk_writel(pcie, 1, PIO_ISR);
505
506 /* Program the control register */
507 reg = advk_readl(pcie, PIO_CTRL);
508 reg &= ~PIO_CTRL_TYPE_MASK;
509 if (bus->number == pcie->root_bus_nr)
510 reg |= PCIE_CONFIG_WR_TYPE0;
511 else
512 reg |= PCIE_CONFIG_WR_TYPE1;
513 advk_writel(pcie, reg, PIO_CTRL);
514
515 /* Program the address registers */
516 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
517 advk_writel(pcie, reg, PIO_ADDR_LS);
518 advk_writel(pcie, 0, PIO_ADDR_MS);
519
520 /* Calculate the write strobe */
521 offset = where & 0x3;
522 reg = val << (8 * offset);
523 data_strobe = GENMASK(size - 1, 0) << offset;
524
525 /* Program the data register */
526 advk_writel(pcie, reg, PIO_WR_DATA);
527
528 /* Program the data strobe */
529 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
530
531 /* Start the transfer */
532 advk_writel(pcie, 1, PIO_START);
533
534 ret = advk_pcie_wait_pio(pcie);
535 if (ret < 0)
536 return PCIBIOS_SET_FAILED;
537
538 advk_pcie_check_pio_status(pcie);
539
540 return PCIBIOS_SUCCESSFUL;
541}
542
543static struct pci_ops advk_pcie_ops = {
544 .read = advk_pcie_rd_conf,
545 .write = advk_pcie_wr_conf,
546};
547
548static int advk_pcie_alloc_msi(struct advk_pcie *pcie)
549{
550 int hwirq;
551
552 mutex_lock(&pcie->msi_used_lock);
553 hwirq = find_first_zero_bit(pcie->msi_irq_in_use, MSI_IRQ_NUM);
554 if (hwirq >= MSI_IRQ_NUM)
555 hwirq = -ENOSPC;
556 else
557 set_bit(hwirq, pcie->msi_irq_in_use);
558 mutex_unlock(&pcie->msi_used_lock);
559
560 return hwirq;
561}
562
563static void advk_pcie_free_msi(struct advk_pcie *pcie, int hwirq)
564{
565 struct device *dev = &pcie->pdev->dev;
566
567 mutex_lock(&pcie->msi_used_lock);
568 if (!test_bit(hwirq, pcie->msi_irq_in_use))
569 dev_err(dev, "trying to free unused MSI#%d\n", hwirq);
570 else
571 clear_bit(hwirq, pcie->msi_irq_in_use);
572 mutex_unlock(&pcie->msi_used_lock);
573}
574
575static int advk_pcie_setup_msi_irq(struct msi_controller *chip,
576 struct pci_dev *pdev,
577 struct msi_desc *desc)
578{
579 struct advk_pcie *pcie = pdev->bus->sysdata;
580 struct msi_msg msg;
581 int virq, hwirq;
582 phys_addr_t msi_msg_phys;
583
584 /* We support MSI, but not MSI-X */
585 if (desc->msi_attrib.is_msix)
586 return -EINVAL;
587
588 hwirq = advk_pcie_alloc_msi(pcie);
589 if (hwirq < 0)
590 return hwirq;
591
592 virq = irq_create_mapping(pcie->msi_domain, hwirq);
593 if (!virq) {
594 advk_pcie_free_msi(pcie, hwirq);
595 return -EINVAL;
596 }
597
598 irq_set_msi_desc(virq, desc);
599
600 msi_msg_phys = virt_to_phys(&pcie->msi_msg);
601
602 msg.address_lo = lower_32_bits(msi_msg_phys);
603 msg.address_hi = upper_32_bits(msi_msg_phys);
604 msg.data = virq;
605
606 pci_write_msi_msg(virq, &msg);
607
608 return 0;
609}
610
611static void advk_pcie_teardown_msi_irq(struct msi_controller *chip,
612 unsigned int irq)
613{
614 struct irq_data *d = irq_get_irq_data(irq);
615 struct msi_desc *msi = irq_data_get_msi_desc(d);
616 struct advk_pcie *pcie = msi_desc_to_pci_sysdata(msi);
617 unsigned long hwirq = d->hwirq;
618
619 irq_dispose_mapping(irq);
620 advk_pcie_free_msi(pcie, hwirq);
621}
622
623static int advk_pcie_msi_map(struct irq_domain *domain,
624 unsigned int virq, irq_hw_number_t hw)
625{
626 struct advk_pcie *pcie = domain->host_data;
627
628 irq_set_chip_and_handler(virq, &pcie->msi_irq_chip,
629 handle_simple_irq);
630
631 return 0;
632}
633
634static const struct irq_domain_ops advk_pcie_msi_irq_ops = {
635 .map = advk_pcie_msi_map,
636};
637
638static void advk_pcie_irq_mask(struct irq_data *d)
639{
640 struct advk_pcie *pcie = d->domain->host_data;
641 irq_hw_number_t hwirq = irqd_to_hwirq(d);
642 u32 mask;
643
644 mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
645 mask |= PCIE_ISR0_INTX_ASSERT(hwirq);
646 advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
647}
648
649static void advk_pcie_irq_unmask(struct irq_data *d)
650{
651 struct advk_pcie *pcie = d->domain->host_data;
652 irq_hw_number_t hwirq = irqd_to_hwirq(d);
653 u32 mask;
654
655 mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
656 mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);
657 advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
658}
659
660static int advk_pcie_irq_map(struct irq_domain *h,
661 unsigned int virq, irq_hw_number_t hwirq)
662{
663 struct advk_pcie *pcie = h->host_data;
664
665 advk_pcie_irq_mask(irq_get_irq_data(virq));
666 irq_set_status_flags(virq, IRQ_LEVEL);
667 irq_set_chip_and_handler(virq, &pcie->irq_chip,
668 handle_level_irq);
669 irq_set_chip_data(virq, pcie);
670
671 return 0;
672}
673
674static const struct irq_domain_ops advk_pcie_irq_domain_ops = {
675 .map = advk_pcie_irq_map,
676 .xlate = irq_domain_xlate_onecell,
677};
678
679static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
680{
681 struct device *dev = &pcie->pdev->dev;
682 struct device_node *node = dev->of_node;
683 struct irq_chip *msi_irq_chip;
684 struct msi_controller *msi;
685 phys_addr_t msi_msg_phys;
686 int ret;
687
688 msi_irq_chip = &pcie->msi_irq_chip;
689
690 msi_irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-msi",
691 dev_name(dev));
692 if (!msi_irq_chip->name)
693 return -ENOMEM;
694
695 msi_irq_chip->irq_enable = pci_msi_unmask_irq;
696 msi_irq_chip->irq_disable = pci_msi_mask_irq;
697 msi_irq_chip->irq_mask = pci_msi_mask_irq;
698 msi_irq_chip->irq_unmask = pci_msi_unmask_irq;
699
700 msi = &pcie->msi;
701
702 msi->setup_irq = advk_pcie_setup_msi_irq;
703 msi->teardown_irq = advk_pcie_teardown_msi_irq;
704 msi->of_node = node;
705
706 mutex_init(&pcie->msi_used_lock);
707
708 msi_msg_phys = virt_to_phys(&pcie->msi_msg);
709
710 advk_writel(pcie, lower_32_bits(msi_msg_phys),
711 PCIE_MSI_ADDR_LOW_REG);
712 advk_writel(pcie, upper_32_bits(msi_msg_phys),
713 PCIE_MSI_ADDR_HIGH_REG);
714
715 pcie->msi_domain =
716 irq_domain_add_linear(NULL, MSI_IRQ_NUM,
717 &advk_pcie_msi_irq_ops, pcie);
718 if (!pcie->msi_domain)
719 return -ENOMEM;
720
721 ret = of_pci_msi_chip_add(msi);
722 if (ret < 0) {
723 irq_domain_remove(pcie->msi_domain);
724 return ret;
725 }
726
727 return 0;
728}
729
730static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
731{
732 of_pci_msi_chip_remove(&pcie->msi);
733 irq_domain_remove(pcie->msi_domain);
734}
735
736static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
737{
738 struct device *dev = &pcie->pdev->dev;
739 struct device_node *node = dev->of_node;
740 struct device_node *pcie_intc_node;
741 struct irq_chip *irq_chip;
742
743 pcie_intc_node = of_get_next_child(node, NULL);
744 if (!pcie_intc_node) {
745 dev_err(dev, "No PCIe Intc node found\n");
746 return -ENODEV;
747 }
748
749 irq_chip = &pcie->irq_chip;
750
751 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
752 dev_name(dev));
753 if (!irq_chip->name) {
754 of_node_put(pcie_intc_node);
755 return -ENOMEM;
756 }
757
758 irq_chip->irq_mask = advk_pcie_irq_mask;
759 irq_chip->irq_mask_ack = advk_pcie_irq_mask;
760 irq_chip->irq_unmask = advk_pcie_irq_unmask;
761
762 pcie->irq_domain =
763 irq_domain_add_linear(pcie_intc_node, LEGACY_IRQ_NUM,
764 &advk_pcie_irq_domain_ops, pcie);
765 if (!pcie->irq_domain) {
766 dev_err(dev, "Failed to get a INTx IRQ domain\n");
767 of_node_put(pcie_intc_node);
768 return -ENOMEM;
769 }
770
771 return 0;
772}
773
774static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
775{
776 irq_domain_remove(pcie->irq_domain);
777}
778
779static void advk_pcie_handle_msi(struct advk_pcie *pcie)
780{
781 u32 msi_val, msi_mask, msi_status, msi_idx;
782 u16 msi_data;
783
784 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
785 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
786 msi_status = msi_val & ~msi_mask;
787
788 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
789 if (!(BIT(msi_idx) & msi_status))
790 continue;
791
792 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
793 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF;
794 generic_handle_irq(msi_data);
795 }
796
797 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
798 PCIE_ISR0_REG);
799}
800
801static void advk_pcie_handle_int(struct advk_pcie *pcie)
802{
803 u32 val, mask, status;
804 int i, virq;
805
806 val = advk_readl(pcie, PCIE_ISR0_REG);
807 mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
808 status = val & ((~mask) & PCIE_ISR0_ALL_MASK);
809
810 if (!status) {
811 advk_writel(pcie, val, PCIE_ISR0_REG);
812 return;
813 }
814
815 /* Process MSI interrupts */
816 if (status & PCIE_ISR0_MSI_INT_PENDING)
817 advk_pcie_handle_msi(pcie);
818
819 /* Process legacy interrupts */
820 for (i = 0; i < LEGACY_IRQ_NUM; i++) {
821 if (!(status & PCIE_ISR0_INTX_ASSERT(i)))
822 continue;
823
824 advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),
825 PCIE_ISR0_REG);
826
827 virq = irq_find_mapping(pcie->irq_domain, i);
828 generic_handle_irq(virq);
829 }
830}
831
832static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)
833{
834 struct advk_pcie *pcie = arg;
835 u32 status;
836
837 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
838 if (!(status & PCIE_IRQ_CORE_INT))
839 return IRQ_NONE;
840
841 advk_pcie_handle_int(pcie);
842
843 /* Clear interrupt */
844 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
845
846 return IRQ_HANDLED;
847}
848
849static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
850{
851 int err, res_valid = 0;
852 struct device *dev = &pcie->pdev->dev;
853 struct device_node *np = dev->of_node;
854 struct resource_entry *win, *tmp;
855 resource_size_t iobase;
856
857 INIT_LIST_HEAD(&pcie->resources);
858
859 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
860 &iobase);
861 if (err)
862 return err;
863
864 err = devm_request_pci_bus_resources(dev, &pcie->resources);
865 if (err)
866 goto out_release_res;
867
868 resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
869 struct resource *res = win->res;
870
871 switch (resource_type(res)) {
872 case IORESOURCE_IO:
873 advk_pcie_set_ob_win(pcie, 1,
874 upper_32_bits(res->start),
875 lower_32_bits(res->start),
876 0, 0xF8000000, 0,
877 lower_32_bits(res->start),
878 OB_PCIE_IO);
879 err = pci_remap_iospace(res, iobase);
880 if (err) {
881 dev_warn(dev, "error %d: failed to map resource %pR\n",
882 err, res);
883 resource_list_destroy_entry(win);
884 }
885 break;
886 case IORESOURCE_MEM:
887 advk_pcie_set_ob_win(pcie, 0,
888 upper_32_bits(res->start),
889 lower_32_bits(res->start),
890 0x0, 0xF8000000, 0,
891 lower_32_bits(res->start),
892 (2 << 20) | OB_PCIE_MEM);
893 res_valid |= !(res->flags & IORESOURCE_PREFETCH);
894 break;
895 case IORESOURCE_BUS:
896 pcie->root_bus_nr = res->start;
897 break;
898 }
899 }
900
901 if (!res_valid) {
902 dev_err(dev, "non-prefetchable memory resource required\n");
903 err = -EINVAL;
904 goto out_release_res;
905 }
906
907 return 0;
908
909out_release_res:
910 pci_free_resource_list(&pcie->resources);
911 return err;
912}
913
914static int advk_pcie_probe(struct platform_device *pdev)
915{
916 struct device *dev = &pdev->dev;
917 struct advk_pcie *pcie;
918 struct resource *res;
919 struct pci_bus *bus, *child;
920 struct msi_controller *msi;
921 struct device_node *msi_node;
922 int ret, irq;
923
924 pcie = devm_kzalloc(dev, sizeof(struct advk_pcie), GFP_KERNEL);
925 if (!pcie)
926 return -ENOMEM;
927
928 pcie->pdev = pdev;
929
930 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
931 pcie->base = devm_ioremap_resource(dev, res);
932 if (IS_ERR(pcie->base))
933 return PTR_ERR(pcie->base);
934
935 irq = platform_get_irq(pdev, 0);
936 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler,
937 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie",
938 pcie);
939 if (ret) {
940 dev_err(dev, "Failed to register interrupt\n");
941 return ret;
942 }
943
944 ret = advk_pcie_parse_request_of_pci_ranges(pcie);
945 if (ret) {
946 dev_err(dev, "Failed to parse resources\n");
947 return ret;
948 }
949
950 advk_pcie_setup_hw(pcie);
951
952 ret = advk_pcie_init_irq_domain(pcie);
953 if (ret) {
954 dev_err(dev, "Failed to initialize irq\n");
955 return ret;
956 }
957
958 ret = advk_pcie_init_msi_irq_domain(pcie);
959 if (ret) {
960 dev_err(dev, "Failed to initialize irq\n");
961 advk_pcie_remove_irq_domain(pcie);
962 return ret;
963 }
964
965 msi_node = of_parse_phandle(dev->of_node, "msi-parent", 0);
966 if (msi_node)
967 msi = of_pci_find_msi_chip_by_node(msi_node);
968 else
969 msi = NULL;
970
971 bus = pci_scan_root_bus_msi(dev, 0, &advk_pcie_ops,
972 pcie, &pcie->resources, &pcie->msi);
973 if (!bus) {
974 advk_pcie_remove_msi_irq_domain(pcie);
975 advk_pcie_remove_irq_domain(pcie);
976 return -ENOMEM;
977 }
978
979 pci_bus_assign_resources(bus);
980
981 list_for_each_entry(child, &bus->children, node)
982 pcie_bus_configure_settings(child);
983
984 pci_bus_add_devices(bus);
985 return 0;
986}
987
988static const struct of_device_id advk_pcie_of_match_table[] = {
989 { .compatible = "marvell,armada-3700-pcie", },
990 {},
991};
992
993static struct platform_driver advk_pcie_driver = {
994 .driver = {
995 .name = "advk-pcie",
996 .of_match_table = advk_pcie_of_match_table,
997 /* Driver unloading/unbinding currently not supported */
998 .suppress_bind_attrs = true,
999 },
1000 .probe = advk_pcie_probe,
1001};
1002builtin_platform_driver(advk_pcie_driver);