tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_QP_H
34#define MLX5_QP_H
35
36#include <linux/mlx5/device.h>
37#include <linux/mlx5/driver.h>
38
39#define MLX5_INVALID_LKEY 0x100
40#define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
41#define MLX5_DIF_SIZE 8
42#define MLX5_STRIDE_BLOCK_OP 0x400
43#define MLX5_CPY_GRD_MASK 0xc0
44#define MLX5_CPY_APP_MASK 0x30
45#define MLX5_CPY_REF_MASK 0x0f
46#define MLX5_BSF_INC_REFTAG (1 << 6)
47#define MLX5_BSF_INL_VALID (1 << 15)
48#define MLX5_BSF_REFRESH_DIF (1 << 14)
49#define MLX5_BSF_REPEAT_BLOCK (1 << 7)
50#define MLX5_BSF_APPTAG_ESCAPE 0x1
51#define MLX5_BSF_APPREF_ESCAPE 0x2
52
53enum mlx5_qp_optpar {
54 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
55 MLX5_QP_OPTPAR_RRE = 1 << 1,
56 MLX5_QP_OPTPAR_RAE = 1 << 2,
57 MLX5_QP_OPTPAR_RWE = 1 << 3,
58 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
59 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
60 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
61 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
62 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
63 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
64 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
65 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
66 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
67 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
68 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
69 MLX5_QP_OPTPAR_SRQN = 1 << 18,
70 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
71 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
72 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
73};
74
75enum mlx5_qp_state {
76 MLX5_QP_STATE_RST = 0,
77 MLX5_QP_STATE_INIT = 1,
78 MLX5_QP_STATE_RTR = 2,
79 MLX5_QP_STATE_RTS = 3,
80 MLX5_QP_STATE_SQER = 4,
81 MLX5_QP_STATE_SQD = 5,
82 MLX5_QP_STATE_ERR = 6,
83 MLX5_QP_STATE_SQ_DRAINING = 7,
84 MLX5_QP_STATE_SUSPENDED = 9,
85 MLX5_QP_NUM_STATE,
86 MLX5_QP_STATE,
87 MLX5_QP_STATE_BAD,
88};
89
90enum {
91 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1,
92 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1,
93 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1,
94 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1,
95};
96
97enum {
98 MLX5_QP_ST_RC = 0x0,
99 MLX5_QP_ST_UC = 0x1,
100 MLX5_QP_ST_UD = 0x2,
101 MLX5_QP_ST_XRC = 0x3,
102 MLX5_QP_ST_MLX = 0x4,
103 MLX5_QP_ST_DCI = 0x5,
104 MLX5_QP_ST_DCT = 0x6,
105 MLX5_QP_ST_QP0 = 0x7,
106 MLX5_QP_ST_QP1 = 0x8,
107 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
108 MLX5_QP_ST_RAW_IPV6 = 0xa,
109 MLX5_QP_ST_SNIFFER = 0xb,
110 MLX5_QP_ST_SYNC_UMR = 0xe,
111 MLX5_QP_ST_PTP_1588 = 0xd,
112 MLX5_QP_ST_REG_UMR = 0xc,
113 MLX5_QP_ST_MAX
114};
115
116enum {
117 MLX5_QP_PM_MIGRATED = 0x3,
118 MLX5_QP_PM_ARMED = 0x0,
119 MLX5_QP_PM_REARM = 0x1
120};
121
122enum {
123 MLX5_NON_ZERO_RQ = 0x0,
124 MLX5_SRQ_RQ = 0x1,
125 MLX5_CRQ_RQ = 0x2,
126 MLX5_ZERO_LEN_RQ = 0x3
127};
128
129/* TODO REM */
130enum {
131 /* params1 */
132 MLX5_QP_BIT_SRE = 1 << 15,
133 MLX5_QP_BIT_SWE = 1 << 14,
134 MLX5_QP_BIT_SAE = 1 << 13,
135 /* params2 */
136 MLX5_QP_BIT_RRE = 1 << 15,
137 MLX5_QP_BIT_RWE = 1 << 14,
138 MLX5_QP_BIT_RAE = 1 << 13,
139 MLX5_QP_BIT_RIC = 1 << 4,
140 MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2,
141 MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1,
142 MLX5_QP_BIT_CC_MASTER = 1 << 0
143};
144
145enum {
146 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
147 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
148 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
149};
150
151enum {
152 MLX5_SEND_WQE_DS = 16,
153 MLX5_SEND_WQE_BB = 64,
154};
155
156#define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
157
158enum {
159 MLX5_SEND_WQE_MAX_WQEBBS = 16,
160};
161
162enum {
163 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
164 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
165 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
166 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
167 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
168};
169
170enum {
171 MLX5_FENCE_MODE_NONE = 0 << 5,
172 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
173 MLX5_FENCE_MODE_FENCE = 2 << 5,
174 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
175 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
176};
177
178enum {
179 MLX5_RCV_DBR = 0,
180 MLX5_SND_DBR = 1,
181};
182
183enum {
184 MLX5_FLAGS_INLINE = 1<<7,
185 MLX5_FLAGS_CHECK_FREE = 1<<5,
186};
187
188struct mlx5_wqe_fmr_seg {
189 __be32 flags;
190 __be32 mem_key;
191 __be64 buf_list;
192 __be64 start_addr;
193 __be64 reg_len;
194 __be32 offset;
195 __be32 page_size;
196 u32 reserved[2];
197};
198
199struct mlx5_wqe_ctrl_seg {
200 __be32 opmod_idx_opcode;
201 __be32 qpn_ds;
202 u8 signature;
203 u8 rsvd[2];
204 u8 fm_ce_se;
205 __be32 imm;
206};
207
208#define MLX5_WQE_CTRL_DS_MASK 0x3f
209#define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
210#define MLX5_WQE_CTRL_QPN_SHIFT 8
211#define MLX5_WQE_DS_UNITS 16
212#define MLX5_WQE_CTRL_OPCODE_MASK 0xff
213#define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
214#define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
215#define MLX5_WQE_AV_EXT 0x80000000
216
217enum {
218 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
219 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
220 MLX5_ETH_WQE_L3_CSUM = 1 << 6,
221 MLX5_ETH_WQE_L4_CSUM = 1 << 7,
222};
223
224enum {
225 MLX5_ETH_WQE_INSERT_VLAN = 1 << 15,
226};
227
228struct mlx5_wqe_eth_seg {
229 u8 rsvd0[4];
230 u8 cs_flags;
231 u8 rsvd1;
232 __be16 mss;
233 __be32 rsvd2;
234 union {
235 struct {
236 __be16 sz;
237 u8 start[2];
238 } inline_hdr;
239 struct {
240 __be16 type;
241 __be16 vlan_tci;
242 } insert;
243 };
244};
245
246struct mlx5_wqe_xrc_seg {
247 __be32 xrc_srqn;
248 u8 rsvd[12];
249};
250
251struct mlx5_wqe_masked_atomic_seg {
252 __be64 swap_add;
253 __be64 compare;
254 __be64 swap_add_mask;
255 __be64 compare_mask;
256};
257
258struct mlx5_base_av {
259 union {
260 struct {
261 __be32 qkey;
262 __be32 reserved;
263 } qkey;
264 __be64 dc_key;
265 } key;
266 __be32 dqp_dct;
267 u8 stat_rate_sl;
268 u8 fl_mlid;
269 union {
270 __be16 rlid;
271 __be16 udp_sport;
272 };
273};
274
275struct mlx5_av {
276 union {
277 struct {
278 __be32 qkey;
279 __be32 reserved;
280 } qkey;
281 __be64 dc_key;
282 } key;
283 __be32 dqp_dct;
284 u8 stat_rate_sl;
285 u8 fl_mlid;
286 union {
287 __be16 rlid;
288 __be16 udp_sport;
289 };
290 u8 reserved0[4];
291 u8 rmac[6];
292 u8 tclass;
293 u8 hop_limit;
294 __be32 grh_gid_fl;
295 u8 rgid[16];
296};
297
298struct mlx5_wqe_datagram_seg {
299 struct mlx5_av av;
300};
301
302struct mlx5_wqe_raddr_seg {
303 __be64 raddr;
304 __be32 rkey;
305 u32 reserved;
306};
307
308struct mlx5_wqe_atomic_seg {
309 __be64 swap_add;
310 __be64 compare;
311};
312
313struct mlx5_wqe_data_seg {
314 __be32 byte_count;
315 __be32 lkey;
316 __be64 addr;
317};
318
319struct mlx5_wqe_umr_ctrl_seg {
320 u8 flags;
321 u8 rsvd0[3];
322 __be16 xlt_octowords;
323 union {
324 __be16 xlt_offset;
325 __be16 bsf_octowords;
326 };
327 __be64 mkey_mask;
328 __be32 xlt_offset_47_16;
329 u8 rsvd1[28];
330};
331
332struct mlx5_seg_set_psv {
333 __be32 psv_num;
334 __be16 syndrome;
335 __be16 status;
336 __be32 transient_sig;
337 __be32 ref_tag;
338};
339
340struct mlx5_seg_get_psv {
341 u8 rsvd[19];
342 u8 num_psv;
343 __be32 l_key;
344 __be64 va;
345 __be32 psv_index[4];
346};
347
348struct mlx5_seg_check_psv {
349 u8 rsvd0[2];
350 __be16 err_coalescing_op;
351 u8 rsvd1[2];
352 __be16 xport_err_op;
353 u8 rsvd2[2];
354 __be16 xport_err_mask;
355 u8 rsvd3[7];
356 u8 num_psv;
357 __be32 l_key;
358 __be64 va;
359 __be32 psv_index[4];
360};
361
362struct mlx5_rwqe_sig {
363 u8 rsvd0[4];
364 u8 signature;
365 u8 rsvd1[11];
366};
367
368struct mlx5_wqe_signature_seg {
369 u8 rsvd0[4];
370 u8 signature;
371 u8 rsvd1[11];
372};
373
374#define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
375
376struct mlx5_wqe_inline_seg {
377 __be32 byte_count;
378};
379
380enum mlx5_sig_type {
381 MLX5_DIF_CRC = 0x1,
382 MLX5_DIF_IPCS = 0x2,
383};
384
385struct mlx5_bsf_inl {
386 __be16 vld_refresh;
387 __be16 dif_apptag;
388 __be32 dif_reftag;
389 u8 sig_type;
390 u8 rp_inv_seed;
391 u8 rsvd[3];
392 u8 dif_inc_ref_guard_check;
393 __be16 dif_app_bitmask_check;
394};
395
396struct mlx5_bsf {
397 struct mlx5_bsf_basic {
398 u8 bsf_size_sbs;
399 u8 check_byte_mask;
400 union {
401 u8 copy_byte_mask;
402 u8 bs_selector;
403 u8 rsvd_wflags;
404 } wire;
405 union {
406 u8 bs_selector;
407 u8 rsvd_mflags;
408 } mem;
409 __be32 raw_data_size;
410 __be32 w_bfs_psv;
411 __be32 m_bfs_psv;
412 } basic;
413 struct mlx5_bsf_ext {
414 __be32 t_init_gen_pro_size;
415 __be32 rsvd_epi_size;
416 __be32 w_tfs_psv;
417 __be32 m_tfs_psv;
418 } ext;
419 struct mlx5_bsf_inl w_inl;
420 struct mlx5_bsf_inl m_inl;
421};
422
423struct mlx5_mtt {
424 __be64 ptag;
425};
426
427struct mlx5_klm {
428 __be32 bcount;
429 __be32 key;
430 __be64 va;
431};
432
433struct mlx5_stride_block_entry {
434 __be16 stride;
435 __be16 bcount;
436 __be32 key;
437 __be64 va;
438};
439
440struct mlx5_stride_block_ctrl_seg {
441 __be32 bcount_per_cycle;
442 __be32 op;
443 __be32 repeat_count;
444 u16 rsvd;
445 __be16 num_entries;
446};
447
448struct mlx5_core_qp {
449 struct mlx5_core_rsc_common common; /* must be first */
450 void (*event) (struct mlx5_core_qp *, int);
451 int qpn;
452 struct mlx5_rsc_debug *dbg;
453 int pid;
454};
455
456struct mlx5_qp_path {
457 u8 fl_free_ar;
458 u8 rsvd3;
459 __be16 pkey_index;
460 u8 rsvd0;
461 u8 grh_mlid;
462 __be16 rlid;
463 u8 ackto_lt;
464 u8 mgid_index;
465 u8 static_rate;
466 u8 hop_limit;
467 __be32 tclass_flowlabel;
468 union {
469 u8 rgid[16];
470 u8 rip[16];
471 };
472 u8 f_dscp_ecn_prio;
473 u8 ecn_dscp;
474 __be16 udp_sport;
475 u8 dci_cfi_prio_sl;
476 u8 port;
477 u8 rmac[6];
478};
479
480/* FIXME: use mlx5_ifc.h qpc */
481struct mlx5_qp_context {
482 __be32 flags;
483 __be32 flags_pd;
484 u8 mtu_msgmax;
485 u8 rq_size_stride;
486 __be16 sq_crq_size;
487 __be32 qp_counter_set_usr_page;
488 __be32 wire_qpn;
489 __be32 log_pg_sz_remote_qpn;
490 struct mlx5_qp_path pri_path;
491 struct mlx5_qp_path alt_path;
492 __be32 params1;
493 u8 reserved2[4];
494 __be32 next_send_psn;
495 __be32 cqn_send;
496 __be32 deth_sqpn;
497 u8 reserved3[4];
498 __be32 last_acked_psn;
499 __be32 ssn;
500 __be32 params2;
501 __be32 rnr_nextrecvpsn;
502 __be32 xrcd;
503 __be32 cqn_recv;
504 __be64 db_rec_addr;
505 __be32 qkey;
506 __be32 rq_type_srqn;
507 __be32 rmsn;
508 __be16 hw_sq_wqe_counter;
509 __be16 sw_sq_wqe_counter;
510 __be16 hw_rcyclic_byte_counter;
511 __be16 hw_rq_counter;
512 __be16 sw_rcyclic_byte_counter;
513 __be16 sw_rq_counter;
514 u8 rsvd0[5];
515 u8 cgs;
516 u8 cs_req;
517 u8 cs_res;
518 __be64 dc_access_key;
519 u8 rsvd1[24];
520};
521
522static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
523{
524 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
525}
526
527static inline struct mlx5_core_mkey *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
528{
529 return radix_tree_lookup(&dev->priv.mkey_table.tree, key);
530}
531
532int mlx5_core_create_qp(struct mlx5_core_dev *dev,
533 struct mlx5_core_qp *qp,
534 u32 *in,
535 int inlen);
536int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 opcode,
537 u32 opt_param_mask, void *qpc,
538 struct mlx5_core_qp *qp);
539int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
540 struct mlx5_core_qp *qp);
541int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
542 u32 *out, int outlen);
543
544int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
545int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
546void mlx5_init_qp_table(struct mlx5_core_dev *dev);
547void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
548int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
549void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
550int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
551 struct mlx5_core_qp *rq);
552void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev,
553 struct mlx5_core_qp *rq);
554int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
555 struct mlx5_core_qp *sq);
556void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev,
557 struct mlx5_core_qp *sq);
558int mlx5_core_alloc_q_counter(struct mlx5_core_dev *dev, u16 *counter_id);
559int mlx5_core_dealloc_q_counter(struct mlx5_core_dev *dev, u16 counter_id);
560int mlx5_core_query_q_counter(struct mlx5_core_dev *dev, u16 counter_id,
561 int reset, void *out, int out_size);
562int mlx5_core_query_out_of_buffer(struct mlx5_core_dev *dev, u16 counter_id,
563 u32 *out_of_buffer);
564
565static inline const char *mlx5_qp_type_str(int type)
566{
567 switch (type) {
568 case MLX5_QP_ST_RC: return "RC";
569 case MLX5_QP_ST_UC: return "C";
570 case MLX5_QP_ST_UD: return "UD";
571 case MLX5_QP_ST_XRC: return "XRC";
572 case MLX5_QP_ST_MLX: return "MLX";
573 case MLX5_QP_ST_QP0: return "QP0";
574 case MLX5_QP_ST_QP1: return "QP1";
575 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
576 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
577 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
578 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
579 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
580 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
581 default: return "Invalid transport type";
582 }
583}
584
585static inline const char *mlx5_qp_state_str(int state)
586{
587 switch (state) {
588 case MLX5_QP_STATE_RST:
589 return "RST";
590 case MLX5_QP_STATE_INIT:
591 return "INIT";
592 case MLX5_QP_STATE_RTR:
593 return "RTR";
594 case MLX5_QP_STATE_RTS:
595 return "RTS";
596 case MLX5_QP_STATE_SQER:
597 return "SQER";
598 case MLX5_QP_STATE_SQD:
599 return "SQD";
600 case MLX5_QP_STATE_ERR:
601 return "ERR";
602 case MLX5_QP_STATE_SQ_DRAINING:
603 return "SQ_DRAINING";
604 case MLX5_QP_STATE_SUSPENDED:
605 return "SUSPENDED";
606 default: return "Invalid QP state";
607 }
608}
609
610#endif /* MLX5_QP_H */