Linux kernel mirror (for testing)
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1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
41#include <linux/slab.h>
42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
44#include <linux/workqueue.h>
45#include <linux/interrupt.h>
46
47#include <linux/mlx5/device.h>
48#include <linux/mlx5/doorbell.h>
49#include <linux/mlx5/srq.h>
50
51enum {
52 MLX5_BOARD_ID_LEN = 64,
53 MLX5_MAX_NAME_LEN = 16,
54};
55
56enum {
57 /* one minute for the sake of bringup. Generally, commands must always
58 * complete and we may need to increase this timeout value
59 */
60 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
61 MLX5_CMD_WQ_MAX_NAME = 32,
62};
63
64enum {
65 CMD_OWNER_SW = 0x0,
66 CMD_OWNER_HW = 0x1,
67 CMD_STATUS_SUCCESS = 0,
68};
69
70enum mlx5_sqp_t {
71 MLX5_SQP_SMI = 0,
72 MLX5_SQP_GSI = 1,
73 MLX5_SQP_IEEE_1588 = 2,
74 MLX5_SQP_SNIFFER = 3,
75 MLX5_SQP_SYNC_UMR = 4,
76};
77
78enum {
79 MLX5_MAX_PORTS = 2,
80};
81
82enum {
83 MLX5_EQ_VEC_PAGES = 0,
84 MLX5_EQ_VEC_CMD = 1,
85 MLX5_EQ_VEC_ASYNC = 2,
86 MLX5_EQ_VEC_COMP_BASE,
87};
88
89enum {
90 MLX5_MAX_IRQ_NAME = 32
91};
92
93enum {
94 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
95 MLX5_ATOMIC_MODE_CX = 2 << 16,
96 MLX5_ATOMIC_MODE_8B = 3 << 16,
97 MLX5_ATOMIC_MODE_16B = 4 << 16,
98 MLX5_ATOMIC_MODE_32B = 5 << 16,
99 MLX5_ATOMIC_MODE_64B = 6 << 16,
100 MLX5_ATOMIC_MODE_128B = 7 << 16,
101 MLX5_ATOMIC_MODE_256B = 8 << 16,
102};
103
104enum {
105 MLX5_REG_QETCR = 0x4005,
106 MLX5_REG_QTCT = 0x400a,
107 MLX5_REG_DCBX_PARAM = 0x4020,
108 MLX5_REG_DCBX_APP = 0x4021,
109 MLX5_REG_PCAP = 0x5001,
110 MLX5_REG_PMTU = 0x5003,
111 MLX5_REG_PTYS = 0x5004,
112 MLX5_REG_PAOS = 0x5006,
113 MLX5_REG_PFCC = 0x5007,
114 MLX5_REG_PPCNT = 0x5008,
115 MLX5_REG_PMAOS = 0x5012,
116 MLX5_REG_PUDE = 0x5009,
117 MLX5_REG_PMPE = 0x5010,
118 MLX5_REG_PELC = 0x500e,
119 MLX5_REG_PVLC = 0x500f,
120 MLX5_REG_PCMR = 0x5041,
121 MLX5_REG_PMLP = 0x5002,
122 MLX5_REG_NODE_DESC = 0x6001,
123 MLX5_REG_HOST_ENDIANNESS = 0x7004,
124 MLX5_REG_MCIA = 0x9014,
125 MLX5_REG_MLCR = 0x902b,
126};
127
128enum mlx5_dcbx_oper_mode {
129 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
130 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
131};
132
133enum {
134 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
135 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
136};
137
138enum mlx5_page_fault_resume_flags {
139 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
140 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
141 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
142 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
143};
144
145enum dbg_rsc_type {
146 MLX5_DBG_RSC_QP,
147 MLX5_DBG_RSC_EQ,
148 MLX5_DBG_RSC_CQ,
149};
150
151struct mlx5_field_desc {
152 struct dentry *dent;
153 int i;
154};
155
156struct mlx5_rsc_debug {
157 struct mlx5_core_dev *dev;
158 void *object;
159 enum dbg_rsc_type type;
160 struct dentry *root;
161 struct mlx5_field_desc fields[0];
162};
163
164enum mlx5_dev_event {
165 MLX5_DEV_EVENT_SYS_ERROR,
166 MLX5_DEV_EVENT_PORT_UP,
167 MLX5_DEV_EVENT_PORT_DOWN,
168 MLX5_DEV_EVENT_PORT_INITIALIZED,
169 MLX5_DEV_EVENT_LID_CHANGE,
170 MLX5_DEV_EVENT_PKEY_CHANGE,
171 MLX5_DEV_EVENT_GUID_CHANGE,
172 MLX5_DEV_EVENT_CLIENT_REREG,
173};
174
175enum mlx5_port_status {
176 MLX5_PORT_UP = 1,
177 MLX5_PORT_DOWN = 2,
178};
179
180struct mlx5_uuar_info {
181 struct mlx5_uar *uars;
182 int num_uars;
183 int num_low_latency_uuars;
184 unsigned long *bitmap;
185 unsigned int *count;
186 struct mlx5_bf *bfs;
187
188 /*
189 * protect uuar allocation data structs
190 */
191 struct mutex lock;
192 u32 ver;
193};
194
195struct mlx5_bf {
196 void __iomem *reg;
197 void __iomem *regreg;
198 int buf_size;
199 struct mlx5_uar *uar;
200 unsigned long offset;
201 int need_lock;
202 /* protect blue flame buffer selection when needed
203 */
204 spinlock_t lock;
205
206 /* serialize 64 bit writes when done as two 32 bit accesses
207 */
208 spinlock_t lock32;
209 int uuarn;
210};
211
212struct mlx5_cmd_first {
213 __be32 data[4];
214};
215
216struct mlx5_cmd_msg {
217 struct list_head list;
218 struct cmd_msg_cache *parent;
219 u32 len;
220 struct mlx5_cmd_first first;
221 struct mlx5_cmd_mailbox *next;
222};
223
224struct mlx5_cmd_debug {
225 struct dentry *dbg_root;
226 struct dentry *dbg_in;
227 struct dentry *dbg_out;
228 struct dentry *dbg_outlen;
229 struct dentry *dbg_status;
230 struct dentry *dbg_run;
231 void *in_msg;
232 void *out_msg;
233 u8 status;
234 u16 inlen;
235 u16 outlen;
236};
237
238struct cmd_msg_cache {
239 /* protect block chain allocations
240 */
241 spinlock_t lock;
242 struct list_head head;
243 unsigned int max_inbox_size;
244 unsigned int num_ent;
245};
246
247enum {
248 MLX5_NUM_COMMAND_CACHES = 5,
249};
250
251struct mlx5_cmd_stats {
252 u64 sum;
253 u64 n;
254 struct dentry *root;
255 struct dentry *avg;
256 struct dentry *count;
257 /* protect command average calculations */
258 spinlock_t lock;
259};
260
261struct mlx5_cmd {
262 void *cmd_alloc_buf;
263 dma_addr_t alloc_dma;
264 int alloc_size;
265 void *cmd_buf;
266 dma_addr_t dma;
267 u16 cmdif_rev;
268 u8 log_sz;
269 u8 log_stride;
270 int max_reg_cmds;
271 int events;
272 u32 __iomem *vector;
273
274 /* protect command queue allocations
275 */
276 spinlock_t alloc_lock;
277
278 /* protect token allocations
279 */
280 spinlock_t token_lock;
281 u8 token;
282 unsigned long bitmask;
283 char wq_name[MLX5_CMD_WQ_MAX_NAME];
284 struct workqueue_struct *wq;
285 struct semaphore sem;
286 struct semaphore pages_sem;
287 int mode;
288 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
289 struct pci_pool *pool;
290 struct mlx5_cmd_debug dbg;
291 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
292 int checksum_disabled;
293 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
294};
295
296struct mlx5_port_caps {
297 int gid_table_len;
298 int pkey_table_len;
299 u8 ext_port_cap;
300};
301
302struct mlx5_cmd_mailbox {
303 void *buf;
304 dma_addr_t dma;
305 struct mlx5_cmd_mailbox *next;
306};
307
308struct mlx5_buf_list {
309 void *buf;
310 dma_addr_t map;
311};
312
313struct mlx5_buf {
314 struct mlx5_buf_list direct;
315 int npages;
316 int size;
317 u8 page_shift;
318};
319
320struct mlx5_frag_buf {
321 struct mlx5_buf_list *frags;
322 int npages;
323 int size;
324 u8 page_shift;
325};
326
327struct mlx5_eq_tasklet {
328 struct list_head list;
329 struct list_head process_list;
330 struct tasklet_struct task;
331 /* lock on completion tasklet list */
332 spinlock_t lock;
333};
334
335struct mlx5_eq {
336 struct mlx5_core_dev *dev;
337 __be32 __iomem *doorbell;
338 u32 cons_index;
339 struct mlx5_buf buf;
340 int size;
341 unsigned int irqn;
342 u8 eqn;
343 int nent;
344 u64 mask;
345 struct list_head list;
346 int index;
347 struct mlx5_rsc_debug *dbg;
348 struct mlx5_eq_tasklet tasklet_ctx;
349};
350
351struct mlx5_core_psv {
352 u32 psv_idx;
353 struct psv_layout {
354 u32 pd;
355 u16 syndrome;
356 u16 reserved;
357 u16 bg;
358 u16 app_tag;
359 u32 ref_tag;
360 } psv;
361};
362
363struct mlx5_core_sig_ctx {
364 struct mlx5_core_psv psv_memory;
365 struct mlx5_core_psv psv_wire;
366 struct ib_sig_err err_item;
367 bool sig_status_checked;
368 bool sig_err_exists;
369 u32 sigerr_count;
370};
371
372struct mlx5_core_mkey {
373 u64 iova;
374 u64 size;
375 u32 key;
376 u32 pd;
377};
378
379enum mlx5_res_type {
380 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
381 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
382 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
383 MLX5_RES_SRQ = 3,
384 MLX5_RES_XSRQ = 4,
385};
386
387struct mlx5_core_rsc_common {
388 enum mlx5_res_type res;
389 atomic_t refcount;
390 struct completion free;
391};
392
393struct mlx5_core_srq {
394 struct mlx5_core_rsc_common common; /* must be first */
395 u32 srqn;
396 int max;
397 int max_gs;
398 int max_avail_gather;
399 int wqe_shift;
400 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
401
402 atomic_t refcount;
403 struct completion free;
404};
405
406struct mlx5_eq_table {
407 void __iomem *update_ci;
408 void __iomem *update_arm_ci;
409 struct list_head comp_eqs_list;
410 struct mlx5_eq pages_eq;
411 struct mlx5_eq async_eq;
412 struct mlx5_eq cmd_eq;
413 int num_comp_vectors;
414 /* protect EQs list
415 */
416 spinlock_t lock;
417};
418
419struct mlx5_uar {
420 u32 index;
421 struct list_head bf_list;
422 unsigned free_bf_bmap;
423 void __iomem *bf_map;
424 void __iomem *map;
425};
426
427
428struct mlx5_core_health {
429 struct health_buffer __iomem *health;
430 __be32 __iomem *health_counter;
431 struct timer_list timer;
432 u32 prev;
433 int miss_counter;
434 bool sick;
435 /* wq spinlock to synchronize draining */
436 spinlock_t wq_lock;
437 struct workqueue_struct *wq;
438 unsigned long flags;
439 struct work_struct work;
440 struct delayed_work recover_work;
441};
442
443struct mlx5_cq_table {
444 /* protect radix tree
445 */
446 spinlock_t lock;
447 struct radix_tree_root tree;
448};
449
450struct mlx5_qp_table {
451 /* protect radix tree
452 */
453 spinlock_t lock;
454 struct radix_tree_root tree;
455};
456
457struct mlx5_srq_table {
458 /* protect radix tree
459 */
460 spinlock_t lock;
461 struct radix_tree_root tree;
462};
463
464struct mlx5_mkey_table {
465 /* protect radix tree
466 */
467 rwlock_t lock;
468 struct radix_tree_root tree;
469};
470
471struct mlx5_vf_context {
472 int enabled;
473};
474
475struct mlx5_core_sriov {
476 struct mlx5_vf_context *vfs_ctx;
477 int num_vfs;
478 int enabled_vfs;
479};
480
481struct mlx5_irq_info {
482 cpumask_var_t mask;
483 char name[MLX5_MAX_IRQ_NAME];
484};
485
486struct mlx5_fc_stats {
487 struct rb_root counters;
488 struct list_head addlist;
489 /* protect addlist add/splice operations */
490 spinlock_t addlist_lock;
491
492 struct workqueue_struct *wq;
493 struct delayed_work work;
494 unsigned long next_query;
495};
496
497struct mlx5_eswitch;
498struct mlx5_lag;
499
500struct mlx5_rl_entry {
501 u32 rate;
502 u16 index;
503 u16 refcount;
504};
505
506struct mlx5_rl_table {
507 /* protect rate limit table */
508 struct mutex rl_lock;
509 u16 max_size;
510 u32 max_rate;
511 u32 min_rate;
512 struct mlx5_rl_entry *rl_entry;
513};
514
515enum port_module_event_status_type {
516 MLX5_MODULE_STATUS_PLUGGED = 0x1,
517 MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
518 MLX5_MODULE_STATUS_ERROR = 0x3,
519 MLX5_MODULE_STATUS_NUM = 0x3,
520};
521
522enum port_module_event_error_type {
523 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
524 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
525 MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
526 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
527 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
528 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
529 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
530 MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
531 MLX5_MODULE_EVENT_ERROR_UNKNOWN,
532 MLX5_MODULE_EVENT_ERROR_NUM,
533};
534
535struct mlx5_port_module_event_stats {
536 u64 status_counters[MLX5_MODULE_STATUS_NUM];
537 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
538};
539
540struct mlx5_priv {
541 char name[MLX5_MAX_NAME_LEN];
542 struct mlx5_eq_table eq_table;
543 struct msix_entry *msix_arr;
544 struct mlx5_irq_info *irq_info;
545 struct mlx5_uuar_info uuari;
546 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
547
548 /* pages stuff */
549 struct workqueue_struct *pg_wq;
550 struct rb_root page_root;
551 int fw_pages;
552 atomic_t reg_pages;
553 struct list_head free_list;
554 int vfs_pages;
555
556 struct mlx5_core_health health;
557
558 struct mlx5_srq_table srq_table;
559
560 /* start: qp staff */
561 struct mlx5_qp_table qp_table;
562 struct dentry *qp_debugfs;
563 struct dentry *eq_debugfs;
564 struct dentry *cq_debugfs;
565 struct dentry *cmdif_debugfs;
566 /* end: qp staff */
567
568 /* start: cq staff */
569 struct mlx5_cq_table cq_table;
570 /* end: cq staff */
571
572 /* start: mkey staff */
573 struct mlx5_mkey_table mkey_table;
574 /* end: mkey staff */
575
576 /* start: alloc staff */
577 /* protect buffer alocation according to numa node */
578 struct mutex alloc_mutex;
579 int numa_node;
580
581 struct mutex pgdir_mutex;
582 struct list_head pgdir_list;
583 /* end: alloc staff */
584 struct dentry *dbg_root;
585
586 /* protect mkey key part */
587 spinlock_t mkey_lock;
588 u8 mkey_key;
589
590 struct list_head dev_list;
591 struct list_head ctx_list;
592 spinlock_t ctx_lock;
593
594 struct mlx5_flow_steering *steering;
595 struct mlx5_eswitch *eswitch;
596 struct mlx5_core_sriov sriov;
597 struct mlx5_lag *lag;
598 unsigned long pci_dev_data;
599 struct mlx5_fc_stats fc_stats;
600 struct mlx5_rl_table rl_table;
601
602 struct mlx5_port_module_event_stats pme_stats;
603};
604
605enum mlx5_device_state {
606 MLX5_DEVICE_STATE_UP,
607 MLX5_DEVICE_STATE_INTERNAL_ERROR,
608};
609
610enum mlx5_interface_state {
611 MLX5_INTERFACE_STATE_DOWN = BIT(0),
612 MLX5_INTERFACE_STATE_UP = BIT(1),
613 MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
614};
615
616enum mlx5_pci_status {
617 MLX5_PCI_STATUS_DISABLED,
618 MLX5_PCI_STATUS_ENABLED,
619};
620
621struct mlx5_td {
622 struct list_head tirs_list;
623 u32 tdn;
624};
625
626struct mlx5e_resources {
627 struct mlx5_uar cq_uar;
628 u32 pdn;
629 struct mlx5_td td;
630 struct mlx5_core_mkey mkey;
631};
632
633struct mlx5_core_dev {
634 struct pci_dev *pdev;
635 /* sync pci state */
636 struct mutex pci_status_mutex;
637 enum mlx5_pci_status pci_status;
638 u8 rev_id;
639 char board_id[MLX5_BOARD_ID_LEN];
640 struct mlx5_cmd cmd;
641 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
642 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
643 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
644 phys_addr_t iseg_base;
645 struct mlx5_init_seg __iomem *iseg;
646 enum mlx5_device_state state;
647 /* sync interface state */
648 struct mutex intf_state_mutex;
649 unsigned long intf_state;
650 void (*event) (struct mlx5_core_dev *dev,
651 enum mlx5_dev_event event,
652 unsigned long param);
653 struct mlx5_priv priv;
654 struct mlx5_profile *profile;
655 atomic_t num_qps;
656 u32 issi;
657 struct mlx5e_resources mlx5e_res;
658#ifdef CONFIG_RFS_ACCEL
659 struct cpu_rmap *rmap;
660#endif
661};
662
663struct mlx5_db {
664 __be32 *db;
665 union {
666 struct mlx5_db_pgdir *pgdir;
667 struct mlx5_ib_user_db_page *user_page;
668 } u;
669 dma_addr_t dma;
670 int index;
671};
672
673enum {
674 MLX5_COMP_EQ_SIZE = 1024,
675};
676
677enum {
678 MLX5_PTYS_IB = 1 << 0,
679 MLX5_PTYS_EN = 1 << 2,
680};
681
682typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
683
684struct mlx5_cmd_work_ent {
685 struct mlx5_cmd_msg *in;
686 struct mlx5_cmd_msg *out;
687 void *uout;
688 int uout_size;
689 mlx5_cmd_cbk_t callback;
690 struct delayed_work cb_timeout_work;
691 void *context;
692 int idx;
693 struct completion done;
694 struct mlx5_cmd *cmd;
695 struct work_struct work;
696 struct mlx5_cmd_layout *lay;
697 int ret;
698 int page_queue;
699 u8 status;
700 u8 token;
701 u64 ts1;
702 u64 ts2;
703 u16 op;
704};
705
706struct mlx5_pas {
707 u64 pa;
708 u8 log_sz;
709};
710
711enum port_state_policy {
712 MLX5_POLICY_DOWN = 0,
713 MLX5_POLICY_UP = 1,
714 MLX5_POLICY_FOLLOW = 2,
715 MLX5_POLICY_INVALID = 0xffffffff
716};
717
718enum phy_port_state {
719 MLX5_AAA_111
720};
721
722struct mlx5_hca_vport_context {
723 u32 field_select;
724 bool sm_virt_aware;
725 bool has_smi;
726 bool has_raw;
727 enum port_state_policy policy;
728 enum phy_port_state phys_state;
729 enum ib_port_state vport_state;
730 u8 port_physical_state;
731 u64 sys_image_guid;
732 u64 port_guid;
733 u64 node_guid;
734 u32 cap_mask1;
735 u32 cap_mask1_perm;
736 u32 cap_mask2;
737 u32 cap_mask2_perm;
738 u16 lid;
739 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
740 u8 lmc;
741 u8 subnet_timeout;
742 u16 sm_lid;
743 u8 sm_sl;
744 u16 qkey_violation_counter;
745 u16 pkey_violation_counter;
746 bool grh_required;
747};
748
749static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
750{
751 return buf->direct.buf + offset;
752}
753
754extern struct workqueue_struct *mlx5_core_wq;
755
756#define STRUCT_FIELD(header, field) \
757 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
758 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
759
760static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
761{
762 return pci_get_drvdata(pdev);
763}
764
765extern struct dentry *mlx5_debugfs_root;
766
767static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
768{
769 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
770}
771
772static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
773{
774 return ioread32be(&dev->iseg->fw_rev) >> 16;
775}
776
777static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
778{
779 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
780}
781
782static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
783{
784 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
785}
786
787static inline void *mlx5_vzalloc(unsigned long size)
788{
789 void *rtn;
790
791 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
792 if (!rtn)
793 rtn = vzalloc(size);
794 return rtn;
795}
796
797static inline u32 mlx5_base_mkey(const u32 key)
798{
799 return key & 0xffffff00u;
800}
801
802int mlx5_cmd_init(struct mlx5_core_dev *dev);
803void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
804void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
805void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
806
807int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
808 int out_size);
809int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
810 void *out, int out_size, mlx5_cmd_cbk_t callback,
811 void *context);
812void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
813
814int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
815int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
816int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
817int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
818int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
819int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar,
820 bool map_wc);
821void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
822void mlx5_health_cleanup(struct mlx5_core_dev *dev);
823int mlx5_health_init(struct mlx5_core_dev *dev);
824void mlx5_start_health_poll(struct mlx5_core_dev *dev);
825void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
826void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
827int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
828 struct mlx5_buf *buf, int node);
829int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
830void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
831int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
832 struct mlx5_frag_buf *buf, int node);
833void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
834struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
835 gfp_t flags, int npages);
836void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
837 struct mlx5_cmd_mailbox *head);
838int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
839 struct mlx5_srq_attr *in);
840int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
841int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
842 struct mlx5_srq_attr *out);
843int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
844 u16 lwm, int is_srq);
845void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
846void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
847int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
848 struct mlx5_core_mkey *mkey,
849 u32 *in, int inlen,
850 u32 *out, int outlen,
851 mlx5_cmd_cbk_t callback, void *context);
852int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
853 struct mlx5_core_mkey *mkey,
854 u32 *in, int inlen);
855int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
856 struct mlx5_core_mkey *mkey);
857int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
858 u32 *out, int outlen);
859int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
860 u32 *mkey);
861int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
862int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
863int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
864 u16 opmod, u8 port);
865void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
866void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
867int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
868void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
869void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
870 s32 npages);
871int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
872int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
873void mlx5_register_debugfs(void);
874void mlx5_unregister_debugfs(void);
875int mlx5_eq_init(struct mlx5_core_dev *dev);
876void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
877void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
878void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
879void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
880void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
881#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
882void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
883#endif
884void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
885struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
886void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
887void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
888int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
889 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
890int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
891int mlx5_start_eqs(struct mlx5_core_dev *dev);
892int mlx5_stop_eqs(struct mlx5_core_dev *dev);
893int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
894 unsigned int *irqn);
895int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
896int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
897
898int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
899void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
900int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
901 int size_in, void *data_out, int size_out,
902 u16 reg_num, int arg, int write);
903
904int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
905void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
906int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
907 u32 *out, int outlen);
908int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
909void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
910int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
911void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
912int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
913int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
914 int node);
915void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
916
917const char *mlx5_command_str(int command);
918int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
919void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
920int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
921 int npsvs, u32 *sig_index);
922int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
923void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
924int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
925 struct mlx5_odp_caps *odp_caps);
926int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
927 u8 port_num, void *out, size_t sz);
928
929int mlx5_init_rl_table(struct mlx5_core_dev *dev);
930void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
931int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
932void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
933bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
934
935static inline int fw_initializing(struct mlx5_core_dev *dev)
936{
937 return ioread32be(&dev->iseg->initializing) >> 31;
938}
939
940static inline u32 mlx5_mkey_to_idx(u32 mkey)
941{
942 return mkey >> 8;
943}
944
945static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
946{
947 return mkey_idx << 8;
948}
949
950static inline u8 mlx5_mkey_variant(u32 mkey)
951{
952 return mkey & 0xff;
953}
954
955enum {
956 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
957 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
958};
959
960enum {
961 MAX_MR_CACHE_ENTRIES = 16,
962};
963
964enum {
965 MLX5_INTERFACE_PROTOCOL_IB = 0,
966 MLX5_INTERFACE_PROTOCOL_ETH = 1,
967};
968
969struct mlx5_interface {
970 void * (*add)(struct mlx5_core_dev *dev);
971 void (*remove)(struct mlx5_core_dev *dev, void *context);
972 int (*attach)(struct mlx5_core_dev *dev, void *context);
973 void (*detach)(struct mlx5_core_dev *dev, void *context);
974 void (*event)(struct mlx5_core_dev *dev, void *context,
975 enum mlx5_dev_event event, unsigned long param);
976 void * (*get_dev)(void *context);
977 int protocol;
978 struct list_head list;
979};
980
981void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
982int mlx5_register_interface(struct mlx5_interface *intf);
983void mlx5_unregister_interface(struct mlx5_interface *intf);
984int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
985
986int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
987int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
988bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
989struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
990
991struct mlx5_profile {
992 u64 mask;
993 u8 log_max_qp;
994 struct {
995 int size;
996 int limit;
997 } mr_cache[MAX_MR_CACHE_ENTRIES];
998};
999
1000enum {
1001 MLX5_PCI_DEV_IS_VF = 1 << 0,
1002};
1003
1004static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1005{
1006 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1007}
1008
1009static inline int mlx5_get_gid_table_len(u16 param)
1010{
1011 if (param > 4) {
1012 pr_warn("gid table length is zero\n");
1013 return 0;
1014 }
1015
1016 return 8 * (1 << param);
1017}
1018
1019static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1020{
1021 return !!(dev->priv.rl_table.max_size);
1022}
1023
1024enum {
1025 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1026};
1027
1028#endif /* MLX5_DRIVER_H */