Linux kernel mirror (for testing)
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tjh.dev
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linux
1#ifndef __LINUX_GPIO_DRIVER_H
2#define __LINUX_GPIO_DRIVER_H
3
4#include <linux/device.h>
5#include <linux/types.h>
6#include <linux/irq.h>
7#include <linux/irqchip/chained_irq.h>
8#include <linux/irqdomain.h>
9#include <linux/lockdep.h>
10#include <linux/pinctrl/pinctrl.h>
11
12struct gpio_desc;
13struct of_phandle_args;
14struct device_node;
15struct seq_file;
16struct gpio_device;
17struct module;
18
19#ifdef CONFIG_GPIOLIB
20
21/**
22 * enum single_ended_mode - mode for single ended operation
23 * @LINE_MODE_PUSH_PULL: normal mode for a GPIO line, drive actively high/low
24 * @LINE_MODE_OPEN_DRAIN: set line to be open drain
25 * @LINE_MODE_OPEN_SOURCE: set line to be open source
26 */
27enum single_ended_mode {
28 LINE_MODE_PUSH_PULL,
29 LINE_MODE_OPEN_DRAIN,
30 LINE_MODE_OPEN_SOURCE,
31};
32
33/**
34 * struct gpio_chip - abstract a GPIO controller
35 * @label: a functional name for the GPIO device, such as a part
36 * number or the name of the SoC IP-block implementing it.
37 * @gpiodev: the internal state holder, opaque struct
38 * @parent: optional parent device providing the GPIOs
39 * @owner: helps prevent removal of modules exporting active GPIOs
40 * @request: optional hook for chip-specific activation, such as
41 * enabling module power and clock; may sleep
42 * @free: optional hook for chip-specific deactivation, such as
43 * disabling module power and clock; may sleep
44 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
45 * (same as GPIOF_DIR_XXX), or negative error
46 * @direction_input: configures signal "offset" as input, or returns error
47 * @direction_output: configures signal "offset" as output, or returns error
48 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
49 * @set: assigns output value for signal "offset"
50 * @set_multiple: assigns output values for multiple signals defined by "mask"
51 * @set_debounce: optional hook for setting debounce time for specified gpio in
52 * interrupt triggered gpio chips
53 * @set_single_ended: optional hook for setting a line as open drain, open
54 * source, or non-single ended (restore from open drain/source to normal
55 * push-pull mode) this should be implemented if the hardware supports
56 * open drain or open source settings. The GPIOlib will otherwise try
57 * to emulate open drain/source by not actively driving lines high/low
58 * if a consumer request this. The driver may return -ENOTSUPP if e.g.
59 * it supports just open drain but not open source and is called
60 * with LINE_MODE_OPEN_SOURCE as mode argument.
61 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
62 * implementation may not sleep
63 * @dbg_show: optional routine to show contents in debugfs; default code
64 * will be used when this is omitted, but custom code can show extra
65 * state (such as pullup/pulldown configuration).
66 * @base: identifies the first GPIO number handled by this chip;
67 * or, if negative during registration, requests dynamic ID allocation.
68 * DEPRECATION: providing anything non-negative and nailing the base
69 * offset of GPIO chips is deprecated. Please pass -1 as base to
70 * let gpiolib select the chip base in all possible cases. We want to
71 * get rid of the static GPIO number space in the long run.
72 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
73 * handled is (base + ngpio - 1).
74 * @names: if set, must be an array of strings to use as alternative
75 * names for the GPIOs in this chip. Any entry in the array
76 * may be NULL if there is no alias for the GPIO, however the
77 * array must be @ngpio entries long. A name can include a single printk
78 * format specifier for an unsigned int. It is substituted by the actual
79 * number of the gpio.
80 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
81 * must while accessing GPIO expander chips over I2C or SPI. This
82 * implies that if the chip supports IRQs, these IRQs need to be threaded
83 * as the chip access may sleep when e.g. reading out the IRQ status
84 * registers.
85 * @read_reg: reader function for generic GPIO
86 * @write_reg: writer function for generic GPIO
87 * @pin2mask: some generic GPIO controllers work with the big-endian bits
88 * notation, e.g. in a 8-bits register, GPIO7 is the least significant
89 * bit. This callback assigns the right bit mask.
90 * @reg_dat: data (in) register for generic GPIO
91 * @reg_set: output set register (out=high) for generic GPIO
92 * @reg_clr: output clear register (out=low) for generic GPIO
93 * @reg_dir: direction setting register for generic GPIO
94 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
95 * <register width> * 8
96 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
97 * shadowed and real data registers writes together.
98 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
99 * safely.
100 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
101 * direction safely.
102 * @irqchip: GPIO IRQ chip impl, provided by GPIO driver
103 * @irqdomain: Interrupt translation domain; responsible for mapping
104 * between GPIO hwirq number and linux irq number
105 * @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated)
106 * @irq_handler: the irq handler to use (often a predefined irq core function)
107 * for GPIO IRQs, provided by GPIO driver
108 * @irq_default_type: default IRQ triggering type applied during GPIO driver
109 * initialization, provided by GPIO driver
110 * @irq_chained_parent: GPIO IRQ chip parent/bank linux irq number,
111 * provided by GPIO driver for chained interrupt (not for nested
112 * interrupts).
113 * @irq_nested: True if set the interrupt handling is nested.
114 * @irq_need_valid_mask: If set core allocates @irq_valid_mask with all
115 * bits set to one
116 * @irq_valid_mask: If not %NULL holds bitmask of GPIOs which are valid to
117 * be included in IRQ domain of the chip
118 * @lock_key: per GPIO IRQ chip lockdep class
119 *
120 * A gpio_chip can help platforms abstract various sources of GPIOs so
121 * they can all be accessed through a common programing interface.
122 * Example sources would be SOC controllers, FPGAs, multifunction
123 * chips, dedicated GPIO expanders, and so on.
124 *
125 * Each chip controls a number of signals, identified in method calls
126 * by "offset" values in the range 0..(@ngpio - 1). When those signals
127 * are referenced through calls like gpio_get_value(gpio), the offset
128 * is calculated by subtracting @base from the gpio number.
129 */
130struct gpio_chip {
131 const char *label;
132 struct gpio_device *gpiodev;
133 struct device *parent;
134 struct module *owner;
135
136 int (*request)(struct gpio_chip *chip,
137 unsigned offset);
138 void (*free)(struct gpio_chip *chip,
139 unsigned offset);
140 int (*get_direction)(struct gpio_chip *chip,
141 unsigned offset);
142 int (*direction_input)(struct gpio_chip *chip,
143 unsigned offset);
144 int (*direction_output)(struct gpio_chip *chip,
145 unsigned offset, int value);
146 int (*get)(struct gpio_chip *chip,
147 unsigned offset);
148 void (*set)(struct gpio_chip *chip,
149 unsigned offset, int value);
150 void (*set_multiple)(struct gpio_chip *chip,
151 unsigned long *mask,
152 unsigned long *bits);
153 int (*set_debounce)(struct gpio_chip *chip,
154 unsigned offset,
155 unsigned debounce);
156 int (*set_single_ended)(struct gpio_chip *chip,
157 unsigned offset,
158 enum single_ended_mode mode);
159
160 int (*to_irq)(struct gpio_chip *chip,
161 unsigned offset);
162
163 void (*dbg_show)(struct seq_file *s,
164 struct gpio_chip *chip);
165 int base;
166 u16 ngpio;
167 const char *const *names;
168 bool can_sleep;
169
170#if IS_ENABLED(CONFIG_GPIO_GENERIC)
171 unsigned long (*read_reg)(void __iomem *reg);
172 void (*write_reg)(void __iomem *reg, unsigned long data);
173 unsigned long (*pin2mask)(struct gpio_chip *gc, unsigned int pin);
174 void __iomem *reg_dat;
175 void __iomem *reg_set;
176 void __iomem *reg_clr;
177 void __iomem *reg_dir;
178 int bgpio_bits;
179 spinlock_t bgpio_lock;
180 unsigned long bgpio_data;
181 unsigned long bgpio_dir;
182#endif
183
184#ifdef CONFIG_GPIOLIB_IRQCHIP
185 /*
186 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
187 * to handle IRQs for most practical cases.
188 */
189 struct irq_chip *irqchip;
190 struct irq_domain *irqdomain;
191 unsigned int irq_base;
192 irq_flow_handler_t irq_handler;
193 unsigned int irq_default_type;
194 int irq_chained_parent;
195 bool irq_nested;
196 bool irq_need_valid_mask;
197 unsigned long *irq_valid_mask;
198 struct lock_class_key *lock_key;
199#endif
200
201#if defined(CONFIG_OF_GPIO)
202 /*
203 * If CONFIG_OF is enabled, then all GPIO controllers described in the
204 * device tree automatically may have an OF translation
205 */
206 struct device_node *of_node;
207 int of_gpio_n_cells;
208 int (*of_xlate)(struct gpio_chip *gc,
209 const struct of_phandle_args *gpiospec, u32 *flags);
210#endif
211};
212
213extern const char *gpiochip_is_requested(struct gpio_chip *chip,
214 unsigned offset);
215
216/* add/remove chips */
217extern int gpiochip_add_data(struct gpio_chip *chip, void *data);
218static inline int gpiochip_add(struct gpio_chip *chip)
219{
220 return gpiochip_add_data(chip, NULL);
221}
222extern void gpiochip_remove(struct gpio_chip *chip);
223extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
224 void *data);
225extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip);
226
227extern struct gpio_chip *gpiochip_find(void *data,
228 int (*match)(struct gpio_chip *chip, void *data));
229
230/* lock/unlock as IRQ */
231int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
232void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
233bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
234
235/* Line status inquiry for drivers */
236bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
237bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
238
239/* get driver data */
240void *gpiochip_get_data(struct gpio_chip *chip);
241
242struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
243
244struct bgpio_pdata {
245 const char *label;
246 int base;
247 int ngpio;
248};
249
250#if IS_ENABLED(CONFIG_GPIO_GENERIC)
251
252int bgpio_init(struct gpio_chip *gc, struct device *dev,
253 unsigned long sz, void __iomem *dat, void __iomem *set,
254 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
255 unsigned long flags);
256
257#define BGPIOF_BIG_ENDIAN BIT(0)
258#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
259#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
260#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
261#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
262#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
263
264#endif
265
266#ifdef CONFIG_GPIOLIB_IRQCHIP
267
268void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
269 struct irq_chip *irqchip,
270 int parent_irq,
271 irq_flow_handler_t parent_handler);
272
273void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
274 struct irq_chip *irqchip,
275 int parent_irq);
276
277int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
278 struct irq_chip *irqchip,
279 unsigned int first_irq,
280 irq_flow_handler_t handler,
281 unsigned int type,
282 bool nested,
283 struct lock_class_key *lock_key);
284
285#ifdef CONFIG_LOCKDEP
286
287/*
288 * Lockdep requires that each irqchip instance be created with a
289 * unique key so as to avoid unnecessary warnings. This upfront
290 * boilerplate static inlines provides such a key for each
291 * unique instance.
292 */
293static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
294 struct irq_chip *irqchip,
295 unsigned int first_irq,
296 irq_flow_handler_t handler,
297 unsigned int type)
298{
299 static struct lock_class_key key;
300
301 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
302 handler, type, false, &key);
303}
304
305static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
306 struct irq_chip *irqchip,
307 unsigned int first_irq,
308 irq_flow_handler_t handler,
309 unsigned int type)
310{
311
312 static struct lock_class_key key;
313
314 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
315 handler, type, true, &key);
316}
317#else
318static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
319 struct irq_chip *irqchip,
320 unsigned int first_irq,
321 irq_flow_handler_t handler,
322 unsigned int type)
323{
324 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
325 handler, type, false, NULL);
326}
327
328static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
329 struct irq_chip *irqchip,
330 unsigned int first_irq,
331 irq_flow_handler_t handler,
332 unsigned int type)
333{
334 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
335 handler, type, true, NULL);
336}
337#endif /* CONFIG_LOCKDEP */
338
339#endif /* CONFIG_GPIOLIB_IRQCHIP */
340
341int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
342void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
343
344#ifdef CONFIG_PINCTRL
345
346/**
347 * struct gpio_pin_range - pin range controlled by a gpio chip
348 * @head: list for maintaining set of pin ranges, used internally
349 * @pctldev: pinctrl device which handles corresponding pins
350 * @range: actual range of pins controlled by a gpio controller
351 */
352
353struct gpio_pin_range {
354 struct list_head node;
355 struct pinctrl_dev *pctldev;
356 struct pinctrl_gpio_range range;
357};
358
359int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
360 unsigned int gpio_offset, unsigned int pin_offset,
361 unsigned int npins);
362int gpiochip_add_pingroup_range(struct gpio_chip *chip,
363 struct pinctrl_dev *pctldev,
364 unsigned int gpio_offset, const char *pin_group);
365void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
366
367#else
368
369static inline int
370gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
371 unsigned int gpio_offset, unsigned int pin_offset,
372 unsigned int npins)
373{
374 return 0;
375}
376static inline int
377gpiochip_add_pingroup_range(struct gpio_chip *chip,
378 struct pinctrl_dev *pctldev,
379 unsigned int gpio_offset, const char *pin_group)
380{
381 return 0;
382}
383
384static inline void
385gpiochip_remove_pin_ranges(struct gpio_chip *chip)
386{
387}
388
389#endif /* CONFIG_PINCTRL */
390
391struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
392 const char *label);
393void gpiochip_free_own_desc(struct gpio_desc *desc);
394
395#else /* CONFIG_GPIOLIB */
396
397static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
398{
399 /* GPIO can never have been requested */
400 WARN_ON(1);
401 return ERR_PTR(-ENODEV);
402}
403
404#endif /* CONFIG_GPIOLIB */
405
406#endif