tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * File: mac.c
16 *
17 * Purpose: MAC routines
18 *
19 * Author: Tevin Chen
20 *
21 * Date: May 21, 1996
22 *
23 * Functions:
24 * MACbIsRegBitsOn - Test if All test Bits On
25 * MACbIsRegBitsOff - Test if All test Bits Off
26 * MACbIsIntDisable - Test if MAC interrupt disable
27 * MACvSetShortRetryLimit - Set 802.11 Short Retry limit
28 * MACvSetLongRetryLimit - Set 802.11 Long Retry limit
29 * MACvSetLoopbackMode - Set MAC Loopback Mode
30 * MACvSaveContext - Save Context of MAC Registers
31 * MACvRestoreContext - Restore Context of MAC Registers
32 * MACbSoftwareReset - Software Reset MAC
33 * MACbSafeRxOff - Turn Off MAC Rx
34 * MACbSafeTxOff - Turn Off MAC Tx
35 * MACbSafeStop - Stop MAC function
36 * MACbShutdown - Shut down MAC
37 * MACvInitialize - Initialize MAC
38 * MACvSetCurrRxDescAddr - Set Rx Descriptors Address
39 * MACvSetCurrTx0DescAddr - Set Tx0 Descriptors Address
40 * MACvSetCurrTx1DescAddr - Set Tx1 Descriptors Address
41 * MACvTimer0MicroSDelay - Micro Second Delay Loop by MAC
42 *
43 * Revision History:
44 * 08-22-2003 Kyle Hsu : Porting MAC functions from sim53
45 * 09-03-2003 Bryan YC Fan : Add MACvClearBusSusInd()&
46 * MACvEnableBusSusEn()
47 * 09-18-2003 Jerry Chen : Add MACvSetKeyEntry & MACvDisableKeyEntry
48 *
49 */
50
51#include "tmacro.h"
52#include "mac.h"
53
54/*
55 * Description:
56 * Test if all test bits on
57 *
58 * Parameters:
59 * In:
60 * io_base - Base Address for MAC
61 * byRegOfs - Offset of MAC Register
62 * byTestBits - Test bits
63 * Out:
64 * none
65 *
66 * Return Value: true if all test bits On; otherwise false
67 *
68 */
69bool MACbIsRegBitsOn(struct vnt_private *priv, unsigned char byRegOfs,
70 unsigned char byTestBits)
71{
72 void __iomem *io_base = priv->PortOffset;
73
74 return (ioread8(io_base + byRegOfs) & byTestBits) == byTestBits;
75}
76
77/*
78 * Description:
79 * Test if all test bits off
80 *
81 * Parameters:
82 * In:
83 * io_base - Base Address for MAC
84 * byRegOfs - Offset of MAC Register
85 * byTestBits - Test bits
86 * Out:
87 * none
88 *
89 * Return Value: true if all test bits Off; otherwise false
90 *
91 */
92bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs,
93 unsigned char byTestBits)
94{
95 void __iomem *io_base = priv->PortOffset;
96
97 return !(ioread8(io_base + byRegOfs) & byTestBits);
98}
99
100/*
101 * Description:
102 * Test if MAC interrupt disable
103 *
104 * Parameters:
105 * In:
106 * io_base - Base Address for MAC
107 * Out:
108 * none
109 *
110 * Return Value: true if interrupt is disable; otherwise false
111 *
112 */
113bool MACbIsIntDisable(struct vnt_private *priv)
114{
115 void __iomem *io_base = priv->PortOffset;
116
117 if (ioread32(io_base + MAC_REG_IMR))
118 return false;
119
120 return true;
121}
122
123/*
124 * Description:
125 * Set 802.11 Short Retry Limit
126 *
127 * Parameters:
128 * In:
129 * io_base - Base Address for MAC
130 * byRetryLimit- Retry Limit
131 * Out:
132 * none
133 *
134 * Return Value: none
135 *
136 */
137void MACvSetShortRetryLimit(struct vnt_private *priv,
138 unsigned char byRetryLimit)
139{
140 void __iomem *io_base = priv->PortOffset;
141 /* set SRT */
142 iowrite8(byRetryLimit, io_base + MAC_REG_SRT);
143}
144
145/*
146 * Description:
147 * Set 802.11 Long Retry Limit
148 *
149 * Parameters:
150 * In:
151 * io_base - Base Address for MAC
152 * byRetryLimit- Retry Limit
153 * Out:
154 * none
155 *
156 * Return Value: none
157 *
158 */
159void MACvSetLongRetryLimit(struct vnt_private *priv,
160 unsigned char byRetryLimit)
161{
162 void __iomem *io_base = priv->PortOffset;
163 /* set LRT */
164 iowrite8(byRetryLimit, io_base + MAC_REG_LRT);
165}
166
167/*
168 * Description:
169 * Set MAC Loopback mode
170 *
171 * Parameters:
172 * In:
173 * io_base - Base Address for MAC
174 * byLoopbackMode - Loopback Mode
175 * Out:
176 * none
177 *
178 * Return Value: none
179 *
180 */
181void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode)
182{
183 void __iomem *io_base = priv->PortOffset;
184
185 byLoopbackMode <<= 6;
186 /* set TCR */
187 iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode,
188 io_base + MAC_REG_TEST);
189}
190
191/*
192 * Description:
193 * Save MAC registers to context buffer
194 *
195 * Parameters:
196 * In:
197 * io_base - Base Address for MAC
198 * Out:
199 * cxt_buf - Context buffer
200 *
201 * Return Value: none
202 *
203 */
204void MACvSaveContext(struct vnt_private *priv, unsigned char *cxt_buf)
205{
206 void __iomem *io_base = priv->PortOffset;
207
208 /* read page0 register */
209 memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0);
210
211 MACvSelectPage1(io_base);
212
213 /* read page1 register */
214 memcpy_fromio(cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, io_base,
215 MAC_MAX_CONTEXT_SIZE_PAGE1);
216
217 MACvSelectPage0(io_base);
218}
219
220/*
221 * Description:
222 * Restore MAC registers from context buffer
223 *
224 * Parameters:
225 * In:
226 * io_base - Base Address for MAC
227 * cxt_buf - Context buffer
228 * Out:
229 * none
230 *
231 * Return Value: none
232 *
233 */
234void MACvRestoreContext(struct vnt_private *priv, unsigned char *cxt_buf)
235{
236 void __iomem *io_base = priv->PortOffset;
237
238 MACvSelectPage1(io_base);
239 /* restore page1 */
240 memcpy_toio(io_base, cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0,
241 MAC_MAX_CONTEXT_SIZE_PAGE1);
242
243 MACvSelectPage0(io_base);
244
245 /* restore RCR,TCR,IMR... */
246 memcpy_toio(io_base + MAC_REG_RCR, cxt_buf + MAC_REG_RCR,
247 MAC_REG_ISR - MAC_REG_RCR);
248
249 /* restore MAC Config. */
250 memcpy_toio(io_base + MAC_REG_LRT, cxt_buf + MAC_REG_LRT,
251 MAC_REG_PAGE1SEL - MAC_REG_LRT);
252
253 iowrite8(*(cxt_buf + MAC_REG_CFG), io_base + MAC_REG_CFG);
254
255 /* restore PS Config. */
256 memcpy_toio(io_base + MAC_REG_PSCFG, cxt_buf + MAC_REG_PSCFG,
257 MAC_REG_BBREGCTL - MAC_REG_PSCFG);
258
259 /* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */
260 iowrite32(*(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0),
261 io_base + MAC_REG_TXDMAPTR0);
262 iowrite32(*(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR),
263 io_base + MAC_REG_AC0DMAPTR);
264 iowrite32(*(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR),
265 io_base + MAC_REG_BCNDMAPTR);
266 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0),
267 io_base + MAC_REG_RXDMAPTR0);
268 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1),
269 io_base + MAC_REG_RXDMAPTR1);
270}
271
272/*
273 * Description:
274 * Software Reset MAC
275 *
276 * Parameters:
277 * In:
278 * io_base - Base Address for MAC
279 * Out:
280 * none
281 *
282 * Return Value: true if Reset Success; otherwise false
283 *
284 */
285bool MACbSoftwareReset(struct vnt_private *priv)
286{
287 void __iomem *io_base = priv->PortOffset;
288 unsigned short ww;
289
290 /* turn on HOSTCR_SOFTRST, just write 0x01 to reset */
291 iowrite8(0x01, io_base + MAC_REG_HOSTCR);
292
293 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
294 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_SOFTRST))
295 break;
296 }
297 if (ww == W_MAX_TIMEOUT)
298 return false;
299 return true;
300}
301
302/*
303 * Description:
304 * save some important register's value, then do reset, then restore
305 * register's value
306 *
307 * Parameters:
308 * In:
309 * io_base - Base Address for MAC
310 * Out:
311 * none
312 *
313 * Return Value: true if success; otherwise false
314 *
315 */
316bool MACbSafeSoftwareReset(struct vnt_private *priv)
317{
318 unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1];
319 bool bRetVal;
320
321 /* PATCH....
322 * save some important register's value, then do
323 * reset, then restore register's value
324 */
325 /* save MAC context */
326 MACvSaveContext(priv, abyTmpRegData);
327 /* do reset */
328 bRetVal = MACbSoftwareReset(priv);
329 /* restore MAC context, except CR0 */
330 MACvRestoreContext(priv, abyTmpRegData);
331
332 return bRetVal;
333}
334
335/*
336 * Description:
337 * Turn Off MAC Rx
338 *
339 * Parameters:
340 * In:
341 * io_base - Base Address for MAC
342 * Out:
343 * none
344 *
345 * Return Value: true if success; otherwise false
346 *
347 */
348bool MACbSafeRxOff(struct vnt_private *priv)
349{
350 void __iomem *io_base = priv->PortOffset;
351 unsigned short ww;
352
353 /* turn off wow temp for turn off Rx safely */
354
355 /* Clear RX DMA0,1 */
356 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0);
357 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1);
358 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
359 if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
360 break;
361 }
362 if (ww == W_MAX_TIMEOUT) {
363 pr_debug(" DBG_PORT80(0x10)\n");
364 return false;
365 }
366 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
367 if (!(ioread32(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
368 break;
369 }
370 if (ww == W_MAX_TIMEOUT) {
371 pr_debug(" DBG_PORT80(0x11)\n");
372 return false;
373 }
374
375 /* try to safe shutdown RX */
376 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_RXON);
377 /* W_MAX_TIMEOUT is the timeout period */
378 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
379 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_RXONST))
380 break;
381 }
382 if (ww == W_MAX_TIMEOUT) {
383 pr_debug(" DBG_PORT80(0x12)\n");
384 return false;
385 }
386 return true;
387}
388
389/*
390 * Description:
391 * Turn Off MAC Tx
392 *
393 * Parameters:
394 * In:
395 * io_base - Base Address for MAC
396 * Out:
397 * none
398 *
399 * Return Value: true if success; otherwise false
400 *
401 */
402bool MACbSafeTxOff(struct vnt_private *priv)
403{
404 void __iomem *io_base = priv->PortOffset;
405 unsigned short ww;
406
407 /* Clear TX DMA */
408 /* Tx0 */
409 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0);
410 /* AC0 */
411 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL);
412
413 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
414 if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
415 break;
416 }
417 if (ww == W_MAX_TIMEOUT) {
418 pr_debug(" DBG_PORT80(0x20)\n");
419 return false;
420 }
421 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
422 if (!(ioread32(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
423 break;
424 }
425 if (ww == W_MAX_TIMEOUT) {
426 pr_debug(" DBG_PORT80(0x21)\n");
427 return false;
428 }
429
430 /* try to safe shutdown TX */
431 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_TXON);
432
433 /* W_MAX_TIMEOUT is the timeout period */
434 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
435 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_TXONST))
436 break;
437 }
438 if (ww == W_MAX_TIMEOUT) {
439 pr_debug(" DBG_PORT80(0x24)\n");
440 return false;
441 }
442 return true;
443}
444
445/*
446 * Description:
447 * Stop MAC function
448 *
449 * Parameters:
450 * In:
451 * io_base - Base Address for MAC
452 * Out:
453 * none
454 *
455 * Return Value: true if success; otherwise false
456 *
457 */
458bool MACbSafeStop(struct vnt_private *priv)
459{
460 void __iomem *io_base = priv->PortOffset;
461
462 MACvRegBitsOff(io_base, MAC_REG_TCR, TCR_AUTOBCNTX);
463
464 if (!MACbSafeRxOff(priv)) {
465 pr_debug(" MACbSafeRxOff == false)\n");
466 MACbSafeSoftwareReset(priv);
467 return false;
468 }
469 if (!MACbSafeTxOff(priv)) {
470 pr_debug(" MACbSafeTxOff == false)\n");
471 MACbSafeSoftwareReset(priv);
472 return false;
473 }
474
475 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_MACEN);
476
477 return true;
478}
479
480/*
481 * Description:
482 * Shut Down MAC
483 *
484 * Parameters:
485 * In:
486 * io_base - Base Address for MAC
487 * Out:
488 * none
489 *
490 * Return Value: true if success; otherwise false
491 *
492 */
493bool MACbShutdown(struct vnt_private *priv)
494{
495 void __iomem *io_base = priv->PortOffset;
496 /* disable MAC IMR */
497 MACvIntDisable(io_base);
498 MACvSetLoopbackMode(priv, MAC_LB_INTERNAL);
499 /* stop the adapter */
500 if (!MACbSafeStop(priv)) {
501 MACvSetLoopbackMode(priv, MAC_LB_NONE);
502 return false;
503 }
504 MACvSetLoopbackMode(priv, MAC_LB_NONE);
505 return true;
506}
507
508/*
509 * Description:
510 * Initialize MAC
511 *
512 * Parameters:
513 * In:
514 * io_base - Base Address for MAC
515 * Out:
516 * none
517 *
518 * Return Value: none
519 *
520 */
521void MACvInitialize(struct vnt_private *priv)
522{
523 void __iomem *io_base = priv->PortOffset;
524 /* clear sticky bits */
525 MACvClearStckDS(io_base);
526 /* disable force PME-enable */
527 iowrite8(PME_OVR, io_base + MAC_REG_PMC1);
528 /* only 3253 A */
529
530 /* do reset */
531 MACbSoftwareReset(priv);
532
533 /* reset TSF counter */
534 iowrite8(TFTCTL_TSFCNTRST, io_base + MAC_REG_TFTCTL);
535 /* enable TSF counter */
536 iowrite8(TFTCTL_TSFCNTREN, io_base + MAC_REG_TFTCTL);
537}
538
539/*
540 * Description:
541 * Set the chip with current rx descriptor address
542 *
543 * Parameters:
544 * In:
545 * io_base - Base Address for MAC
546 * curr_desc_addr - Descriptor Address
547 * Out:
548 * none
549 *
550 * Return Value: none
551 *
552 */
553void MACvSetCurrRx0DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
554{
555 void __iomem *io_base = priv->PortOffset;
556 unsigned short ww;
557 unsigned char org_dma_ctl;
558
559 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL0);
560 if (org_dma_ctl & DMACTL_RUN)
561 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0 + 2);
562
563 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
564 if (!(ioread8(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
565 break;
566 }
567
568 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR0);
569 if (org_dma_ctl & DMACTL_RUN)
570 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0);
571}
572
573/*
574 * Description:
575 * Set the chip with current rx descriptor address
576 *
577 * Parameters:
578 * In:
579 * io_base - Base Address for MAC
580 * curr_desc_addr - Descriptor Address
581 * Out:
582 * none
583 *
584 * Return Value: none
585 *
586 */
587void MACvSetCurrRx1DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
588{
589 void __iomem *io_base = priv->PortOffset;
590 unsigned short ww;
591 unsigned char org_dma_ctl;
592
593 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL1);
594 if (org_dma_ctl & DMACTL_RUN)
595 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1 + 2);
596
597 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
598 if (!(ioread8(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
599 break;
600 }
601
602 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR1);
603 if (org_dma_ctl & DMACTL_RUN)
604 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1);
605
606}
607
608/*
609 * Description:
610 * Set the chip with current tx0 descriptor address
611 *
612 * Parameters:
613 * In:
614 * io_base - Base Address for MAC
615 * curr_desc_addr - Descriptor Address
616 * Out:
617 * none
618 *
619 * Return Value: none
620 *
621 */
622void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv,
623 u32 curr_desc_addr)
624{
625 void __iomem *io_base = priv->PortOffset;
626 unsigned short ww;
627 unsigned char org_dma_ctl;
628
629 org_dma_ctl = ioread8(io_base + MAC_REG_TXDMACTL0);
630 if (org_dma_ctl & DMACTL_RUN)
631 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0 + 2);
632
633 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
634 if (!(ioread8(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
635 break;
636 }
637
638 iowrite32(curr_desc_addr, io_base + MAC_REG_TXDMAPTR0);
639 if (org_dma_ctl & DMACTL_RUN)
640 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0);
641}
642
643/*
644 * Description:
645 * Set the chip with current AC0 descriptor address
646 *
647 * Parameters:
648 * In:
649 * io_base - Base Address for MAC
650 * curr_desc_addr - Descriptor Address
651 * Out:
652 * none
653 *
654 * Return Value: none
655 *
656 */
657/* TxDMA1 = AC0DMA */
658void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv,
659 u32 curr_desc_addr)
660{
661 void __iomem *io_base = priv->PortOffset;
662 unsigned short ww;
663 unsigned char org_dma_ctl;
664
665 org_dma_ctl = ioread8(io_base + MAC_REG_AC0DMACTL);
666 if (org_dma_ctl & DMACTL_RUN)
667 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL + 2);
668
669 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
670 if (!(ioread8(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
671 break;
672 }
673 if (ww == W_MAX_TIMEOUT)
674 pr_debug(" DBG_PORT80(0x26)\n");
675 iowrite32(curr_desc_addr, io_base + MAC_REG_AC0DMAPTR);
676 if (org_dma_ctl & DMACTL_RUN)
677 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL);
678}
679
680void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv,
681 u32 curr_desc_addr)
682{
683 if (iTxType == TYPE_AC0DMA)
684 MACvSetCurrAC0DescAddrEx(priv, curr_desc_addr);
685 else if (iTxType == TYPE_TXDMA0)
686 MACvSetCurrTx0DescAddrEx(priv, curr_desc_addr);
687}
688
689/*
690 * Description:
691 * Micro Second Delay via MAC
692 *
693 * Parameters:
694 * In:
695 * io_base - Base Address for MAC
696 * uDelay - Delay time (timer resolution is 4 us)
697 * Out:
698 * none
699 *
700 * Return Value: none
701 *
702 */
703void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay)
704{
705 void __iomem *io_base = priv->PortOffset;
706 unsigned char byValue;
707 unsigned int uu, ii;
708
709 iowrite8(0, io_base + MAC_REG_TMCTL0);
710 iowrite32(uDelay, io_base + MAC_REG_TMDATA0);
711 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL0);
712 for (ii = 0; ii < 66; ii++) { /* assume max PCI clock is 66Mhz */
713 for (uu = 0; uu < uDelay; uu++) {
714 byValue = ioread8(io_base + MAC_REG_TMCTL0);
715 if ((byValue == 0) ||
716 (byValue & TMCTL_TSUSP)) {
717 iowrite8(0, io_base + MAC_REG_TMCTL0);
718 return;
719 }
720 }
721 }
722 iowrite8(0, io_base + MAC_REG_TMCTL0);
723}
724
725/*
726 * Description:
727 * Micro Second One shot timer via MAC
728 *
729 * Parameters:
730 * In:
731 * io_base - Base Address for MAC
732 * uDelay - Delay time
733 * Out:
734 * none
735 *
736 * Return Value: none
737 *
738 */
739void MACvOneShotTimer1MicroSec(struct vnt_private *priv,
740 unsigned int uDelayTime)
741{
742 void __iomem *io_base = priv->PortOffset;
743
744 iowrite8(0, io_base + MAC_REG_TMCTL1);
745 iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1);
746 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL1);
747}
748
749void MACvSetMISCFifo(struct vnt_private *priv, unsigned short offset,
750 u32 data)
751{
752 void __iomem *io_base = priv->PortOffset;
753
754 if (offset > 273)
755 return;
756 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
757 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
758 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
759}
760
761bool MACbPSWakeup(struct vnt_private *priv)
762{
763 void __iomem *io_base = priv->PortOffset;
764 unsigned int ww;
765 /* Read PSCTL */
766 if (MACbIsRegBitsOff(priv, MAC_REG_PSCTL, PSCTL_PS))
767 return true;
768
769 /* Disable PS */
770 MACvRegBitsOff(io_base, MAC_REG_PSCTL, PSCTL_PSEN);
771
772 /* Check if SyncFlushOK */
773 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
774 if (ioread8(io_base + MAC_REG_PSCTL) & PSCTL_WAKEDONE)
775 break;
776 }
777 if (ww == W_MAX_TIMEOUT) {
778 pr_debug(" DBG_PORT80(0x33)\n");
779 return false;
780 }
781 return true;
782}
783
784/*
785 * Description:
786 * Set the Key by MISCFIFO
787 *
788 * Parameters:
789 * In:
790 * io_base - Base Address for MAC
791 *
792 * Out:
793 * none
794 *
795 * Return Value: none
796 *
797 */
798
799void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
800 unsigned int uEntryIdx, unsigned int uKeyIdx,
801 unsigned char *pbyAddr, u32 *pdwKey,
802 unsigned char byLocalID)
803{
804 void __iomem *io_base = priv->PortOffset;
805 unsigned short offset;
806 u32 data;
807 int ii;
808
809 if (byLocalID <= 1)
810 return;
811
812 pr_debug("MACvSetKeyEntry\n");
813 offset = MISCFIFO_KEYETRY0;
814 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
815
816 data = 0;
817 data |= wKeyCtl;
818 data <<= 16;
819 data |= MAKEWORD(*(pbyAddr + 4), *(pbyAddr + 5));
820 pr_debug("1. offset: %d, Data: %X, KeyCtl:%X\n",
821 offset, data, wKeyCtl);
822
823 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
824 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
825 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
826 offset++;
827
828 data = 0;
829 data |= *(pbyAddr + 3);
830 data <<= 8;
831 data |= *(pbyAddr + 2);
832 data <<= 8;
833 data |= *(pbyAddr + 1);
834 data <<= 8;
835 data |= *pbyAddr;
836 pr_debug("2. offset: %d, Data: %X\n", offset, data);
837
838 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
839 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
840 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
841 offset++;
842
843 offset += (uKeyIdx * 4);
844 for (ii = 0; ii < 4; ii++) {
845 /* always push 128 bits */
846 pr_debug("3.(%d) offset: %d, Data: %X\n",
847 ii, offset + ii, *pdwKey);
848 iowrite16(offset + ii, io_base + MAC_REG_MISCFFNDEX);
849 iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA);
850 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
851 }
852}
853
854/*
855 * Description:
856 * Disable the Key Entry by MISCFIFO
857 *
858 * Parameters:
859 * In:
860 * io_base - Base Address for MAC
861 *
862 * Out:
863 * none
864 *
865 * Return Value: none
866 *
867 */
868void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx)
869{
870 void __iomem *io_base = priv->PortOffset;
871 unsigned short offset;
872
873 offset = MISCFIFO_KEYETRY0;
874 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
875
876 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
877 iowrite32(0, io_base + MAC_REG_MISCFFDATA);
878 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
879}