tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
20
21#define FDMI_DID 0xfffffaU
22#define NameServer_DID 0xfffffcU
23#define SCR_DID 0xfffffdU
24#define Fabric_DID 0xfffffeU
25#define Bcast_DID 0xffffffU
26#define Mask_DID 0xffffffU
27#define CT_DID_MASK 0xffff00U
28#define Fabric_DID_MASK 0xfff000U
29#define WELL_KNOWN_DID_MASK 0xfffff0U
30
31#define PT2PT_LocalID 1
32#define PT2PT_RemoteID 2
33
34#define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35#define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36#define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */
37#define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
38
39#define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
40 0 */
41
42#define FCELSSIZE 1024 /* maximum ELS transfer size */
43
44#define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
45#define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
46#define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47#define LPFC_FCP_NEXT_RING 3
48#define LPFC_FCP_OAS_RING 3
49
50#define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
51#define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
52#define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
53#define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
54#define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
55#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
56#define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
57#define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
58#define SLI2_IOCB_CMD_R3_ENTRIES 0
59#define SLI2_IOCB_RSP_R3_ENTRIES 0
60#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62
63#define SLI2_IOCB_CMD_SIZE 32
64#define SLI2_IOCB_RSP_SIZE 32
65#define SLI3_IOCB_CMD_SIZE 128
66#define SLI3_IOCB_RSP_SIZE 64
67
68#define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
69#define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
70
71/* vendor ID used in SCSI netlink calls */
72#define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
73
74#define FW_REV_STR_SIZE 32
75/* Common Transport structures and definitions */
76
77union CtRevisionId {
78 /* Structure is in Big Endian format */
79 struct {
80 uint32_t Revision:8;
81 uint32_t InId:24;
82 } bits;
83 uint32_t word;
84};
85
86union CtCommandResponse {
87 /* Structure is in Big Endian format */
88 struct {
89 uint32_t CmdRsp:16;
90 uint32_t Size:16;
91 } bits;
92 uint32_t word;
93};
94
95#define FC4_FEATURE_INIT 0x2
96#define FC4_FEATURE_TARGET 0x1
97
98struct lpfc_sli_ct_request {
99 /* Structure is in Big Endian format */
100 union CtRevisionId RevisionId;
101 uint8_t FsType;
102 uint8_t FsSubType;
103 uint8_t Options;
104 uint8_t Rsrvd1;
105 union CtCommandResponse CommandResponse;
106 uint8_t Rsrvd2;
107 uint8_t ReasonCode;
108 uint8_t Explanation;
109 uint8_t VendorUnique;
110#define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */
111
112 union {
113 uint32_t PortID;
114 struct gid {
115 uint8_t PortType; /* for GID_PT requests */
116 uint8_t DomainScope;
117 uint8_t AreaScope;
118 uint8_t Fc4Type; /* for GID_FT requests */
119 } gid;
120 struct rft {
121 uint32_t PortId; /* For RFT_ID requests */
122
123#ifdef __BIG_ENDIAN_BITFIELD
124 uint32_t rsvd0:16;
125 uint32_t rsvd1:7;
126 uint32_t fcpReg:1; /* Type 8 */
127 uint32_t rsvd2:2;
128 uint32_t ipReg:1; /* Type 5 */
129 uint32_t rsvd3:5;
130#else /* __LITTLE_ENDIAN_BITFIELD */
131 uint32_t rsvd0:16;
132 uint32_t fcpReg:1; /* Type 8 */
133 uint32_t rsvd1:7;
134 uint32_t rsvd3:5;
135 uint32_t ipReg:1; /* Type 5 */
136 uint32_t rsvd2:2;
137#endif
138
139 uint32_t rsvd[7];
140 } rft;
141 struct rnn {
142 uint32_t PortId; /* For RNN_ID requests */
143 uint8_t wwnn[8];
144 } rnn;
145 struct rsnn { /* For RSNN_ID requests */
146 uint8_t wwnn[8];
147 uint8_t len;
148 uint8_t symbname[255];
149 } rsnn;
150 struct da_id { /* For DA_ID requests */
151 uint32_t port_id;
152 } da_id;
153 struct rspn { /* For RSPN_ID requests */
154 uint32_t PortId;
155 uint8_t len;
156 uint8_t symbname[255];
157 } rspn;
158 struct gff {
159 uint32_t PortId;
160 } gff;
161 struct gff_acc {
162 uint8_t fbits[128];
163 } gff_acc;
164#define FCP_TYPE_FEATURE_OFFSET 7
165 struct rff {
166 uint32_t PortId;
167 uint8_t reserved[2];
168 uint8_t fbits;
169 uint8_t type_code; /* type=8 for FCP */
170 } rff;
171 } un;
172};
173
174#define LPFC_MAX_CT_SIZE (60 * 4096)
175
176#define SLI_CT_REVISION 1
177#define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
178 sizeof(struct gid))
179#define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
180 sizeof(struct gff))
181#define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
182 sizeof(struct rft))
183#define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
184 sizeof(struct rff))
185#define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
186 sizeof(struct rnn))
187#define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
188 sizeof(struct rsnn))
189#define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
190 sizeof(struct da_id))
191#define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
192 sizeof(struct rspn))
193
194/*
195 * FsType Definitions
196 */
197
198#define SLI_CT_MANAGEMENT_SERVICE 0xFA
199#define SLI_CT_TIME_SERVICE 0xFB
200#define SLI_CT_DIRECTORY_SERVICE 0xFC
201#define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
202
203/*
204 * Directory Service Subtypes
205 */
206
207#define SLI_CT_DIRECTORY_NAME_SERVER 0x02
208
209/*
210 * Response Codes
211 */
212
213#define SLI_CT_RESPONSE_FS_RJT 0x8001
214#define SLI_CT_RESPONSE_FS_ACC 0x8002
215
216/*
217 * Reason Codes
218 */
219
220#define SLI_CT_NO_ADDITIONAL_EXPL 0x0
221#define SLI_CT_INVALID_COMMAND 0x01
222#define SLI_CT_INVALID_VERSION 0x02
223#define SLI_CT_LOGICAL_ERROR 0x03
224#define SLI_CT_INVALID_IU_SIZE 0x04
225#define SLI_CT_LOGICAL_BUSY 0x05
226#define SLI_CT_PROTOCOL_ERROR 0x07
227#define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
228#define SLI_CT_REQ_NOT_SUPPORTED 0x0b
229#define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
230#define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
231#define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
232#define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
233#define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
234#define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
235#define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
236#define SLI_CT_VENDOR_UNIQUE 0xff
237
238/*
239 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
240 */
241
242#define SLI_CT_NO_PORT_ID 0x01
243#define SLI_CT_NO_PORT_NAME 0x02
244#define SLI_CT_NO_NODE_NAME 0x03
245#define SLI_CT_NO_CLASS_OF_SERVICE 0x04
246#define SLI_CT_NO_IP_ADDRESS 0x05
247#define SLI_CT_NO_IPA 0x06
248#define SLI_CT_NO_FC4_TYPES 0x07
249#define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
250#define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
251#define SLI_CT_NO_PORT_TYPE 0x0A
252#define SLI_CT_ACCESS_DENIED 0x10
253#define SLI_CT_INVALID_PORT_ID 0x11
254#define SLI_CT_DATABASE_EMPTY 0x12
255
256/*
257 * Name Server Command Codes
258 */
259
260#define SLI_CTNS_GA_NXT 0x0100
261#define SLI_CTNS_GPN_ID 0x0112
262#define SLI_CTNS_GNN_ID 0x0113
263#define SLI_CTNS_GCS_ID 0x0114
264#define SLI_CTNS_GFT_ID 0x0117
265#define SLI_CTNS_GSPN_ID 0x0118
266#define SLI_CTNS_GPT_ID 0x011A
267#define SLI_CTNS_GFF_ID 0x011F
268#define SLI_CTNS_GID_PN 0x0121
269#define SLI_CTNS_GID_NN 0x0131
270#define SLI_CTNS_GIP_NN 0x0135
271#define SLI_CTNS_GIPA_NN 0x0136
272#define SLI_CTNS_GSNN_NN 0x0139
273#define SLI_CTNS_GNN_IP 0x0153
274#define SLI_CTNS_GIPA_IP 0x0156
275#define SLI_CTNS_GID_FT 0x0171
276#define SLI_CTNS_GID_PT 0x01A1
277#define SLI_CTNS_RPN_ID 0x0212
278#define SLI_CTNS_RNN_ID 0x0213
279#define SLI_CTNS_RCS_ID 0x0214
280#define SLI_CTNS_RFT_ID 0x0217
281#define SLI_CTNS_RSPN_ID 0x0218
282#define SLI_CTNS_RPT_ID 0x021A
283#define SLI_CTNS_RFF_ID 0x021F
284#define SLI_CTNS_RIP_NN 0x0235
285#define SLI_CTNS_RIPA_NN 0x0236
286#define SLI_CTNS_RSNN_NN 0x0239
287#define SLI_CTNS_DA_ID 0x0300
288
289/*
290 * Port Types
291 */
292
293#define SLI_CTPT_N_PORT 0x01
294#define SLI_CTPT_NL_PORT 0x02
295#define SLI_CTPT_FNL_PORT 0x03
296#define SLI_CTPT_IP 0x04
297#define SLI_CTPT_FCP 0x08
298#define SLI_CTPT_NX_PORT 0x7F
299#define SLI_CTPT_F_PORT 0x81
300#define SLI_CTPT_FL_PORT 0x82
301#define SLI_CTPT_E_PORT 0x84
302
303#define SLI_CT_LAST_ENTRY 0x80000000
304
305/* Fibre Channel Service Parameter definitions */
306
307#define FC_PH_4_0 6 /* FC-PH version 4.0 */
308#define FC_PH_4_1 7 /* FC-PH version 4.1 */
309#define FC_PH_4_2 8 /* FC-PH version 4.2 */
310#define FC_PH_4_3 9 /* FC-PH version 4.3 */
311
312#define FC_PH_LOW 8 /* Lowest supported FC-PH version */
313#define FC_PH_HIGH 9 /* Highest supported FC-PH version */
314#define FC_PH3 0x20 /* FC-PH-3 version */
315
316#define FF_FRAME_SIZE 2048
317
318struct lpfc_name {
319 union {
320 struct {
321#ifdef __BIG_ENDIAN_BITFIELD
322 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
323 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
324 8:11 of IEEE ext */
325#else /* __LITTLE_ENDIAN_BITFIELD */
326 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
327 8:11 of IEEE ext */
328 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
329#endif
330
331#define NAME_IEEE 0x1 /* IEEE name - nameType */
332#define NAME_IEEE_EXT 0x2 /* IEEE extended name */
333#define NAME_FC_TYPE 0x3 /* FC native name type */
334#define NAME_IP_TYPE 0x4 /* IP address */
335#define NAME_CCITT_TYPE 0xC
336#define NAME_CCITT_GR_TYPE 0xE
337 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
338 extended Lsb */
339 uint8_t IEEE[6]; /* FC IEEE address */
340 } s;
341 uint8_t wwn[8];
342 } u;
343};
344
345struct csp {
346 uint8_t fcphHigh; /* FC Word 0, byte 0 */
347 uint8_t fcphLow;
348 uint8_t bbCreditMsb;
349 uint8_t bbCreditLsb; /* FC Word 0, byte 3 */
350
351/*
352 * Word 1 Bit 31 in common service parameter is overloaded.
353 * Word 1 Bit 31 in FLOGI request is multiple NPort request
354 * Word 1 Bit 31 in FLOGI response is clean address bit
355 */
356#define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
357/*
358 * Word 1 Bit 30 in common service parameter is overloaded.
359 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
360 * Word 1 Bit 30 in PLOGI request is random offset
361 */
362#define virtual_fabric_support randomOffset /* Word 1, bit 30 */
363#ifdef __BIG_ENDIAN_BITFIELD
364 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
365 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
366 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
367 uint16_t fPort:1; /* FC Word 1, bit 28 */
368 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
369 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
370 uint16_t multicast:1; /* FC Word 1, bit 25 */
371 uint16_t broadcast:1; /* FC Word 1, bit 24 */
372
373 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
374 uint16_t simplex:1; /* FC Word 1, bit 22 */
375 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
376 uint16_t dhd:1; /* FC Word 1, bit 18 */
377 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
378 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
379#else /* __LITTLE_ENDIAN_BITFIELD */
380 uint16_t broadcast:1; /* FC Word 1, bit 24 */
381 uint16_t multicast:1; /* FC Word 1, bit 25 */
382 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
383 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
384 uint16_t fPort:1; /* FC Word 1, bit 28 */
385 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
386 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
387 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
388
389 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
390 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
391 uint16_t dhd:1; /* FC Word 1, bit 18 */
392 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
393 uint16_t simplex:1; /* FC Word 1, bit 22 */
394 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
395#endif
396
397 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
398 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
399 union {
400 struct {
401 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
402
403 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
404 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
405
406 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
407 } nPort;
408 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
409 } w2;
410
411 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
412};
413
414struct class_parms {
415#ifdef __BIG_ENDIAN_BITFIELD
416 uint8_t classValid:1; /* FC Word 0, bit 31 */
417 uint8_t intermix:1; /* FC Word 0, bit 30 */
418 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
419 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
420 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
421 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
422#else /* __LITTLE_ENDIAN_BITFIELD */
423 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
424 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
425 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
426 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
427 uint8_t intermix:1; /* FC Word 0, bit 30 */
428 uint8_t classValid:1; /* FC Word 0, bit 31 */
429
430#endif
431
432 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
433
434#ifdef __BIG_ENDIAN_BITFIELD
435 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
436 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
437 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
438 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
439 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
440#else /* __LITTLE_ENDIAN_BITFIELD */
441 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
442 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
443 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
444 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
445 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
446#endif
447
448 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
449
450#ifdef __BIG_ENDIAN_BITFIELD
451 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
452 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
453 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
454 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
455 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
456 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
457#else /* __LITTLE_ENDIAN_BITFIELD */
458 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
459 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
460 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
461 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
462 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
463 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
464#endif
465
466 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
467 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
468 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
469
470 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
471 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
472 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
473 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
474
475 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
476 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
477 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
478 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
479};
480
481struct serv_parm { /* Structure is in Big Endian format */
482 struct csp cmn;
483 struct lpfc_name portName;
484 struct lpfc_name nodeName;
485 struct class_parms cls1;
486 struct class_parms cls2;
487 struct class_parms cls3;
488 struct class_parms cls4;
489 uint8_t vendorVersion[16];
490};
491
492/*
493 * Virtual Fabric Tagging Header
494 */
495struct fc_vft_header {
496 uint32_t word0;
497#define fc_vft_hdr_r_ctl_SHIFT 24
498#define fc_vft_hdr_r_ctl_MASK 0xFF
499#define fc_vft_hdr_r_ctl_WORD word0
500#define fc_vft_hdr_ver_SHIFT 22
501#define fc_vft_hdr_ver_MASK 0x3
502#define fc_vft_hdr_ver_WORD word0
503#define fc_vft_hdr_type_SHIFT 18
504#define fc_vft_hdr_type_MASK 0xF
505#define fc_vft_hdr_type_WORD word0
506#define fc_vft_hdr_e_SHIFT 16
507#define fc_vft_hdr_e_MASK 0x1
508#define fc_vft_hdr_e_WORD word0
509#define fc_vft_hdr_priority_SHIFT 13
510#define fc_vft_hdr_priority_MASK 0x7
511#define fc_vft_hdr_priority_WORD word0
512#define fc_vft_hdr_vf_id_SHIFT 1
513#define fc_vft_hdr_vf_id_MASK 0xFFF
514#define fc_vft_hdr_vf_id_WORD word0
515 uint32_t word1;
516#define fc_vft_hdr_hopct_SHIFT 24
517#define fc_vft_hdr_hopct_MASK 0xFF
518#define fc_vft_hdr_hopct_WORD word1
519};
520
521/*
522 * Extended Link Service LS_COMMAND codes (Payload Word 0)
523 */
524#ifdef __BIG_ENDIAN_BITFIELD
525#define ELS_CMD_MASK 0xffff0000
526#define ELS_RSP_MASK 0xff000000
527#define ELS_CMD_LS_RJT 0x01000000
528#define ELS_CMD_ACC 0x02000000
529#define ELS_CMD_PLOGI 0x03000000
530#define ELS_CMD_FLOGI 0x04000000
531#define ELS_CMD_LOGO 0x05000000
532#define ELS_CMD_ABTX 0x06000000
533#define ELS_CMD_RCS 0x07000000
534#define ELS_CMD_RES 0x08000000
535#define ELS_CMD_RSS 0x09000000
536#define ELS_CMD_RSI 0x0A000000
537#define ELS_CMD_ESTS 0x0B000000
538#define ELS_CMD_ESTC 0x0C000000
539#define ELS_CMD_ADVC 0x0D000000
540#define ELS_CMD_RTV 0x0E000000
541#define ELS_CMD_RLS 0x0F000000
542#define ELS_CMD_ECHO 0x10000000
543#define ELS_CMD_TEST 0x11000000
544#define ELS_CMD_RRQ 0x12000000
545#define ELS_CMD_REC 0x13000000
546#define ELS_CMD_RDP 0x18000000
547#define ELS_CMD_PRLI 0x20100014
548#define ELS_CMD_PRLO 0x21100014
549#define ELS_CMD_PRLO_ACC 0x02100014
550#define ELS_CMD_PDISC 0x50000000
551#define ELS_CMD_FDISC 0x51000000
552#define ELS_CMD_ADISC 0x52000000
553#define ELS_CMD_FARP 0x54000000
554#define ELS_CMD_FARPR 0x55000000
555#define ELS_CMD_RPS 0x56000000
556#define ELS_CMD_RPL 0x57000000
557#define ELS_CMD_FAN 0x60000000
558#define ELS_CMD_RSCN 0x61040000
559#define ELS_CMD_SCR 0x62000000
560#define ELS_CMD_RNID 0x78000000
561#define ELS_CMD_LIRR 0x7A000000
562#define ELS_CMD_LCB 0x81000000
563#else /* __LITTLE_ENDIAN_BITFIELD */
564#define ELS_CMD_MASK 0xffff
565#define ELS_RSP_MASK 0xff
566#define ELS_CMD_LS_RJT 0x01
567#define ELS_CMD_ACC 0x02
568#define ELS_CMD_PLOGI 0x03
569#define ELS_CMD_FLOGI 0x04
570#define ELS_CMD_LOGO 0x05
571#define ELS_CMD_ABTX 0x06
572#define ELS_CMD_RCS 0x07
573#define ELS_CMD_RES 0x08
574#define ELS_CMD_RSS 0x09
575#define ELS_CMD_RSI 0x0A
576#define ELS_CMD_ESTS 0x0B
577#define ELS_CMD_ESTC 0x0C
578#define ELS_CMD_ADVC 0x0D
579#define ELS_CMD_RTV 0x0E
580#define ELS_CMD_RLS 0x0F
581#define ELS_CMD_ECHO 0x10
582#define ELS_CMD_TEST 0x11
583#define ELS_CMD_RRQ 0x12
584#define ELS_CMD_REC 0x13
585#define ELS_CMD_RDP 0x18
586#define ELS_CMD_PRLI 0x14001020
587#define ELS_CMD_PRLO 0x14001021
588#define ELS_CMD_PRLO_ACC 0x14001002
589#define ELS_CMD_PDISC 0x50
590#define ELS_CMD_FDISC 0x51
591#define ELS_CMD_ADISC 0x52
592#define ELS_CMD_FARP 0x54
593#define ELS_CMD_FARPR 0x55
594#define ELS_CMD_RPS 0x56
595#define ELS_CMD_RPL 0x57
596#define ELS_CMD_FAN 0x60
597#define ELS_CMD_RSCN 0x0461
598#define ELS_CMD_SCR 0x62
599#define ELS_CMD_RNID 0x78
600#define ELS_CMD_LIRR 0x7A
601#define ELS_CMD_LCB 0x81
602#endif
603
604/*
605 * LS_RJT Payload Definition
606 */
607
608struct ls_rjt { /* Structure is in Big Endian format */
609 union {
610 uint32_t lsRjtError;
611 struct {
612 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
613
614 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
615 /* LS_RJT reason codes */
616#define LSRJT_INVALID_CMD 0x01
617#define LSRJT_LOGICAL_ERR 0x03
618#define LSRJT_LOGICAL_BSY 0x05
619#define LSRJT_PROTOCOL_ERR 0x07
620#define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
621#define LSRJT_CMD_UNSUPPORTED 0x0B
622#define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
623
624 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
625 /* LS_RJT reason explanation */
626#define LSEXP_NOTHING_MORE 0x00
627#define LSEXP_SPARM_OPTIONS 0x01
628#define LSEXP_SPARM_ICTL 0x03
629#define LSEXP_SPARM_RCTL 0x05
630#define LSEXP_SPARM_RCV_SIZE 0x07
631#define LSEXP_SPARM_CONCUR_SEQ 0x09
632#define LSEXP_SPARM_CREDIT 0x0B
633#define LSEXP_INVALID_PNAME 0x0D
634#define LSEXP_INVALID_NNAME 0x0E
635#define LSEXP_INVALID_CSP 0x0F
636#define LSEXP_INVALID_ASSOC_HDR 0x11
637#define LSEXP_ASSOC_HDR_REQ 0x13
638#define LSEXP_INVALID_O_SID 0x15
639#define LSEXP_INVALID_OX_RX 0x17
640#define LSEXP_CMD_IN_PROGRESS 0x19
641#define LSEXP_PORT_LOGIN_REQ 0x1E
642#define LSEXP_INVALID_NPORT_ID 0x1F
643#define LSEXP_INVALID_SEQ_ID 0x21
644#define LSEXP_INVALID_XCHG 0x23
645#define LSEXP_INACTIVE_XCHG 0x25
646#define LSEXP_RQ_REQUIRED 0x27
647#define LSEXP_OUT_OF_RESOURCE 0x29
648#define LSEXP_CANT_GIVE_DATA 0x2A
649#define LSEXP_REQ_UNSUPPORTED 0x2C
650 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
651 } b;
652 } un;
653};
654
655/*
656 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
657 */
658
659typedef struct _LOGO { /* Structure is in Big Endian format */
660 union {
661 uint32_t nPortId32; /* Access nPortId as a word */
662 struct {
663 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
664 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
665 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
666 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
667 } b;
668 } un;
669 struct lpfc_name portName; /* N_port name field */
670} LOGO;
671
672/*
673 * FCP Login (PRLI Request / ACC) Payload Definition
674 */
675
676#define PRLX_PAGE_LEN 0x10
677#define TPRLO_PAGE_LEN 0x14
678
679typedef struct _PRLI { /* Structure is in Big Endian format */
680 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
681
682#define PRLI_FCP_TYPE 0x08
683 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
684
685#ifdef __BIG_ENDIAN_BITFIELD
686 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
687 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
688 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
689
690 /* ACC = imagePairEstablished */
691 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
692 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
693#else /* __LITTLE_ENDIAN_BITFIELD */
694 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
695 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
696 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
697 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
698 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
699 /* ACC = imagePairEstablished */
700#endif
701
702#define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
703#define PRLI_NO_RESOURCES 0x2
704#define PRLI_INIT_INCOMPLETE 0x3
705#define PRLI_NO_SUCH_PA 0x4
706#define PRLI_PREDEF_CONFIG 0x5
707#define PRLI_PARTIAL_SUCCESS 0x6
708#define PRLI_INVALID_PAGE_CNT 0x7
709 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
710
711 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
712
713 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
714
715 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
716 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
717
718#ifdef __BIG_ENDIAN_BITFIELD
719 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
720 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
721 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
722 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
723 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
724 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
725 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
726 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
727 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
728 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
729 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
730 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
731 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
732 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
733 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
734 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
735#else /* __LITTLE_ENDIAN_BITFIELD */
736 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
737 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
738 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
739 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
740 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
741 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
742 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
743 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
744 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
745 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
746 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
747 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
748 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
749 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
750 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
751 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
752#endif
753} PRLI;
754
755/*
756 * FCP Logout (PRLO Request / ACC) Payload Definition
757 */
758
759typedef struct _PRLO { /* Structure is in Big Endian format */
760 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
761
762#define PRLO_FCP_TYPE 0x08
763 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
764
765#ifdef __BIG_ENDIAN_BITFIELD
766 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
767 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
768 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
769 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
770#else /* __LITTLE_ENDIAN_BITFIELD */
771 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
772 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
773 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
774 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
775#endif
776
777#define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
778#define PRLO_NO_SUCH_IMAGE 0x4
779#define PRLO_INVALID_PAGE_CNT 0x7
780
781 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
782
783 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
784
785 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
786
787 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
788} PRLO;
789
790typedef struct _ADISC { /* Structure is in Big Endian format */
791 uint32_t hardAL_PA;
792 struct lpfc_name portName;
793 struct lpfc_name nodeName;
794 uint32_t DID;
795} ADISC;
796
797typedef struct _FARP { /* Structure is in Big Endian format */
798 uint32_t Mflags:8;
799 uint32_t Odid:24;
800#define FARP_NO_ACTION 0 /* FARP information enclosed, no
801 action */
802#define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
803#define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
804#define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
805#define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
806 supported */
807#define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
808 supported */
809 uint32_t Rflags:8;
810 uint32_t Rdid:24;
811#define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
812#define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
813 struct lpfc_name OportName;
814 struct lpfc_name OnodeName;
815 struct lpfc_name RportName;
816 struct lpfc_name RnodeName;
817 uint8_t Oipaddr[16];
818 uint8_t Ripaddr[16];
819} FARP;
820
821typedef struct _FAN { /* Structure is in Big Endian format */
822 uint32_t Fdid;
823 struct lpfc_name FportName;
824 struct lpfc_name FnodeName;
825} FAN;
826
827typedef struct _SCR { /* Structure is in Big Endian format */
828 uint8_t resvd1;
829 uint8_t resvd2;
830 uint8_t resvd3;
831 uint8_t Function;
832#define SCR_FUNC_FABRIC 0x01
833#define SCR_FUNC_NPORT 0x02
834#define SCR_FUNC_FULL 0x03
835#define SCR_CLEAR 0xff
836} SCR;
837
838typedef struct _RNID_TOP_DISC {
839 struct lpfc_name portName;
840 uint8_t resvd[8];
841 uint32_t unitType;
842#define RNID_HBA 0x7
843#define RNID_HOST 0xa
844#define RNID_DRIVER 0xd
845 uint32_t physPort;
846 uint32_t attachedNodes;
847 uint16_t ipVersion;
848#define RNID_IPV4 0x1
849#define RNID_IPV6 0x2
850 uint16_t UDPport;
851 uint8_t ipAddr[16];
852 uint16_t resvd1;
853 uint16_t flags;
854#define RNID_TD_SUPPORT 0x1
855#define RNID_LP_VALID 0x2
856} RNID_TOP_DISC;
857
858typedef struct _RNID { /* Structure is in Big Endian format */
859 uint8_t Format;
860#define RNID_TOPOLOGY_DISC 0xdf
861 uint8_t CommonLen;
862 uint8_t resvd1;
863 uint8_t SpecificLen;
864 struct lpfc_name portName;
865 struct lpfc_name nodeName;
866 union {
867 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
868 } un;
869} RNID;
870
871typedef struct _RPS { /* Structure is in Big Endian format */
872 union {
873 uint32_t portNum;
874 struct lpfc_name portName;
875 } un;
876} RPS;
877
878typedef struct _RPS_RSP { /* Structure is in Big Endian format */
879 uint16_t rsvd1;
880 uint16_t portStatus;
881 uint32_t linkFailureCnt;
882 uint32_t lossSyncCnt;
883 uint32_t lossSignalCnt;
884 uint32_t primSeqErrCnt;
885 uint32_t invalidXmitWord;
886 uint32_t crcCnt;
887} RPS_RSP;
888
889struct RLS { /* Structure is in Big Endian format */
890 uint32_t rls;
891#define rls_rsvd_SHIFT 24
892#define rls_rsvd_MASK 0x000000ff
893#define rls_rsvd_WORD rls
894#define rls_did_SHIFT 0
895#define rls_did_MASK 0x00ffffff
896#define rls_did_WORD rls
897};
898
899struct RLS_RSP { /* Structure is in Big Endian format */
900 uint32_t linkFailureCnt;
901 uint32_t lossSyncCnt;
902 uint32_t lossSignalCnt;
903 uint32_t primSeqErrCnt;
904 uint32_t invalidXmitWord;
905 uint32_t crcCnt;
906};
907
908struct RRQ { /* Structure is in Big Endian format */
909 uint32_t rrq;
910#define rrq_rsvd_SHIFT 24
911#define rrq_rsvd_MASK 0x000000ff
912#define rrq_rsvd_WORD rrq
913#define rrq_did_SHIFT 0
914#define rrq_did_MASK 0x00ffffff
915#define rrq_did_WORD rrq
916 uint32_t rrq_exchg;
917#define rrq_oxid_SHIFT 16
918#define rrq_oxid_MASK 0xffff
919#define rrq_oxid_WORD rrq_exchg
920#define rrq_rxid_SHIFT 0
921#define rrq_rxid_MASK 0xffff
922#define rrq_rxid_WORD rrq_exchg
923};
924
925#define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
926#define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
927
928struct RTV_RSP { /* Structure is in Big Endian format */
929 uint32_t ratov;
930 uint32_t edtov;
931 uint32_t qtov;
932#define qtov_rsvd0_SHIFT 28
933#define qtov_rsvd0_MASK 0x0000000f
934#define qtov_rsvd0_WORD qtov /* reserved */
935#define qtov_edtovres_SHIFT 27
936#define qtov_edtovres_MASK 0x00000001
937#define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
938#define qtov__rsvd1_SHIFT 19
939#define qtov_rsvd1_MASK 0x0000003f
940#define qtov_rsvd1_WORD qtov /* reserved */
941#define qtov_rttov_SHIFT 18
942#define qtov_rttov_MASK 0x00000001
943#define qtov_rttov_WORD qtov /* R_T_TOV value */
944#define qtov_rsvd2_SHIFT 0
945#define qtov_rsvd2_MASK 0x0003ffff
946#define qtov_rsvd2_WORD qtov /* reserved */
947};
948
949
950typedef struct _RPL { /* Structure is in Big Endian format */
951 uint32_t maxsize;
952 uint32_t index;
953} RPL;
954
955typedef struct _PORT_NUM_BLK {
956 uint32_t portNum;
957 uint32_t portID;
958 struct lpfc_name portName;
959} PORT_NUM_BLK;
960
961typedef struct _RPL_RSP { /* Structure is in Big Endian format */
962 uint32_t listLen;
963 uint32_t index;
964 PORT_NUM_BLK port_num_blk;
965} RPL_RSP;
966
967/* This is used for RSCN command */
968typedef struct _D_ID { /* Structure is in Big Endian format */
969 union {
970 uint32_t word;
971 struct {
972#ifdef __BIG_ENDIAN_BITFIELD
973 uint8_t resv;
974 uint8_t domain;
975 uint8_t area;
976 uint8_t id;
977#else /* __LITTLE_ENDIAN_BITFIELD */
978 uint8_t id;
979 uint8_t area;
980 uint8_t domain;
981 uint8_t resv;
982#endif
983 } b;
984 } un;
985} D_ID;
986
987#define RSCN_ADDRESS_FORMAT_PORT 0x0
988#define RSCN_ADDRESS_FORMAT_AREA 0x1
989#define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
990#define RSCN_ADDRESS_FORMAT_FABRIC 0x3
991#define RSCN_ADDRESS_FORMAT_MASK 0x3
992
993/*
994 * Structure to define all ELS Payload types
995 */
996
997typedef struct _ELS_PKT { /* Structure is in Big Endian format */
998 uint8_t elsCode; /* FC Word 0, bit 24:31 */
999 uint8_t elsByte1;
1000 uint8_t elsByte2;
1001 uint8_t elsByte3;
1002 union {
1003 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
1004 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
1005 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
1006 PRLI prli; /* Payload for PRLI/ACC */
1007 PRLO prlo; /* Payload for PRLO/ACC */
1008 ADISC adisc; /* Payload for ADISC/ACC */
1009 FARP farp; /* Payload for FARP/ACC */
1010 FAN fan; /* Payload for FAN */
1011 SCR scr; /* Payload for SCR/ACC */
1012 RNID rnid; /* Payload for RNID */
1013 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
1014 } un;
1015} ELS_PKT;
1016
1017/*
1018 * Link Cable Beacon (LCB) ELS Frame
1019 */
1020
1021struct fc_lcb_request_frame {
1022 uint32_t lcb_command; /* ELS command opcode (0x81) */
1023 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1024#define LPFC_LCB_ON 0x1
1025#define LPFC_LCB_OFF 0x2
1026 uint8_t reserved[3];
1027
1028 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1029#define LPFC_LCB_GREEN 0x1
1030#define LPFC_LCB_AMBER 0x2
1031 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1032 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1033};
1034
1035/*
1036 * Link Cable Beacon (LCB) ELS Response Frame
1037 */
1038struct fc_lcb_res_frame {
1039 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */
1040 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1041 uint8_t reserved[3];
1042 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1043 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1044 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1045};
1046
1047/*
1048 * Read Diagnostic Parameters (RDP) ELS frame.
1049 */
1050#define SFF_PG0_IDENT_SFP 0x3
1051
1052#define SFP_FLAG_PT_OPTICAL 0x0
1053#define SFP_FLAG_PT_SWLASER 0x01
1054#define SFP_FLAG_PT_LWLASER_LC1310 0x02
1055#define SFP_FLAG_PT_LWLASER_LL1550 0x03
1056#define SFP_FLAG_PT_MASK 0x0F
1057#define SFP_FLAG_PT_SHIFT 0
1058
1059#define SFP_FLAG_IS_OPTICAL_PORT 0x01
1060#define SFP_FLAG_IS_OPTICAL_MASK 0x010
1061#define SFP_FLAG_IS_OPTICAL_SHIFT 4
1062
1063#define SFP_FLAG_IS_DESC_VALID 0x01
1064#define SFP_FLAG_IS_DESC_VALID_MASK 0x020
1065#define SFP_FLAG_IS_DESC_VALID_SHIFT 5
1066
1067#define SFP_FLAG_CT_UNKNOWN 0x0
1068#define SFP_FLAG_CT_SFP_PLUS 0x01
1069#define SFP_FLAG_CT_MASK 0x3C
1070#define SFP_FLAG_CT_SHIFT 6
1071
1072struct fc_rdp_port_name_info {
1073 uint8_t wwnn[8];
1074 uint8_t wwpn[8];
1075};
1076
1077
1078/*
1079 * Link Error Status Block Structure (FC-FS-3) for RDP
1080 * This similar to RPS ELS
1081 */
1082struct fc_link_status {
1083 uint32_t link_failure_cnt;
1084 uint32_t loss_of_synch_cnt;
1085 uint32_t loss_of_signal_cnt;
1086 uint32_t primitive_seq_proto_err;
1087 uint32_t invalid_trans_word;
1088 uint32_t invalid_crc_cnt;
1089
1090};
1091
1092#define RDP_PORT_NAMES_DESC_TAG 0x00010003
1093struct fc_rdp_port_name_desc {
1094 uint32_t tag; /* 0001 0003h */
1095 uint32_t length; /* set to size of payload struct */
1096 struct fc_rdp_port_name_info port_names;
1097};
1098
1099
1100struct fc_rdp_fec_info {
1101 uint32_t CorrectedBlocks;
1102 uint32_t UncorrectableBlocks;
1103};
1104
1105#define RDP_FEC_DESC_TAG 0x00010005
1106struct fc_fec_rdp_desc {
1107 uint32_t tag;
1108 uint32_t length;
1109 struct fc_rdp_fec_info info;
1110};
1111
1112struct fc_rdp_link_error_status_payload_info {
1113 struct fc_link_status link_status; /* 24 bytes */
1114 uint32_t port_type; /* bits 31-30 only */
1115};
1116
1117#define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
1118struct fc_rdp_link_error_status_desc {
1119 uint32_t tag; /* 0001 0002h */
1120 uint32_t length; /* set to size of payload struct */
1121 struct fc_rdp_link_error_status_payload_info info;
1122};
1123
1124#define VN_PT_PHY_UNKNOWN 0x00
1125#define VN_PT_PHY_PF_PORT 0x01
1126#define VN_PT_PHY_ETH_MAC 0x10
1127#define VN_PT_PHY_SHIFT 30
1128
1129#define RDP_PS_1GB 0x8000
1130#define RDP_PS_2GB 0x4000
1131#define RDP_PS_4GB 0x2000
1132#define RDP_PS_10GB 0x1000
1133#define RDP_PS_8GB 0x0800
1134#define RDP_PS_16GB 0x0400
1135#define RDP_PS_32GB 0x0200
1136
1137#define RDP_CAP_USER_CONFIGURED 0x0002
1138#define RDP_CAP_UNKNOWN 0x0001
1139#define RDP_PS_UNKNOWN 0x0002
1140#define RDP_PS_NOT_ESTABLISHED 0x0001
1141
1142struct fc_rdp_port_speed {
1143 uint16_t capabilities;
1144 uint16_t speed;
1145};
1146
1147struct fc_rdp_port_speed_info {
1148 struct fc_rdp_port_speed port_speed;
1149};
1150
1151#define RDP_PORT_SPEED_DESC_TAG 0x00010001
1152struct fc_rdp_port_speed_desc {
1153 uint32_t tag; /* 00010001h */
1154 uint32_t length; /* set to size of payload struct */
1155 struct fc_rdp_port_speed_info info;
1156};
1157
1158#define RDP_NPORT_ID_SIZE 4
1159#define RDP_N_PORT_DESC_TAG 0x00000003
1160struct fc_rdp_nport_desc {
1161 uint32_t tag; /* 0000 0003h, big endian */
1162 uint32_t length; /* size of RDP_N_PORT_ID struct */
1163 uint32_t nport_id : 12;
1164 uint32_t reserved : 8;
1165};
1166
1167
1168struct fc_rdp_link_service_info {
1169 uint32_t els_req; /* Request payload word 0 value.*/
1170};
1171
1172#define RDP_LINK_SERVICE_DESC_TAG 0x00000001
1173struct fc_rdp_link_service_desc {
1174 uint32_t tag; /* Descriptor tag 1 */
1175 uint32_t length; /* set to size of payload struct. */
1176 struct fc_rdp_link_service_info payload;
1177 /* must be ELS req Word 0(0x18) */
1178};
1179
1180struct fc_rdp_sfp_info {
1181 uint16_t temperature;
1182 uint16_t vcc;
1183 uint16_t tx_bias;
1184 uint16_t tx_power;
1185 uint16_t rx_power;
1186 uint16_t flags;
1187};
1188
1189#define RDP_SFP_DESC_TAG 0x00010000
1190struct fc_rdp_sfp_desc {
1191 uint32_t tag;
1192 uint32_t length; /* set to size of sfp_info struct */
1193 struct fc_rdp_sfp_info sfp_info;
1194};
1195
1196/* Buffer Credit Descriptor */
1197struct fc_rdp_bbc_info {
1198 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */
1199 uint32_t attached_port_bbc;
1200 uint32_t rtt; /* Round trip time */
1201};
1202#define RDP_BBC_DESC_TAG 0x00010006
1203struct fc_rdp_bbc_desc {
1204 uint32_t tag;
1205 uint32_t length;
1206 struct fc_rdp_bbc_info bbc_info;
1207};
1208
1209/* Optical Element Type Transgression Flags */
1210#define RDP_OET_LOW_WARNING 0x1
1211#define RDP_OET_HIGH_WARNING 0x2
1212#define RDP_OET_LOW_ALARM 0x4
1213#define RDP_OET_HIGH_ALARM 0x8
1214
1215#define RDP_OED_TEMPERATURE 0x1
1216#define RDP_OED_VOLTAGE 0x2
1217#define RDP_OED_TXBIAS 0x3
1218#define RDP_OED_TXPOWER 0x4
1219#define RDP_OED_RXPOWER 0x5
1220
1221#define RDP_OED_TYPE_SHIFT 28
1222/* Optical Element Data descriptor */
1223struct fc_rdp_oed_info {
1224 uint16_t hi_alarm;
1225 uint16_t lo_alarm;
1226 uint16_t hi_warning;
1227 uint16_t lo_warning;
1228 uint32_t function_flags;
1229};
1230#define RDP_OED_DESC_TAG 0x00010007
1231struct fc_rdp_oed_sfp_desc {
1232 uint32_t tag;
1233 uint32_t length;
1234 struct fc_rdp_oed_info oed_info;
1235};
1236
1237/* Optical Product Data descriptor */
1238struct fc_rdp_opd_sfp_info {
1239 uint8_t vendor_name[16];
1240 uint8_t model_number[16];
1241 uint8_t serial_number[16];
1242 uint8_t revision[2];
1243 uint8_t reserved[2];
1244 uint8_t date[8];
1245};
1246
1247#define RDP_OPD_DESC_TAG 0x00010008
1248struct fc_rdp_opd_sfp_desc {
1249 uint32_t tag;
1250 uint32_t length;
1251 struct fc_rdp_opd_sfp_info opd_info;
1252};
1253
1254struct fc_rdp_req_frame {
1255 uint32_t rdp_command; /* ELS command opcode (0x18)*/
1256 uint32_t rdp_des_length; /* RDP Payload Word 1 */
1257 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1258};
1259
1260
1261struct fc_rdp_res_frame {
1262 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */
1263 uint32_t length; /* FC Word 1 */
1264 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */
1265 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */
1266 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10-12 */
1267 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13-21 */
1268 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22-27 */
1269 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28-33 */
1270 struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/
1271 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/
1272 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/
1273 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/
1274 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/
1275 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/
1276 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/
1277 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/
1278};
1279
1280
1281/******** FDMI ********/
1282
1283/* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1284#define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */
1285
1286/*
1287 * Registered Port List Format
1288 */
1289struct lpfc_fdmi_reg_port_list {
1290 uint32_t EntryCnt;
1291 uint32_t pe; /* Variable-length array */
1292};
1293
1294
1295/* Definitions for HBA / Port attribute entries */
1296
1297struct lpfc_fdmi_attr_def { /* Defined in TLV format */
1298 /* Structure is in Big Endian format */
1299 uint32_t AttrType:16;
1300 uint32_t AttrLen:16;
1301 uint32_t AttrValue; /* Marks start of Value (ATTRIBUTE_ENTRY) */
1302};
1303
1304
1305/* Attribute Entry */
1306struct lpfc_fdmi_attr_entry {
1307 union {
1308 uint32_t AttrInt;
1309 uint8_t AttrTypes[32];
1310 uint8_t AttrString[256];
1311 struct lpfc_name AttrWWN;
1312 } un;
1313};
1314
1315#define LPFC_FDMI_MAX_AE_SIZE sizeof(struct lpfc_fdmi_attr_entry)
1316
1317/*
1318 * HBA Attribute Block
1319 */
1320struct lpfc_fdmi_attr_block {
1321 uint32_t EntryCnt; /* Number of HBA attribute entries */
1322 struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */
1323};
1324
1325/*
1326 * Port Entry
1327 */
1328struct lpfc_fdmi_port_entry {
1329 struct lpfc_name PortName;
1330};
1331
1332/*
1333 * HBA Identifier
1334 */
1335struct lpfc_fdmi_hba_ident {
1336 struct lpfc_name PortName;
1337};
1338
1339/*
1340 * Register HBA(RHBA)
1341 */
1342struct lpfc_fdmi_reg_hba {
1343 struct lpfc_fdmi_hba_ident hi;
1344 struct lpfc_fdmi_reg_port_list rpl; /* variable-length array */
1345/* struct lpfc_fdmi_attr_block ab; */
1346};
1347
1348/*
1349 * Register HBA Attributes (RHAT)
1350 */
1351struct lpfc_fdmi_reg_hbaattr {
1352 struct lpfc_name HBA_PortName;
1353 struct lpfc_fdmi_attr_block ab;
1354};
1355
1356/*
1357 * Register Port Attributes (RPA)
1358 */
1359struct lpfc_fdmi_reg_portattr {
1360 struct lpfc_name PortName;
1361 struct lpfc_fdmi_attr_block ab;
1362};
1363
1364/*
1365 * HBA MAnagement Operations Command Codes
1366 */
1367#define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1368#define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1369#define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1370#define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1371#define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */
1372#define SLI_MGMT_RHBA 0x200 /* Register HBA */
1373#define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
1374#define SLI_MGMT_RPRT 0x210 /* Register Port */
1375#define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1376#define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1377#define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */
1378#define SLI_MGMT_DPRT 0x310 /* De-register Port */
1379#define SLI_MGMT_DPA 0x311 /* De-register Port attributes */
1380
1381#define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */
1382
1383/*
1384 * HBA Attribute Types
1385 */
1386#define RHBA_NODENAME 0x1 /* 8 byte WWNN */
1387#define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */
1388#define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */
1389#define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */
1390#define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */
1391#define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */
1392#define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */
1393#define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1394#define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */
1395#define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */
1396#define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1397#define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */
1398#define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */
1399#define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */
1400#define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */
1401#define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */
1402#define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */
1403#define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */
1404
1405/* Bit mask for all individual HBA attributes */
1406#define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001
1407#define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002
1408#define LPFC_FDMI_HBA_ATTR_sn 0x00000004
1409#define LPFC_FDMI_HBA_ATTR_model 0x00000008
1410#define LPFC_FDMI_HBA_ATTR_description 0x00000010
1411#define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020
1412#define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040
1413#define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080
1414#define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100
1415#define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200
1416#define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400
1417#define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800
1418#define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */
1419#define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000
1420#define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000
1421#define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000
1422#define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */
1423#define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000
1424
1425/* Bit mask for FDMI-1 defined HBA attributes */
1426#define LPFC_FDMI1_HBA_ATTR 0x000007ff
1427
1428/* Bit mask for FDMI-2 defined HBA attributes */
1429/* Skip vendor_info and bios_state */
1430#define LPFC_FDMI2_HBA_ATTR 0x0002efff
1431
1432/*
1433 * Port Attrubute Types
1434 */
1435#define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */
1436#define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */
1437#define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */
1438#define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */
1439#define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */
1440#define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */
1441#define RPRT_NODENAME 0x7 /* 8 byte WWNN */
1442#define RPRT_PORTNAME 0x8 /* 8 byte WWPN */
1443#define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */
1444#define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */
1445#define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */
1446#define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */
1447#define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */
1448#define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */
1449#define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */
1450#define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */
1451#define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */
1452#define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */
1453#define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */
1454#define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */
1455#define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */
1456#define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */
1457#define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */
1458
1459/* Bit mask for all individual PORT attributes */
1460#define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001
1461#define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002
1462#define LPFC_FDMI_PORT_ATTR_speed 0x00000004
1463#define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008
1464#define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010
1465#define LPFC_FDMI_PORT_ATTR_host_name 0x00000020
1466#define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040
1467#define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080
1468#define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100
1469#define LPFC_FDMI_PORT_ATTR_port_type 0x00000200
1470#define LPFC_FDMI_PORT_ATTR_class 0x00000400
1471#define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800
1472#define LPFC_FDMI_PORT_ATTR_port_state 0x00001000
1473#define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000
1474#define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000
1475#define LPFC_FDMI_PORT_ATTR_nportid 0x00008000
1476#define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */
1477#define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */
1478#define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */
1479#define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */
1480#define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */
1481#define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */
1482#define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */
1483
1484/* Bit mask for FDMI-1 defined PORT attributes */
1485#define LPFC_FDMI1_PORT_ATTR 0x0000003f
1486
1487/* Bit mask for FDMI-2 defined PORT attributes */
1488#define LPFC_FDMI2_PORT_ATTR 0x0000ffff
1489
1490/* Bit mask for Smart SAN defined PORT attributes */
1491#define LPFC_FDMI2_SMART_ATTR 0x007fffff
1492
1493/* Defines for PORT port state attribute */
1494#define LPFC_FDMI_PORTSTATE_UNKNOWN 1
1495#define LPFC_FDMI_PORTSTATE_ONLINE 2
1496
1497/* Defines for PORT port type attribute */
1498#define LPFC_FDMI_PORTTYPE_UNKNOWN 0
1499#define LPFC_FDMI_PORTTYPE_NPORT 1
1500#define LPFC_FDMI_PORTTYPE_NLPORT 2
1501
1502/*
1503 * Begin HBA configuration parameters.
1504 * The PCI configuration register BAR assignments are:
1505 * BAR0, offset 0x10 - SLIM base memory address
1506 * BAR1, offset 0x14 - SLIM base memory high address
1507 * BAR2, offset 0x18 - REGISTER base memory address
1508 * BAR3, offset 0x1c - REGISTER base memory high address
1509 * BAR4, offset 0x20 - BIU I/O registers
1510 * BAR5, offset 0x24 - REGISTER base io high address
1511 */
1512
1513/* Number of rings currently used and available. */
1514#define MAX_SLI3_CONFIGURED_RINGS 3
1515#define MAX_SLI3_RINGS 4
1516
1517/* IOCB / Mailbox is owned by FireFly */
1518#define OWN_CHIP 1
1519
1520/* IOCB / Mailbox is owned by Host */
1521#define OWN_HOST 0
1522
1523/* Number of 4-byte words in an IOCB. */
1524#define IOCB_WORD_SZ 8
1525
1526/* network headers for Dfctl field */
1527#define FC_NET_HDR 0x20
1528
1529/* Start FireFly Register definitions */
1530#define PCI_VENDOR_ID_EMULEX 0x10df
1531#define PCI_DEVICE_ID_FIREFLY 0x1ae5
1532#define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1533#define PCI_DEVICE_ID_BALIUS 0xe131
1534#define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1535#define PCI_DEVICE_ID_LANCER_FC 0xe200
1536#define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1537#define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1538#define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1539#define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
1540#define PCI_DEVICE_ID_SAT_SMB 0xf011
1541#define PCI_DEVICE_ID_SAT_MID 0xf015
1542#define PCI_DEVICE_ID_RFLY 0xf095
1543#define PCI_DEVICE_ID_PFLY 0xf098
1544#define PCI_DEVICE_ID_LP101 0xf0a1
1545#define PCI_DEVICE_ID_TFLY 0xf0a5
1546#define PCI_DEVICE_ID_BSMB 0xf0d1
1547#define PCI_DEVICE_ID_BMID 0xf0d5
1548#define PCI_DEVICE_ID_ZSMB 0xf0e1
1549#define PCI_DEVICE_ID_ZMID 0xf0e5
1550#define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1551#define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1552#define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1553#define PCI_DEVICE_ID_SAT 0xf100
1554#define PCI_DEVICE_ID_SAT_SCSP 0xf111
1555#define PCI_DEVICE_ID_SAT_DCSP 0xf112
1556#define PCI_DEVICE_ID_FALCON 0xf180
1557#define PCI_DEVICE_ID_SUPERFLY 0xf700
1558#define PCI_DEVICE_ID_DRAGONFLY 0xf800
1559#define PCI_DEVICE_ID_CENTAUR 0xf900
1560#define PCI_DEVICE_ID_PEGASUS 0xf980
1561#define PCI_DEVICE_ID_THOR 0xfa00
1562#define PCI_DEVICE_ID_VIPER 0xfb00
1563#define PCI_DEVICE_ID_LP10000S 0xfc00
1564#define PCI_DEVICE_ID_LP11000S 0xfc10
1565#define PCI_DEVICE_ID_LPE11000S 0xfc20
1566#define PCI_DEVICE_ID_SAT_S 0xfc40
1567#define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1568#define PCI_DEVICE_ID_HELIOS 0xfd00
1569#define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1570#define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1571#define PCI_DEVICE_ID_ZEPHYR 0xfe00
1572#define PCI_DEVICE_ID_HORNET 0xfe05
1573#define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1574#define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1575#define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1576#define PCI_DEVICE_ID_TIGERSHARK 0x0704
1577#define PCI_DEVICE_ID_TOMCAT 0x0714
1578#define PCI_DEVICE_ID_SKYHAWK 0x0724
1579#define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
1580
1581#define JEDEC_ID_ADDRESS 0x0080001c
1582#define FIREFLY_JEDEC_ID 0x1ACC
1583#define SUPERFLY_JEDEC_ID 0x0020
1584#define DRAGONFLY_JEDEC_ID 0x0021
1585#define DRAGONFLY_V2_JEDEC_ID 0x0025
1586#define CENTAUR_2G_JEDEC_ID 0x0026
1587#define CENTAUR_1G_JEDEC_ID 0x0028
1588#define PEGASUS_ORION_JEDEC_ID 0x0036
1589#define PEGASUS_JEDEC_ID 0x0038
1590#define THOR_JEDEC_ID 0x0012
1591#define HELIOS_JEDEC_ID 0x0364
1592#define ZEPHYR_JEDEC_ID 0x0577
1593#define VIPER_JEDEC_ID 0x4838
1594#define SATURN_JEDEC_ID 0x1004
1595#define HORNET_JDEC_ID 0x2057706D
1596
1597#define JEDEC_ID_MASK 0x0FFFF000
1598#define JEDEC_ID_SHIFT 12
1599#define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1600
1601typedef struct { /* FireFly BIU registers */
1602 uint32_t hostAtt; /* See definitions for Host Attention
1603 register */
1604 uint32_t chipAtt; /* See definitions for Chip Attention
1605 register */
1606 uint32_t hostStatus; /* See definitions for Host Status register */
1607 uint32_t hostControl; /* See definitions for Host Control register */
1608 uint32_t buiConfig; /* See definitions for BIU configuration
1609 register */
1610} FF_REGS;
1611
1612/* IO Register size in bytes */
1613#define FF_REG_AREA_SIZE 256
1614
1615/* Host Attention Register */
1616
1617#define HA_REG_OFFSET 0 /* Byte offset from register base address */
1618
1619#define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1620#define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1621#define HA_R0ATT 0x00000008 /* Bit 3 */
1622#define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1623#define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1624#define HA_R1ATT 0x00000080 /* Bit 7 */
1625#define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1626#define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1627#define HA_R2ATT 0x00000800 /* Bit 11 */
1628#define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1629#define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1630#define HA_R3ATT 0x00008000 /* Bit 15 */
1631#define HA_LATT 0x20000000 /* Bit 29 */
1632#define HA_MBATT 0x40000000 /* Bit 30 */
1633#define HA_ERATT 0x80000000 /* Bit 31 */
1634
1635#define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1636#define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1637#define HA_RXATT 0x00000008 /* Bit 3 */
1638#define HA_RXMASK 0x0000000f
1639
1640#define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1641#define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1642#define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1643#define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1644
1645#define HA_R0_POS 3
1646#define HA_R1_POS 7
1647#define HA_R2_POS 11
1648#define HA_R3_POS 15
1649#define HA_LE_POS 29
1650#define HA_MB_POS 30
1651#define HA_ER_POS 31
1652/* Chip Attention Register */
1653
1654#define CA_REG_OFFSET 4 /* Byte offset from register base address */
1655
1656#define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1657#define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1658#define CA_R0ATT 0x00000008 /* Bit 3 */
1659#define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1660#define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1661#define CA_R1ATT 0x00000080 /* Bit 7 */
1662#define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1663#define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1664#define CA_R2ATT 0x00000800 /* Bit 11 */
1665#define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1666#define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1667#define CA_R3ATT 0x00008000 /* Bit 15 */
1668#define CA_MBATT 0x40000000 /* Bit 30 */
1669
1670/* Host Status Register */
1671
1672#define HS_REG_OFFSET 8 /* Byte offset from register base address */
1673
1674#define HS_MBRDY 0x00400000 /* Bit 22 */
1675#define HS_FFRDY 0x00800000 /* Bit 23 */
1676#define HS_FFER8 0x01000000 /* Bit 24 */
1677#define HS_FFER7 0x02000000 /* Bit 25 */
1678#define HS_FFER6 0x04000000 /* Bit 26 */
1679#define HS_FFER5 0x08000000 /* Bit 27 */
1680#define HS_FFER4 0x10000000 /* Bit 28 */
1681#define HS_FFER3 0x20000000 /* Bit 29 */
1682#define HS_FFER2 0x40000000 /* Bit 30 */
1683#define HS_FFER1 0x80000000 /* Bit 31 */
1684#define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1685#define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1686#define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
1687/* Host Control Register */
1688
1689#define HC_REG_OFFSET 12 /* Byte offset from register base address */
1690
1691#define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1692#define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1693#define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1694#define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1695#define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1696#define HC_INITHBI 0x02000000 /* Bit 25 */
1697#define HC_INITMB 0x04000000 /* Bit 26 */
1698#define HC_INITFF 0x08000000 /* Bit 27 */
1699#define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1700#define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1701
1702/* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1703#define MSIX_DFLT_ID 0
1704#define MSIX_RNG0_ID 0
1705#define MSIX_RNG1_ID 1
1706#define MSIX_RNG2_ID 2
1707#define MSIX_RNG3_ID 3
1708
1709#define MSIX_LINK_ID 4
1710#define MSIX_MBOX_ID 5
1711
1712#define MSIX_SPARE0_ID 6
1713#define MSIX_SPARE1_ID 7
1714
1715/* Mailbox Commands */
1716#define MBX_SHUTDOWN 0x00 /* terminate testing */
1717#define MBX_LOAD_SM 0x01
1718#define MBX_READ_NV 0x02
1719#define MBX_WRITE_NV 0x03
1720#define MBX_RUN_BIU_DIAG 0x04
1721#define MBX_INIT_LINK 0x05
1722#define MBX_DOWN_LINK 0x06
1723#define MBX_CONFIG_LINK 0x07
1724#define MBX_CONFIG_RING 0x09
1725#define MBX_RESET_RING 0x0A
1726#define MBX_READ_CONFIG 0x0B
1727#define MBX_READ_RCONFIG 0x0C
1728#define MBX_READ_SPARM 0x0D
1729#define MBX_READ_STATUS 0x0E
1730#define MBX_READ_RPI 0x0F
1731#define MBX_READ_XRI 0x10
1732#define MBX_READ_REV 0x11
1733#define MBX_READ_LNK_STAT 0x12
1734#define MBX_REG_LOGIN 0x13
1735#define MBX_UNREG_LOGIN 0x14
1736#define MBX_CLEAR_LA 0x16
1737#define MBX_DUMP_MEMORY 0x17
1738#define MBX_DUMP_CONTEXT 0x18
1739#define MBX_RUN_DIAGS 0x19
1740#define MBX_RESTART 0x1A
1741#define MBX_UPDATE_CFG 0x1B
1742#define MBX_DOWN_LOAD 0x1C
1743#define MBX_DEL_LD_ENTRY 0x1D
1744#define MBX_RUN_PROGRAM 0x1E
1745#define MBX_SET_MASK 0x20
1746#define MBX_SET_VARIABLE 0x21
1747#define MBX_UNREG_D_ID 0x23
1748#define MBX_KILL_BOARD 0x24
1749#define MBX_CONFIG_FARP 0x25
1750#define MBX_BEACON 0x2A
1751#define MBX_CONFIG_MSI 0x30
1752#define MBX_HEARTBEAT 0x31
1753#define MBX_WRITE_VPARMS 0x32
1754#define MBX_ASYNCEVT_ENABLE 0x33
1755#define MBX_READ_EVENT_LOG_STATUS 0x37
1756#define MBX_READ_EVENT_LOG 0x38
1757#define MBX_WRITE_EVENT_LOG 0x39
1758
1759#define MBX_PORT_CAPABILITIES 0x3B
1760#define MBX_PORT_IOV_CONTROL 0x3C
1761
1762#define MBX_CONFIG_HBQ 0x7C
1763#define MBX_LOAD_AREA 0x81
1764#define MBX_RUN_BIU_DIAG64 0x84
1765#define MBX_CONFIG_PORT 0x88
1766#define MBX_READ_SPARM64 0x8D
1767#define MBX_READ_RPI64 0x8F
1768#define MBX_REG_LOGIN64 0x93
1769#define MBX_READ_TOPOLOGY 0x95
1770#define MBX_REG_VPI 0x96
1771#define MBX_UNREG_VPI 0x97
1772
1773#define MBX_WRITE_WWN 0x98
1774#define MBX_SET_DEBUG 0x99
1775#define MBX_LOAD_EXP_ROM 0x9C
1776#define MBX_SLI4_CONFIG 0x9B
1777#define MBX_SLI4_REQ_FTRS 0x9D
1778#define MBX_MAX_CMDS 0x9E
1779#define MBX_RESUME_RPI 0x9E
1780#define MBX_SLI2_CMD_MASK 0x80
1781#define MBX_REG_VFI 0x9F
1782#define MBX_REG_FCFI 0xA0
1783#define MBX_UNREG_VFI 0xA1
1784#define MBX_UNREG_FCFI 0xA2
1785#define MBX_INIT_VFI 0xA3
1786#define MBX_INIT_VPI 0xA4
1787#define MBX_ACCESS_VDATA 0xA5
1788
1789#define MBX_AUTH_PORT 0xF8
1790#define MBX_SECURITY_MGMT 0xF9
1791
1792/* IOCB Commands */
1793
1794#define CMD_RCV_SEQUENCE_CX 0x01
1795#define CMD_XMIT_SEQUENCE_CR 0x02
1796#define CMD_XMIT_SEQUENCE_CX 0x03
1797#define CMD_XMIT_BCAST_CN 0x04
1798#define CMD_XMIT_BCAST_CX 0x05
1799#define CMD_QUE_RING_BUF_CN 0x06
1800#define CMD_QUE_XRI_BUF_CX 0x07
1801#define CMD_IOCB_CONTINUE_CN 0x08
1802#define CMD_RET_XRI_BUF_CX 0x09
1803#define CMD_ELS_REQUEST_CR 0x0A
1804#define CMD_ELS_REQUEST_CX 0x0B
1805#define CMD_RCV_ELS_REQ_CX 0x0D
1806#define CMD_ABORT_XRI_CN 0x0E
1807#define CMD_ABORT_XRI_CX 0x0F
1808#define CMD_CLOSE_XRI_CN 0x10
1809#define CMD_CLOSE_XRI_CX 0x11
1810#define CMD_CREATE_XRI_CR 0x12
1811#define CMD_CREATE_XRI_CX 0x13
1812#define CMD_GET_RPI_CN 0x14
1813#define CMD_XMIT_ELS_RSP_CX 0x15
1814#define CMD_GET_RPI_CR 0x16
1815#define CMD_XRI_ABORTED_CX 0x17
1816#define CMD_FCP_IWRITE_CR 0x18
1817#define CMD_FCP_IWRITE_CX 0x19
1818#define CMD_FCP_IREAD_CR 0x1A
1819#define CMD_FCP_IREAD_CX 0x1B
1820#define CMD_FCP_ICMND_CR 0x1C
1821#define CMD_FCP_ICMND_CX 0x1D
1822#define CMD_FCP_TSEND_CX 0x1F
1823#define CMD_FCP_TRECEIVE_CX 0x21
1824#define CMD_FCP_TRSP_CX 0x23
1825#define CMD_FCP_AUTO_TRSP_CX 0x29
1826
1827#define CMD_ADAPTER_MSG 0x20
1828#define CMD_ADAPTER_DUMP 0x22
1829
1830/* SLI_2 IOCB Command Set */
1831
1832#define CMD_ASYNC_STATUS 0x7C
1833#define CMD_RCV_SEQUENCE64_CX 0x81
1834#define CMD_XMIT_SEQUENCE64_CR 0x82
1835#define CMD_XMIT_SEQUENCE64_CX 0x83
1836#define CMD_XMIT_BCAST64_CN 0x84
1837#define CMD_XMIT_BCAST64_CX 0x85
1838#define CMD_QUE_RING_BUF64_CN 0x86
1839#define CMD_QUE_XRI_BUF64_CX 0x87
1840#define CMD_IOCB_CONTINUE64_CN 0x88
1841#define CMD_RET_XRI_BUF64_CX 0x89
1842#define CMD_ELS_REQUEST64_CR 0x8A
1843#define CMD_ELS_REQUEST64_CX 0x8B
1844#define CMD_ABORT_MXRI64_CN 0x8C
1845#define CMD_RCV_ELS_REQ64_CX 0x8D
1846#define CMD_XMIT_ELS_RSP64_CX 0x95
1847#define CMD_XMIT_BLS_RSP64_CX 0x97
1848#define CMD_FCP_IWRITE64_CR 0x98
1849#define CMD_FCP_IWRITE64_CX 0x99
1850#define CMD_FCP_IREAD64_CR 0x9A
1851#define CMD_FCP_IREAD64_CX 0x9B
1852#define CMD_FCP_ICMND64_CR 0x9C
1853#define CMD_FCP_ICMND64_CX 0x9D
1854#define CMD_FCP_TSEND64_CX 0x9F
1855#define CMD_FCP_TRECEIVE64_CX 0xA1
1856#define CMD_FCP_TRSP64_CX 0xA3
1857
1858#define CMD_QUE_XRI64_CX 0xB3
1859#define CMD_IOCB_RCV_SEQ64_CX 0xB5
1860#define CMD_IOCB_RCV_ELS64_CX 0xB7
1861#define CMD_IOCB_RET_XRI64_CX 0xB9
1862#define CMD_IOCB_RCV_CONT64_CX 0xBB
1863
1864#define CMD_GEN_REQUEST64_CR 0xC2
1865#define CMD_GEN_REQUEST64_CX 0xC3
1866
1867/* Unhandled SLI-3 Commands */
1868#define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1869#define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1870#define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1871#define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1872#define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1873#define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1874#define CMD_IOCB_RET_HBQE64_CN 0xCA
1875#define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1876#define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1877#define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1878#define CMD_IOCB_LOGENTRY_CN 0x94
1879#define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1880
1881/* Data Security SLI Commands */
1882#define DSSCMD_IWRITE64_CR 0xF8
1883#define DSSCMD_IWRITE64_CX 0xF9
1884#define DSSCMD_IREAD64_CR 0xFA
1885#define DSSCMD_IREAD64_CX 0xFB
1886
1887#define CMD_MAX_IOCB_CMD 0xFB
1888#define CMD_IOCB_MASK 0xff
1889
1890#define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1891 iocb */
1892#define LPFC_MAX_ADPTMSG 32 /* max msg data */
1893/*
1894 * Define Status
1895 */
1896#define MBX_SUCCESS 0
1897#define MBXERR_NUM_RINGS 1
1898#define MBXERR_NUM_IOCBS 2
1899#define MBXERR_IOCBS_EXCEEDED 3
1900#define MBXERR_BAD_RING_NUMBER 4
1901#define MBXERR_MASK_ENTRIES_RANGE 5
1902#define MBXERR_MASKS_EXCEEDED 6
1903#define MBXERR_BAD_PROFILE 7
1904#define MBXERR_BAD_DEF_CLASS 8
1905#define MBXERR_BAD_MAX_RESPONDER 9
1906#define MBXERR_BAD_MAX_ORIGINATOR 10
1907#define MBXERR_RPI_REGISTERED 11
1908#define MBXERR_RPI_FULL 12
1909#define MBXERR_NO_RESOURCES 13
1910#define MBXERR_BAD_RCV_LENGTH 14
1911#define MBXERR_DMA_ERROR 15
1912#define MBXERR_ERROR 16
1913#define MBXERR_LINK_DOWN 0x33
1914#define MBXERR_SEC_NO_PERMISSION 0xF02
1915#define MBX_NOT_FINISHED 255
1916
1917#define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1918#define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1919
1920#define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1921
1922/*
1923 * return code Fail
1924 */
1925#define FAILURE 1
1926
1927/*
1928 * Begin Structure Definitions for Mailbox Commands
1929 */
1930
1931typedef struct {
1932#ifdef __BIG_ENDIAN_BITFIELD
1933 uint8_t tval;
1934 uint8_t tmask;
1935 uint8_t rval;
1936 uint8_t rmask;
1937#else /* __LITTLE_ENDIAN_BITFIELD */
1938 uint8_t rmask;
1939 uint8_t rval;
1940 uint8_t tmask;
1941 uint8_t tval;
1942#endif
1943} RR_REG;
1944
1945struct ulp_bde {
1946 uint32_t bdeAddress;
1947#ifdef __BIG_ENDIAN_BITFIELD
1948 uint32_t bdeReserved:4;
1949 uint32_t bdeAddrHigh:4;
1950 uint32_t bdeSize:24;
1951#else /* __LITTLE_ENDIAN_BITFIELD */
1952 uint32_t bdeSize:24;
1953 uint32_t bdeAddrHigh:4;
1954 uint32_t bdeReserved:4;
1955#endif
1956};
1957
1958typedef struct ULP_BDL { /* SLI-2 */
1959#ifdef __BIG_ENDIAN_BITFIELD
1960 uint32_t bdeFlags:8; /* BDL Flags */
1961 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1962#else /* __LITTLE_ENDIAN_BITFIELD */
1963 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1964 uint32_t bdeFlags:8; /* BDL Flags */
1965#endif
1966
1967 uint32_t addrLow; /* Address 0:31 */
1968 uint32_t addrHigh; /* Address 32:63 */
1969 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1970} ULP_BDL;
1971
1972/*
1973 * BlockGuard Definitions
1974 */
1975
1976enum lpfc_protgrp_type {
1977 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
1978 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
1979 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
1980 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
1981};
1982
1983/* PDE Descriptors */
1984#define LPFC_PDE5_DESCRIPTOR 0x85
1985#define LPFC_PDE6_DESCRIPTOR 0x86
1986#define LPFC_PDE7_DESCRIPTOR 0x87
1987
1988/* BlockGuard Opcodes */
1989#define BG_OP_IN_NODIF_OUT_CRC 0x0
1990#define BG_OP_IN_CRC_OUT_NODIF 0x1
1991#define BG_OP_IN_NODIF_OUT_CSUM 0x2
1992#define BG_OP_IN_CSUM_OUT_NODIF 0x3
1993#define BG_OP_IN_CRC_OUT_CRC 0x4
1994#define BG_OP_IN_CSUM_OUT_CSUM 0x5
1995#define BG_OP_IN_CRC_OUT_CSUM 0x6
1996#define BG_OP_IN_CSUM_OUT_CRC 0x7
1997#define BG_OP_RAW_MODE 0x8
1998
1999struct lpfc_pde5 {
2000 uint32_t word0;
2001#define pde5_type_SHIFT 24
2002#define pde5_type_MASK 0x000000ff
2003#define pde5_type_WORD word0
2004#define pde5_rsvd0_SHIFT 0
2005#define pde5_rsvd0_MASK 0x00ffffff
2006#define pde5_rsvd0_WORD word0
2007 uint32_t reftag; /* Reference Tag Value */
2008 uint32_t reftagtr; /* Reference Tag Translation Value */
2009};
2010
2011struct lpfc_pde6 {
2012 uint32_t word0;
2013#define pde6_type_SHIFT 24
2014#define pde6_type_MASK 0x000000ff
2015#define pde6_type_WORD word0
2016#define pde6_rsvd0_SHIFT 0
2017#define pde6_rsvd0_MASK 0x00ffffff
2018#define pde6_rsvd0_WORD word0
2019 uint32_t word1;
2020#define pde6_rsvd1_SHIFT 26
2021#define pde6_rsvd1_MASK 0x0000003f
2022#define pde6_rsvd1_WORD word1
2023#define pde6_na_SHIFT 25
2024#define pde6_na_MASK 0x00000001
2025#define pde6_na_WORD word1
2026#define pde6_rsvd2_SHIFT 16
2027#define pde6_rsvd2_MASK 0x000001FF
2028#define pde6_rsvd2_WORD word1
2029#define pde6_apptagtr_SHIFT 0
2030#define pde6_apptagtr_MASK 0x0000ffff
2031#define pde6_apptagtr_WORD word1
2032 uint32_t word2;
2033#define pde6_optx_SHIFT 28
2034#define pde6_optx_MASK 0x0000000f
2035#define pde6_optx_WORD word2
2036#define pde6_oprx_SHIFT 24
2037#define pde6_oprx_MASK 0x0000000f
2038#define pde6_oprx_WORD word2
2039#define pde6_nr_SHIFT 23
2040#define pde6_nr_MASK 0x00000001
2041#define pde6_nr_WORD word2
2042#define pde6_ce_SHIFT 22
2043#define pde6_ce_MASK 0x00000001
2044#define pde6_ce_WORD word2
2045#define pde6_re_SHIFT 21
2046#define pde6_re_MASK 0x00000001
2047#define pde6_re_WORD word2
2048#define pde6_ae_SHIFT 20
2049#define pde6_ae_MASK 0x00000001
2050#define pde6_ae_WORD word2
2051#define pde6_ai_SHIFT 19
2052#define pde6_ai_MASK 0x00000001
2053#define pde6_ai_WORD word2
2054#define pde6_bs_SHIFT 16
2055#define pde6_bs_MASK 0x00000007
2056#define pde6_bs_WORD word2
2057#define pde6_apptagval_SHIFT 0
2058#define pde6_apptagval_MASK 0x0000ffff
2059#define pde6_apptagval_WORD word2
2060};
2061
2062struct lpfc_pde7 {
2063 uint32_t word0;
2064#define pde7_type_SHIFT 24
2065#define pde7_type_MASK 0x000000ff
2066#define pde7_type_WORD word0
2067#define pde7_rsvd0_SHIFT 0
2068#define pde7_rsvd0_MASK 0x00ffffff
2069#define pde7_rsvd0_WORD word0
2070 uint32_t addrHigh;
2071 uint32_t addrLow;
2072};
2073
2074/* Structure for MB Command LOAD_SM and DOWN_LOAD */
2075
2076typedef struct {
2077#ifdef __BIG_ENDIAN_BITFIELD
2078 uint32_t rsvd2:25;
2079 uint32_t acknowledgment:1;
2080 uint32_t version:1;
2081 uint32_t erase_or_prog:1;
2082 uint32_t update_flash:1;
2083 uint32_t update_ram:1;
2084 uint32_t method:1;
2085 uint32_t load_cmplt:1;
2086#else /* __LITTLE_ENDIAN_BITFIELD */
2087 uint32_t load_cmplt:1;
2088 uint32_t method:1;
2089 uint32_t update_ram:1;
2090 uint32_t update_flash:1;
2091 uint32_t erase_or_prog:1;
2092 uint32_t version:1;
2093 uint32_t acknowledgment:1;
2094 uint32_t rsvd2:25;
2095#endif
2096
2097 uint32_t dl_to_adr_low;
2098 uint32_t dl_to_adr_high;
2099 uint32_t dl_len;
2100 union {
2101 uint32_t dl_from_mbx_offset;
2102 struct ulp_bde dl_from_bde;
2103 struct ulp_bde64 dl_from_bde64;
2104 } un;
2105
2106} LOAD_SM_VAR;
2107
2108/* Structure for MB Command READ_NVPARM (02) */
2109
2110typedef struct {
2111 uint32_t rsvd1[3]; /* Read as all one's */
2112 uint32_t rsvd2; /* Read as all zero's */
2113 uint32_t portname[2]; /* N_PORT name */
2114 uint32_t nodename[2]; /* NODE name */
2115
2116#ifdef __BIG_ENDIAN_BITFIELD
2117 uint32_t pref_DID:24;
2118 uint32_t hardAL_PA:8;
2119#else /* __LITTLE_ENDIAN_BITFIELD */
2120 uint32_t hardAL_PA:8;
2121 uint32_t pref_DID:24;
2122#endif
2123
2124 uint32_t rsvd3[21]; /* Read as all one's */
2125} READ_NV_VAR;
2126
2127/* Structure for MB Command WRITE_NVPARMS (03) */
2128
2129typedef struct {
2130 uint32_t rsvd1[3]; /* Must be all one's */
2131 uint32_t rsvd2; /* Must be all zero's */
2132 uint32_t portname[2]; /* N_PORT name */
2133 uint32_t nodename[2]; /* NODE name */
2134
2135#ifdef __BIG_ENDIAN_BITFIELD
2136 uint32_t pref_DID:24;
2137 uint32_t hardAL_PA:8;
2138#else /* __LITTLE_ENDIAN_BITFIELD */
2139 uint32_t hardAL_PA:8;
2140 uint32_t pref_DID:24;
2141#endif
2142
2143 uint32_t rsvd3[21]; /* Must be all one's */
2144} WRITE_NV_VAR;
2145
2146/* Structure for MB Command RUN_BIU_DIAG (04) */
2147/* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2148
2149typedef struct {
2150 uint32_t rsvd1;
2151 union {
2152 struct {
2153 struct ulp_bde xmit_bde;
2154 struct ulp_bde rcv_bde;
2155 } s1;
2156 struct {
2157 struct ulp_bde64 xmit_bde64;
2158 struct ulp_bde64 rcv_bde64;
2159 } s2;
2160 } un;
2161} BIU_DIAG_VAR;
2162
2163/* Structure for MB command READ_EVENT_LOG (0x38) */
2164struct READ_EVENT_LOG_VAR {
2165 uint32_t word1;
2166#define lpfc_event_log_SHIFT 29
2167#define lpfc_event_log_MASK 0x00000001
2168#define lpfc_event_log_WORD word1
2169#define USE_MAILBOX_RESPONSE 1
2170 uint32_t offset;
2171 struct ulp_bde64 rcv_bde64;
2172};
2173
2174/* Structure for MB Command INIT_LINK (05) */
2175
2176typedef struct {
2177#ifdef __BIG_ENDIAN_BITFIELD
2178 uint32_t rsvd1:24;
2179 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2180#else /* __LITTLE_ENDIAN_BITFIELD */
2181 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2182 uint32_t rsvd1:24;
2183#endif
2184
2185#ifdef __BIG_ENDIAN_BITFIELD
2186 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2187 uint8_t rsvd2;
2188 uint16_t link_flags;
2189#else /* __LITTLE_ENDIAN_BITFIELD */
2190 uint16_t link_flags;
2191 uint8_t rsvd2;
2192 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2193#endif
2194
2195#define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
2196#define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
2197#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
2198#define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
2199#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
2200#define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
2201#define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
2202
2203#define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
2204#define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
2205#define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
2206
2207 uint32_t link_speed;
2208#define LINK_SPEED_AUTO 0x0 /* Auto selection */
2209#define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
2210#define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
2211#define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
2212#define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
2213#define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
2214#define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
2215#define LINK_SPEED_32G 0x14 /* 32 Gigabaud */
2216
2217} INIT_LINK_VAR;
2218
2219/* Structure for MB Command DOWN_LINK (06) */
2220
2221typedef struct {
2222 uint32_t rsvd1;
2223} DOWN_LINK_VAR;
2224
2225/* Structure for MB Command CONFIG_LINK (07) */
2226
2227typedef struct {
2228#ifdef __BIG_ENDIAN_BITFIELD
2229 uint32_t cr:1;
2230 uint32_t ci:1;
2231 uint32_t cr_delay:6;
2232 uint32_t cr_count:8;
2233 uint32_t rsvd1:8;
2234 uint32_t MaxBBC:8;
2235#else /* __LITTLE_ENDIAN_BITFIELD */
2236 uint32_t MaxBBC:8;
2237 uint32_t rsvd1:8;
2238 uint32_t cr_count:8;
2239 uint32_t cr_delay:6;
2240 uint32_t ci:1;
2241 uint32_t cr:1;
2242#endif
2243
2244 uint32_t myId;
2245 uint32_t rsvd2;
2246 uint32_t edtov;
2247 uint32_t arbtov;
2248 uint32_t ratov;
2249 uint32_t rttov;
2250 uint32_t altov;
2251 uint32_t crtov;
2252 uint32_t citov;
2253#ifdef __BIG_ENDIAN_BITFIELD
2254 uint32_t rrq_enable:1;
2255 uint32_t rrq_immed:1;
2256 uint32_t rsvd4:29;
2257 uint32_t ack0_enable:1;
2258#else /* __LITTLE_ENDIAN_BITFIELD */
2259 uint32_t ack0_enable:1;
2260 uint32_t rsvd4:29;
2261 uint32_t rrq_immed:1;
2262 uint32_t rrq_enable:1;
2263#endif
2264} CONFIG_LINK;
2265
2266/* Structure for MB Command PART_SLIM (08)
2267 * will be removed since SLI1 is no longer supported!
2268 */
2269typedef struct {
2270#ifdef __BIG_ENDIAN_BITFIELD
2271 uint16_t offCiocb;
2272 uint16_t numCiocb;
2273 uint16_t offRiocb;
2274 uint16_t numRiocb;
2275#else /* __LITTLE_ENDIAN_BITFIELD */
2276 uint16_t numCiocb;
2277 uint16_t offCiocb;
2278 uint16_t numRiocb;
2279 uint16_t offRiocb;
2280#endif
2281} RING_DEF;
2282
2283typedef struct {
2284#ifdef __BIG_ENDIAN_BITFIELD
2285 uint32_t unused1:24;
2286 uint32_t numRing:8;
2287#else /* __LITTLE_ENDIAN_BITFIELD */
2288 uint32_t numRing:8;
2289 uint32_t unused1:24;
2290#endif
2291
2292 RING_DEF ringdef[4];
2293 uint32_t hbainit;
2294} PART_SLIM_VAR;
2295
2296/* Structure for MB Command CONFIG_RING (09) */
2297
2298typedef struct {
2299#ifdef __BIG_ENDIAN_BITFIELD
2300 uint32_t unused2:6;
2301 uint32_t recvSeq:1;
2302 uint32_t recvNotify:1;
2303 uint32_t numMask:8;
2304 uint32_t profile:8;
2305 uint32_t unused1:4;
2306 uint32_t ring:4;
2307#else /* __LITTLE_ENDIAN_BITFIELD */
2308 uint32_t ring:4;
2309 uint32_t unused1:4;
2310 uint32_t profile:8;
2311 uint32_t numMask:8;
2312 uint32_t recvNotify:1;
2313 uint32_t recvSeq:1;
2314 uint32_t unused2:6;
2315#endif
2316
2317#ifdef __BIG_ENDIAN_BITFIELD
2318 uint16_t maxRespXchg;
2319 uint16_t maxOrigXchg;
2320#else /* __LITTLE_ENDIAN_BITFIELD */
2321 uint16_t maxOrigXchg;
2322 uint16_t maxRespXchg;
2323#endif
2324
2325 RR_REG rrRegs[6];
2326} CONFIG_RING_VAR;
2327
2328/* Structure for MB Command RESET_RING (10) */
2329
2330typedef struct {
2331 uint32_t ring_no;
2332} RESET_RING_VAR;
2333
2334/* Structure for MB Command READ_CONFIG (11) */
2335
2336typedef struct {
2337#ifdef __BIG_ENDIAN_BITFIELD
2338 uint32_t cr:1;
2339 uint32_t ci:1;
2340 uint32_t cr_delay:6;
2341 uint32_t cr_count:8;
2342 uint32_t InitBBC:8;
2343 uint32_t MaxBBC:8;
2344#else /* __LITTLE_ENDIAN_BITFIELD */
2345 uint32_t MaxBBC:8;
2346 uint32_t InitBBC:8;
2347 uint32_t cr_count:8;
2348 uint32_t cr_delay:6;
2349 uint32_t ci:1;
2350 uint32_t cr:1;
2351#endif
2352
2353#ifdef __BIG_ENDIAN_BITFIELD
2354 uint32_t topology:8;
2355 uint32_t myDid:24;
2356#else /* __LITTLE_ENDIAN_BITFIELD */
2357 uint32_t myDid:24;
2358 uint32_t topology:8;
2359#endif
2360
2361 /* Defines for topology (defined previously) */
2362#ifdef __BIG_ENDIAN_BITFIELD
2363 uint32_t AR:1;
2364 uint32_t IR:1;
2365 uint32_t rsvd1:29;
2366 uint32_t ack0:1;
2367#else /* __LITTLE_ENDIAN_BITFIELD */
2368 uint32_t ack0:1;
2369 uint32_t rsvd1:29;
2370 uint32_t IR:1;
2371 uint32_t AR:1;
2372#endif
2373
2374 uint32_t edtov;
2375 uint32_t arbtov;
2376 uint32_t ratov;
2377 uint32_t rttov;
2378 uint32_t altov;
2379 uint32_t lmt;
2380#define LMT_RESERVED 0x000 /* Not used */
2381#define LMT_1Gb 0x004
2382#define LMT_2Gb 0x008
2383#define LMT_4Gb 0x040
2384#define LMT_8Gb 0x080
2385#define LMT_10Gb 0x100
2386#define LMT_16Gb 0x200
2387#define LMT_32Gb 0x400
2388 uint32_t rsvd2;
2389 uint32_t rsvd3;
2390 uint32_t max_xri;
2391 uint32_t max_iocb;
2392 uint32_t max_rpi;
2393 uint32_t avail_xri;
2394 uint32_t avail_iocb;
2395 uint32_t avail_rpi;
2396 uint32_t max_vpi;
2397 uint32_t rsvd4;
2398 uint32_t rsvd5;
2399 uint32_t avail_vpi;
2400} READ_CONFIG_VAR;
2401
2402/* Structure for MB Command READ_RCONFIG (12) */
2403
2404typedef struct {
2405#ifdef __BIG_ENDIAN_BITFIELD
2406 uint32_t rsvd2:7;
2407 uint32_t recvNotify:1;
2408 uint32_t numMask:8;
2409 uint32_t profile:8;
2410 uint32_t rsvd1:4;
2411 uint32_t ring:4;
2412#else /* __LITTLE_ENDIAN_BITFIELD */
2413 uint32_t ring:4;
2414 uint32_t rsvd1:4;
2415 uint32_t profile:8;
2416 uint32_t numMask:8;
2417 uint32_t recvNotify:1;
2418 uint32_t rsvd2:7;
2419#endif
2420
2421#ifdef __BIG_ENDIAN_BITFIELD
2422 uint16_t maxResp;
2423 uint16_t maxOrig;
2424#else /* __LITTLE_ENDIAN_BITFIELD */
2425 uint16_t maxOrig;
2426 uint16_t maxResp;
2427#endif
2428
2429 RR_REG rrRegs[6];
2430
2431#ifdef __BIG_ENDIAN_BITFIELD
2432 uint16_t cmdRingOffset;
2433 uint16_t cmdEntryCnt;
2434 uint16_t rspRingOffset;
2435 uint16_t rspEntryCnt;
2436 uint16_t nextCmdOffset;
2437 uint16_t rsvd3;
2438 uint16_t nextRspOffset;
2439 uint16_t rsvd4;
2440#else /* __LITTLE_ENDIAN_BITFIELD */
2441 uint16_t cmdEntryCnt;
2442 uint16_t cmdRingOffset;
2443 uint16_t rspEntryCnt;
2444 uint16_t rspRingOffset;
2445 uint16_t rsvd3;
2446 uint16_t nextCmdOffset;
2447 uint16_t rsvd4;
2448 uint16_t nextRspOffset;
2449#endif
2450} READ_RCONF_VAR;
2451
2452/* Structure for MB Command READ_SPARM (13) */
2453/* Structure for MB Command READ_SPARM64 (0x8D) */
2454
2455typedef struct {
2456 uint32_t rsvd1;
2457 uint32_t rsvd2;
2458 union {
2459 struct ulp_bde sp; /* This BDE points to struct serv_parm
2460 structure */
2461 struct ulp_bde64 sp64;
2462 } un;
2463#ifdef __BIG_ENDIAN_BITFIELD
2464 uint16_t rsvd3;
2465 uint16_t vpi;
2466#else /* __LITTLE_ENDIAN_BITFIELD */
2467 uint16_t vpi;
2468 uint16_t rsvd3;
2469#endif
2470} READ_SPARM_VAR;
2471
2472/* Structure for MB Command READ_STATUS (14) */
2473
2474typedef struct {
2475#ifdef __BIG_ENDIAN_BITFIELD
2476 uint32_t rsvd1:31;
2477 uint32_t clrCounters:1;
2478 uint16_t activeXriCnt;
2479 uint16_t activeRpiCnt;
2480#else /* __LITTLE_ENDIAN_BITFIELD */
2481 uint32_t clrCounters:1;
2482 uint32_t rsvd1:31;
2483 uint16_t activeRpiCnt;
2484 uint16_t activeXriCnt;
2485#endif
2486
2487 uint32_t xmitByteCnt;
2488 uint32_t rcvByteCnt;
2489 uint32_t xmitFrameCnt;
2490 uint32_t rcvFrameCnt;
2491 uint32_t xmitSeqCnt;
2492 uint32_t rcvSeqCnt;
2493 uint32_t totalOrigExchanges;
2494 uint32_t totalRespExchanges;
2495 uint32_t rcvPbsyCnt;
2496 uint32_t rcvFbsyCnt;
2497} READ_STATUS_VAR;
2498
2499/* Structure for MB Command READ_RPI (15) */
2500/* Structure for MB Command READ_RPI64 (0x8F) */
2501
2502typedef struct {
2503#ifdef __BIG_ENDIAN_BITFIELD
2504 uint16_t nextRpi;
2505 uint16_t reqRpi;
2506 uint32_t rsvd2:8;
2507 uint32_t DID:24;
2508#else /* __LITTLE_ENDIAN_BITFIELD */
2509 uint16_t reqRpi;
2510 uint16_t nextRpi;
2511 uint32_t DID:24;
2512 uint32_t rsvd2:8;
2513#endif
2514
2515 union {
2516 struct ulp_bde sp;
2517 struct ulp_bde64 sp64;
2518 } un;
2519
2520} READ_RPI_VAR;
2521
2522/* Structure for MB Command READ_XRI (16) */
2523
2524typedef struct {
2525#ifdef __BIG_ENDIAN_BITFIELD
2526 uint16_t nextXri;
2527 uint16_t reqXri;
2528 uint16_t rsvd1;
2529 uint16_t rpi;
2530 uint32_t rsvd2:8;
2531 uint32_t DID:24;
2532 uint32_t rsvd3:8;
2533 uint32_t SID:24;
2534 uint32_t rsvd4;
2535 uint8_t seqId;
2536 uint8_t rsvd5;
2537 uint16_t seqCount;
2538 uint16_t oxId;
2539 uint16_t rxId;
2540 uint32_t rsvd6:30;
2541 uint32_t si:1;
2542 uint32_t exchOrig:1;
2543#else /* __LITTLE_ENDIAN_BITFIELD */
2544 uint16_t reqXri;
2545 uint16_t nextXri;
2546 uint16_t rpi;
2547 uint16_t rsvd1;
2548 uint32_t DID:24;
2549 uint32_t rsvd2:8;
2550 uint32_t SID:24;
2551 uint32_t rsvd3:8;
2552 uint32_t rsvd4;
2553 uint16_t seqCount;
2554 uint8_t rsvd5;
2555 uint8_t seqId;
2556 uint16_t rxId;
2557 uint16_t oxId;
2558 uint32_t exchOrig:1;
2559 uint32_t si:1;
2560 uint32_t rsvd6:30;
2561#endif
2562} READ_XRI_VAR;
2563
2564/* Structure for MB Command READ_REV (17) */
2565
2566typedef struct {
2567#ifdef __BIG_ENDIAN_BITFIELD
2568 uint32_t cv:1;
2569 uint32_t rr:1;
2570 uint32_t rsvd2:2;
2571 uint32_t v3req:1;
2572 uint32_t v3rsp:1;
2573 uint32_t rsvd1:25;
2574 uint32_t rv:1;
2575#else /* __LITTLE_ENDIAN_BITFIELD */
2576 uint32_t rv:1;
2577 uint32_t rsvd1:25;
2578 uint32_t v3rsp:1;
2579 uint32_t v3req:1;
2580 uint32_t rsvd2:2;
2581 uint32_t rr:1;
2582 uint32_t cv:1;
2583#endif
2584
2585 uint32_t biuRev;
2586 uint32_t smRev;
2587 union {
2588 uint32_t smFwRev;
2589 struct {
2590#ifdef __BIG_ENDIAN_BITFIELD
2591 uint8_t ProgType;
2592 uint8_t ProgId;
2593 uint16_t ProgVer:4;
2594 uint16_t ProgRev:4;
2595 uint16_t ProgFixLvl:2;
2596 uint16_t ProgDistType:2;
2597 uint16_t DistCnt:4;
2598#else /* __LITTLE_ENDIAN_BITFIELD */
2599 uint16_t DistCnt:4;
2600 uint16_t ProgDistType:2;
2601 uint16_t ProgFixLvl:2;
2602 uint16_t ProgRev:4;
2603 uint16_t ProgVer:4;
2604 uint8_t ProgId;
2605 uint8_t ProgType;
2606#endif
2607
2608 } b;
2609 } un;
2610 uint32_t endecRev;
2611#ifdef __BIG_ENDIAN_BITFIELD
2612 uint8_t feaLevelHigh;
2613 uint8_t feaLevelLow;
2614 uint8_t fcphHigh;
2615 uint8_t fcphLow;
2616#else /* __LITTLE_ENDIAN_BITFIELD */
2617 uint8_t fcphLow;
2618 uint8_t fcphHigh;
2619 uint8_t feaLevelLow;
2620 uint8_t feaLevelHigh;
2621#endif
2622
2623 uint32_t postKernRev;
2624 uint32_t opFwRev;
2625 uint8_t opFwName[16];
2626 uint32_t sli1FwRev;
2627 uint8_t sli1FwName[16];
2628 uint32_t sli2FwRev;
2629 uint8_t sli2FwName[16];
2630 uint32_t sli3Feat;
2631 uint32_t RandomData[6];
2632} READ_REV_VAR;
2633
2634/* Structure for MB Command READ_LINK_STAT (18) */
2635
2636typedef struct {
2637 uint32_t word0;
2638
2639#define lpfc_read_link_stat_rec_SHIFT 0
2640#define lpfc_read_link_stat_rec_MASK 0x1
2641#define lpfc_read_link_stat_rec_WORD word0
2642
2643#define lpfc_read_link_stat_gec_SHIFT 1
2644#define lpfc_read_link_stat_gec_MASK 0x1
2645#define lpfc_read_link_stat_gec_WORD word0
2646
2647#define lpfc_read_link_stat_w02oftow23of_SHIFT 2
2648#define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF
2649#define lpfc_read_link_stat_w02oftow23of_WORD word0
2650
2651#define lpfc_read_link_stat_rsvd_SHIFT 24
2652#define lpfc_read_link_stat_rsvd_MASK 0x1F
2653#define lpfc_read_link_stat_rsvd_WORD word0
2654
2655#define lpfc_read_link_stat_gec2_SHIFT 29
2656#define lpfc_read_link_stat_gec2_MASK 0x1
2657#define lpfc_read_link_stat_gec2_WORD word0
2658
2659#define lpfc_read_link_stat_clrc_SHIFT 30
2660#define lpfc_read_link_stat_clrc_MASK 0x1
2661#define lpfc_read_link_stat_clrc_WORD word0
2662
2663#define lpfc_read_link_stat_clof_SHIFT 31
2664#define lpfc_read_link_stat_clof_MASK 0x1
2665#define lpfc_read_link_stat_clof_WORD word0
2666
2667 uint32_t linkFailureCnt;
2668 uint32_t lossSyncCnt;
2669 uint32_t lossSignalCnt;
2670 uint32_t primSeqErrCnt;
2671 uint32_t invalidXmitWord;
2672 uint32_t crcCnt;
2673 uint32_t primSeqTimeout;
2674 uint32_t elasticOverrun;
2675 uint32_t arbTimeout;
2676 uint32_t advRecBufCredit;
2677 uint32_t curRecBufCredit;
2678 uint32_t advTransBufCredit;
2679 uint32_t curTransBufCredit;
2680 uint32_t recEofCount;
2681 uint32_t recEofdtiCount;
2682 uint32_t recEofniCount;
2683 uint32_t recSofcount;
2684 uint32_t rsvd1;
2685 uint32_t rsvd2;
2686 uint32_t recDrpXriCount;
2687 uint32_t fecCorrBlkCount;
2688 uint32_t fecUncorrBlkCount;
2689} READ_LNK_VAR;
2690
2691/* Structure for MB Command REG_LOGIN (19) */
2692/* Structure for MB Command REG_LOGIN64 (0x93) */
2693
2694typedef struct {
2695#ifdef __BIG_ENDIAN_BITFIELD
2696 uint16_t rsvd1;
2697 uint16_t rpi;
2698 uint32_t rsvd2:8;
2699 uint32_t did:24;
2700#else /* __LITTLE_ENDIAN_BITFIELD */
2701 uint16_t rpi;
2702 uint16_t rsvd1;
2703 uint32_t did:24;
2704 uint32_t rsvd2:8;
2705#endif
2706
2707 union {
2708 struct ulp_bde sp;
2709 struct ulp_bde64 sp64;
2710 } un;
2711
2712#ifdef __BIG_ENDIAN_BITFIELD
2713 uint16_t rsvd6;
2714 uint16_t vpi;
2715#else /* __LITTLE_ENDIAN_BITFIELD */
2716 uint16_t vpi;
2717 uint16_t rsvd6;
2718#endif
2719
2720} REG_LOGIN_VAR;
2721
2722/* Word 30 contents for REG_LOGIN */
2723typedef union {
2724 struct {
2725#ifdef __BIG_ENDIAN_BITFIELD
2726 uint16_t rsvd1:12;
2727 uint16_t wd30_class:4;
2728 uint16_t xri;
2729#else /* __LITTLE_ENDIAN_BITFIELD */
2730 uint16_t xri;
2731 uint16_t wd30_class:4;
2732 uint16_t rsvd1:12;
2733#endif
2734 } f;
2735 uint32_t word;
2736} REG_WD30;
2737
2738/* Structure for MB Command UNREG_LOGIN (20) */
2739
2740typedef struct {
2741#ifdef __BIG_ENDIAN_BITFIELD
2742 uint16_t rsvd1;
2743 uint16_t rpi;
2744 uint32_t rsvd2;
2745 uint32_t rsvd3;
2746 uint32_t rsvd4;
2747 uint32_t rsvd5;
2748 uint16_t rsvd6;
2749 uint16_t vpi;
2750#else /* __LITTLE_ENDIAN_BITFIELD */
2751 uint16_t rpi;
2752 uint16_t rsvd1;
2753 uint32_t rsvd2;
2754 uint32_t rsvd3;
2755 uint32_t rsvd4;
2756 uint32_t rsvd5;
2757 uint16_t vpi;
2758 uint16_t rsvd6;
2759#endif
2760} UNREG_LOGIN_VAR;
2761
2762/* Structure for MB Command REG_VPI (0x96) */
2763typedef struct {
2764#ifdef __BIG_ENDIAN_BITFIELD
2765 uint32_t rsvd1;
2766 uint32_t rsvd2:7;
2767 uint32_t upd:1;
2768 uint32_t sid:24;
2769 uint32_t wwn[2];
2770 uint32_t rsvd5;
2771 uint16_t vfi;
2772 uint16_t vpi;
2773#else /* __LITTLE_ENDIAN */
2774 uint32_t rsvd1;
2775 uint32_t sid:24;
2776 uint32_t upd:1;
2777 uint32_t rsvd2:7;
2778 uint32_t wwn[2];
2779 uint32_t rsvd5;
2780 uint16_t vpi;
2781 uint16_t vfi;
2782#endif
2783} REG_VPI_VAR;
2784
2785/* Structure for MB Command UNREG_VPI (0x97) */
2786typedef struct {
2787 uint32_t rsvd1;
2788#ifdef __BIG_ENDIAN_BITFIELD
2789 uint16_t rsvd2;
2790 uint16_t sli4_vpi;
2791#else /* __LITTLE_ENDIAN */
2792 uint16_t sli4_vpi;
2793 uint16_t rsvd2;
2794#endif
2795 uint32_t rsvd3;
2796 uint32_t rsvd4;
2797 uint32_t rsvd5;
2798#ifdef __BIG_ENDIAN_BITFIELD
2799 uint16_t rsvd6;
2800 uint16_t vpi;
2801#else /* __LITTLE_ENDIAN */
2802 uint16_t vpi;
2803 uint16_t rsvd6;
2804#endif
2805} UNREG_VPI_VAR;
2806
2807/* Structure for MB Command UNREG_D_ID (0x23) */
2808
2809typedef struct {
2810 uint32_t did;
2811 uint32_t rsvd2;
2812 uint32_t rsvd3;
2813 uint32_t rsvd4;
2814 uint32_t rsvd5;
2815#ifdef __BIG_ENDIAN_BITFIELD
2816 uint16_t rsvd6;
2817 uint16_t vpi;
2818#else
2819 uint16_t vpi;
2820 uint16_t rsvd6;
2821#endif
2822} UNREG_D_ID_VAR;
2823
2824/* Structure for MB Command READ_TOPOLOGY (0x95) */
2825struct lpfc_mbx_read_top {
2826 uint32_t eventTag; /* Event tag */
2827 uint32_t word2;
2828#define lpfc_mbx_read_top_fa_SHIFT 12
2829#define lpfc_mbx_read_top_fa_MASK 0x00000001
2830#define lpfc_mbx_read_top_fa_WORD word2
2831#define lpfc_mbx_read_top_mm_SHIFT 11
2832#define lpfc_mbx_read_top_mm_MASK 0x00000001
2833#define lpfc_mbx_read_top_mm_WORD word2
2834#define lpfc_mbx_read_top_pb_SHIFT 9
2835#define lpfc_mbx_read_top_pb_MASK 0X00000001
2836#define lpfc_mbx_read_top_pb_WORD word2
2837#define lpfc_mbx_read_top_il_SHIFT 8
2838#define lpfc_mbx_read_top_il_MASK 0x00000001
2839#define lpfc_mbx_read_top_il_WORD word2
2840#define lpfc_mbx_read_top_att_type_SHIFT 0
2841#define lpfc_mbx_read_top_att_type_MASK 0x000000FF
2842#define lpfc_mbx_read_top_att_type_WORD word2
2843#define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
2844#define LPFC_ATT_LINK_UP 0x01 /* Link is up */
2845#define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
2846 uint32_t word3;
2847#define lpfc_mbx_read_top_alpa_granted_SHIFT 24
2848#define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
2849#define lpfc_mbx_read_top_alpa_granted_WORD word3
2850#define lpfc_mbx_read_top_lip_alps_SHIFT 16
2851#define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
2852#define lpfc_mbx_read_top_lip_alps_WORD word3
2853#define lpfc_mbx_read_top_lip_type_SHIFT 8
2854#define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
2855#define lpfc_mbx_read_top_lip_type_WORD word3
2856#define lpfc_mbx_read_top_topology_SHIFT 0
2857#define lpfc_mbx_read_top_topology_MASK 0x000000FF
2858#define lpfc_mbx_read_top_topology_WORD word3
2859#define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2860#define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2861#define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
2862 /* store the LILP AL_PA position map into */
2863 struct ulp_bde64 lilpBde64;
2864#define LPFC_ALPA_MAP_SIZE 128
2865 uint32_t word7;
2866#define lpfc_mbx_read_top_ld_lu_SHIFT 31
2867#define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
2868#define lpfc_mbx_read_top_ld_lu_WORD word7
2869#define lpfc_mbx_read_top_ld_tf_SHIFT 30
2870#define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
2871#define lpfc_mbx_read_top_ld_tf_WORD word7
2872#define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
2873#define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
2874#define lpfc_mbx_read_top_ld_link_spd_WORD word7
2875#define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
2876#define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
2877#define lpfc_mbx_read_top_ld_nl_port_WORD word7
2878#define lpfc_mbx_read_top_ld_tx_SHIFT 2
2879#define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
2880#define lpfc_mbx_read_top_ld_tx_WORD word7
2881#define lpfc_mbx_read_top_ld_rx_SHIFT 0
2882#define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
2883#define lpfc_mbx_read_top_ld_rx_WORD word7
2884 uint32_t word8;
2885#define lpfc_mbx_read_top_lu_SHIFT 31
2886#define lpfc_mbx_read_top_lu_MASK 0x00000001
2887#define lpfc_mbx_read_top_lu_WORD word8
2888#define lpfc_mbx_read_top_tf_SHIFT 30
2889#define lpfc_mbx_read_top_tf_MASK 0x00000001
2890#define lpfc_mbx_read_top_tf_WORD word8
2891#define lpfc_mbx_read_top_link_spd_SHIFT 8
2892#define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
2893#define lpfc_mbx_read_top_link_spd_WORD word8
2894#define lpfc_mbx_read_top_nl_port_SHIFT 4
2895#define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
2896#define lpfc_mbx_read_top_nl_port_WORD word8
2897#define lpfc_mbx_read_top_tx_SHIFT 2
2898#define lpfc_mbx_read_top_tx_MASK 0x00000003
2899#define lpfc_mbx_read_top_tx_WORD word8
2900#define lpfc_mbx_read_top_rx_SHIFT 0
2901#define lpfc_mbx_read_top_rx_MASK 0x00000003
2902#define lpfc_mbx_read_top_rx_WORD word8
2903#define LPFC_LINK_SPEED_UNKNOWN 0x0
2904#define LPFC_LINK_SPEED_1GHZ 0x04
2905#define LPFC_LINK_SPEED_2GHZ 0x08
2906#define LPFC_LINK_SPEED_4GHZ 0x10
2907#define LPFC_LINK_SPEED_8GHZ 0x20
2908#define LPFC_LINK_SPEED_10GHZ 0x40
2909#define LPFC_LINK_SPEED_16GHZ 0x80
2910#define LPFC_LINK_SPEED_32GHZ 0x90
2911};
2912
2913/* Structure for MB Command CLEAR_LA (22) */
2914
2915typedef struct {
2916 uint32_t eventTag; /* Event tag */
2917 uint32_t rsvd1;
2918} CLEAR_LA_VAR;
2919
2920/* Structure for MB Command DUMP */
2921
2922typedef struct {
2923#ifdef __BIG_ENDIAN_BITFIELD
2924 uint32_t rsvd:25;
2925 uint32_t ra:1;
2926 uint32_t co:1;
2927 uint32_t cv:1;
2928 uint32_t type:4;
2929 uint32_t entry_index:16;
2930 uint32_t region_id:16;
2931#else /* __LITTLE_ENDIAN_BITFIELD */
2932 uint32_t type:4;
2933 uint32_t cv:1;
2934 uint32_t co:1;
2935 uint32_t ra:1;
2936 uint32_t rsvd:25;
2937 uint32_t region_id:16;
2938 uint32_t entry_index:16;
2939#endif
2940
2941 uint32_t sli4_length;
2942 uint32_t word_cnt;
2943 uint32_t resp_offset;
2944} DUMP_VAR;
2945
2946#define DMP_MEM_REG 0x1
2947#define DMP_NV_PARAMS 0x2
2948#define DMP_LMSD 0x3 /* Link Module Serial Data */
2949#define DMP_WELL_KNOWN 0x4
2950
2951#define DMP_REGION_VPD 0xe
2952#define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2953#define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2954#define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2955
2956#define DMP_REGION_VPORT 0x16 /* VPort info region */
2957#define DMP_VPORT_REGION_SIZE 0x200
2958#define DMP_MBOX_OFFSET_WORD 0x5
2959
2960#define DMP_REGION_23 0x17 /* fcoe param and port state region */
2961#define DMP_RGN23_SIZE 0x400
2962
2963#define WAKE_UP_PARMS_REGION_ID 4
2964#define WAKE_UP_PARMS_WORD_SIZE 15
2965
2966struct vport_rec {
2967 uint8_t wwpn[8];
2968 uint8_t wwnn[8];
2969};
2970
2971#define VPORT_INFO_SIG 0x32324752
2972#define VPORT_INFO_REV_MASK 0xff
2973#define VPORT_INFO_REV 0x1
2974#define MAX_STATIC_VPORT_COUNT 16
2975struct static_vport_info {
2976 uint32_t signature;
2977 uint32_t rev;
2978 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
2979 uint32_t resvd[66];
2980};
2981
2982/* Option rom version structure */
2983struct prog_id {
2984#ifdef __BIG_ENDIAN_BITFIELD
2985 uint8_t type;
2986 uint8_t id;
2987 uint32_t ver:4; /* Major Version */
2988 uint32_t rev:4; /* Revision */
2989 uint32_t lev:2; /* Level */
2990 uint32_t dist:2; /* Dist Type */
2991 uint32_t num:4; /* number after dist type */
2992#else /* __LITTLE_ENDIAN_BITFIELD */
2993 uint32_t num:4; /* number after dist type */
2994 uint32_t dist:2; /* Dist Type */
2995 uint32_t lev:2; /* Level */
2996 uint32_t rev:4; /* Revision */
2997 uint32_t ver:4; /* Major Version */
2998 uint8_t id;
2999 uint8_t type;
3000#endif
3001};
3002
3003/* Structure for MB Command UPDATE_CFG (0x1B) */
3004
3005struct update_cfg_var {
3006#ifdef __BIG_ENDIAN_BITFIELD
3007 uint32_t rsvd2:16;
3008 uint32_t type:8;
3009 uint32_t rsvd:1;
3010 uint32_t ra:1;
3011 uint32_t co:1;
3012 uint32_t cv:1;
3013 uint32_t req:4;
3014 uint32_t entry_length:16;
3015 uint32_t region_id:16;
3016#else /* __LITTLE_ENDIAN_BITFIELD */
3017 uint32_t req:4;
3018 uint32_t cv:1;
3019 uint32_t co:1;
3020 uint32_t ra:1;
3021 uint32_t rsvd:1;
3022 uint32_t type:8;
3023 uint32_t rsvd2:16;
3024 uint32_t region_id:16;
3025 uint32_t entry_length:16;
3026#endif
3027
3028 uint32_t resp_info;
3029 uint32_t byte_cnt;
3030 uint32_t data_offset;
3031};
3032
3033struct hbq_mask {
3034#ifdef __BIG_ENDIAN_BITFIELD
3035 uint8_t tmatch;
3036 uint8_t tmask;
3037 uint8_t rctlmatch;
3038 uint8_t rctlmask;
3039#else /* __LITTLE_ENDIAN */
3040 uint8_t rctlmask;
3041 uint8_t rctlmatch;
3042 uint8_t tmask;
3043 uint8_t tmatch;
3044#endif
3045};
3046
3047
3048/* Structure for MB Command CONFIG_HBQ (7c) */
3049
3050struct config_hbq_var {
3051#ifdef __BIG_ENDIAN_BITFIELD
3052 uint32_t rsvd1 :7;
3053 uint32_t recvNotify :1; /* Receive Notification */
3054 uint32_t numMask :8; /* # Mask Entries */
3055 uint32_t profile :8; /* Selection Profile */
3056 uint32_t rsvd2 :8;
3057#else /* __LITTLE_ENDIAN */
3058 uint32_t rsvd2 :8;
3059 uint32_t profile :8; /* Selection Profile */
3060 uint32_t numMask :8; /* # Mask Entries */
3061 uint32_t recvNotify :1; /* Receive Notification */
3062 uint32_t rsvd1 :7;
3063#endif
3064
3065#ifdef __BIG_ENDIAN_BITFIELD
3066 uint32_t hbqId :16;
3067 uint32_t rsvd3 :12;
3068 uint32_t ringMask :4;
3069#else /* __LITTLE_ENDIAN */
3070 uint32_t ringMask :4;
3071 uint32_t rsvd3 :12;
3072 uint32_t hbqId :16;
3073#endif
3074
3075#ifdef __BIG_ENDIAN_BITFIELD
3076 uint32_t entry_count :16;
3077 uint32_t rsvd4 :8;
3078 uint32_t headerLen :8;
3079#else /* __LITTLE_ENDIAN */
3080 uint32_t headerLen :8;
3081 uint32_t rsvd4 :8;
3082 uint32_t entry_count :16;
3083#endif
3084
3085 uint32_t hbqaddrLow;
3086 uint32_t hbqaddrHigh;
3087
3088#ifdef __BIG_ENDIAN_BITFIELD
3089 uint32_t rsvd5 :31;
3090 uint32_t logEntry :1;
3091#else /* __LITTLE_ENDIAN */
3092 uint32_t logEntry :1;
3093 uint32_t rsvd5 :31;
3094#endif
3095
3096 uint32_t rsvd6; /* w7 */
3097 uint32_t rsvd7; /* w8 */
3098 uint32_t rsvd8; /* w9 */
3099
3100 struct hbq_mask hbqMasks[6];
3101
3102
3103 union {
3104 uint32_t allprofiles[12];
3105
3106 struct {
3107 #ifdef __BIG_ENDIAN_BITFIELD
3108 uint32_t seqlenoff :16;
3109 uint32_t maxlen :16;
3110 #else /* __LITTLE_ENDIAN */
3111 uint32_t maxlen :16;
3112 uint32_t seqlenoff :16;
3113 #endif
3114 #ifdef __BIG_ENDIAN_BITFIELD
3115 uint32_t rsvd1 :28;
3116 uint32_t seqlenbcnt :4;
3117 #else /* __LITTLE_ENDIAN */
3118 uint32_t seqlenbcnt :4;
3119 uint32_t rsvd1 :28;
3120 #endif
3121 uint32_t rsvd[10];
3122 } profile2;
3123
3124 struct {
3125 #ifdef __BIG_ENDIAN_BITFIELD
3126 uint32_t seqlenoff :16;
3127 uint32_t maxlen :16;
3128 #else /* __LITTLE_ENDIAN */
3129 uint32_t maxlen :16;
3130 uint32_t seqlenoff :16;
3131 #endif
3132 #ifdef __BIG_ENDIAN_BITFIELD
3133 uint32_t cmdcodeoff :28;
3134 uint32_t rsvd1 :12;
3135 uint32_t seqlenbcnt :4;
3136 #else /* __LITTLE_ENDIAN */
3137 uint32_t seqlenbcnt :4;
3138 uint32_t rsvd1 :12;
3139 uint32_t cmdcodeoff :28;
3140 #endif
3141 uint32_t cmdmatch[8];
3142
3143 uint32_t rsvd[2];
3144 } profile3;
3145
3146 struct {
3147 #ifdef __BIG_ENDIAN_BITFIELD
3148 uint32_t seqlenoff :16;
3149 uint32_t maxlen :16;
3150 #else /* __LITTLE_ENDIAN */
3151 uint32_t maxlen :16;
3152 uint32_t seqlenoff :16;
3153 #endif
3154 #ifdef __BIG_ENDIAN_BITFIELD
3155 uint32_t cmdcodeoff :28;
3156 uint32_t rsvd1 :12;
3157 uint32_t seqlenbcnt :4;
3158 #else /* __LITTLE_ENDIAN */
3159 uint32_t seqlenbcnt :4;
3160 uint32_t rsvd1 :12;
3161 uint32_t cmdcodeoff :28;
3162 #endif
3163 uint32_t cmdmatch[8];
3164
3165 uint32_t rsvd[2];
3166 } profile5;
3167
3168 } profiles;
3169
3170};
3171
3172
3173
3174/* Structure for MB Command CONFIG_PORT (0x88) */
3175typedef struct {
3176#ifdef __BIG_ENDIAN_BITFIELD
3177 uint32_t cBE : 1;
3178 uint32_t cET : 1;
3179 uint32_t cHpcb : 1;
3180 uint32_t cMA : 1;
3181 uint32_t sli_mode : 4;
3182 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3183 * config block */
3184#else /* __LITTLE_ENDIAN */
3185 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3186 * config block */
3187 uint32_t sli_mode : 4;
3188 uint32_t cMA : 1;
3189 uint32_t cHpcb : 1;
3190 uint32_t cET : 1;
3191 uint32_t cBE : 1;
3192#endif
3193
3194 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
3195 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
3196 uint32_t hbainit[5];
3197#ifdef __BIG_ENDIAN_BITFIELD
3198 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3199 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3200#else /* __LITTLE_ENDIAN */
3201 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3202 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3203#endif
3204
3205#ifdef __BIG_ENDIAN_BITFIELD
3206 uint32_t rsvd1 : 19; /* Reserved */
3207 uint32_t cdss : 1; /* Configure Data Security SLI */
3208 uint32_t casabt : 1; /* Configure async abts status notice */
3209 uint32_t rsvd2 : 2; /* Reserved */
3210 uint32_t cbg : 1; /* Configure BlockGuard */
3211 uint32_t cmv : 1; /* Configure Max VPIs */
3212 uint32_t ccrp : 1; /* Config Command Ring Polling */
3213 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3214 uint32_t chbs : 1; /* Cofigure Host Backing store */
3215 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3216 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3217 uint32_t cmx : 1; /* Configure Max XRIs */
3218 uint32_t cmr : 1; /* Configure Max RPIs */
3219#else /* __LITTLE_ENDIAN */
3220 uint32_t cmr : 1; /* Configure Max RPIs */
3221 uint32_t cmx : 1; /* Configure Max XRIs */
3222 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3223 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3224 uint32_t chbs : 1; /* Cofigure Host Backing store */
3225 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3226 uint32_t ccrp : 1; /* Config Command Ring Polling */
3227 uint32_t cmv : 1; /* Configure Max VPIs */
3228 uint32_t cbg : 1; /* Configure BlockGuard */
3229 uint32_t rsvd2 : 2; /* Reserved */
3230 uint32_t casabt : 1; /* Configure async abts status notice */
3231 uint32_t cdss : 1; /* Configure Data Security SLI */
3232 uint32_t rsvd1 : 19; /* Reserved */
3233#endif
3234#ifdef __BIG_ENDIAN_BITFIELD
3235 uint32_t rsvd3 : 19; /* Reserved */
3236 uint32_t gdss : 1; /* Configure Data Security SLI */
3237 uint32_t gasabt : 1; /* Grant async abts status notice */
3238 uint32_t rsvd4 : 2; /* Reserved */
3239 uint32_t gbg : 1; /* Grant BlockGuard */
3240 uint32_t gmv : 1; /* Grant Max VPIs */
3241 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3242 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3243 uint32_t ghbs : 1; /* Grant Host Backing Store */
3244 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3245 uint32_t gerbm : 1; /* Grant ERBM Request */
3246 uint32_t gmx : 1; /* Grant Max XRIs */
3247 uint32_t gmr : 1; /* Grant Max RPIs */
3248#else /* __LITTLE_ENDIAN */
3249 uint32_t gmr : 1; /* Grant Max RPIs */
3250 uint32_t gmx : 1; /* Grant Max XRIs */
3251 uint32_t gerbm : 1; /* Grant ERBM Request */
3252 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3253 uint32_t ghbs : 1; /* Grant Host Backing Store */
3254 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3255 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3256 uint32_t gmv : 1; /* Grant Max VPIs */
3257 uint32_t gbg : 1; /* Grant BlockGuard */
3258 uint32_t rsvd4 : 2; /* Reserved */
3259 uint32_t gasabt : 1; /* Grant async abts status notice */
3260 uint32_t gdss : 1; /* Configure Data Security SLI */
3261 uint32_t rsvd3 : 19; /* Reserved */
3262#endif
3263
3264#ifdef __BIG_ENDIAN_BITFIELD
3265 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3266 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3267#else /* __LITTLE_ENDIAN */
3268 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3269 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3270#endif
3271
3272#ifdef __BIG_ENDIAN_BITFIELD
3273 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3274 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3275#else /* __LITTLE_ENDIAN */
3276 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3277 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3278#endif
3279
3280 uint32_t rsvd6; /* Reserved */
3281
3282#ifdef __BIG_ENDIAN_BITFIELD
3283 uint32_t fips_rev : 3; /* FIPS Spec Revision */
3284 uint32_t fips_level : 4; /* FIPS Level */
3285 uint32_t sec_err : 9; /* security crypto error */
3286 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3287#else /* __LITTLE_ENDIAN */
3288 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3289 uint32_t sec_err : 9; /* security crypto error */
3290 uint32_t fips_level : 4; /* FIPS Level */
3291 uint32_t fips_rev : 3; /* FIPS Spec Revision */
3292#endif
3293
3294} CONFIG_PORT_VAR;
3295
3296/* Structure for MB Command CONFIG_MSI (0x30) */
3297struct config_msi_var {
3298#ifdef __BIG_ENDIAN_BITFIELD
3299 uint32_t dfltMsgNum:8; /* Default message number */
3300 uint32_t rsvd1:11; /* Reserved */
3301 uint32_t NID:5; /* Number of secondary attention IDs */
3302 uint32_t rsvd2:5; /* Reserved */
3303 uint32_t dfltPresent:1; /* Default message number present */
3304 uint32_t addFlag:1; /* Add association flag */
3305 uint32_t reportFlag:1; /* Report association flag */
3306#else /* __LITTLE_ENDIAN_BITFIELD */
3307 uint32_t reportFlag:1; /* Report association flag */
3308 uint32_t addFlag:1; /* Add association flag */
3309 uint32_t dfltPresent:1; /* Default message number present */
3310 uint32_t rsvd2:5; /* Reserved */
3311 uint32_t NID:5; /* Number of secondary attention IDs */
3312 uint32_t rsvd1:11; /* Reserved */
3313 uint32_t dfltMsgNum:8; /* Default message number */
3314#endif
3315 uint32_t attentionConditions[2];
3316 uint8_t attentionId[16];
3317 uint8_t messageNumberByHA[64];
3318 uint8_t messageNumberByID[16];
3319 uint32_t autoClearHA[2];
3320#ifdef __BIG_ENDIAN_BITFIELD
3321 uint32_t rsvd3:16;
3322 uint32_t autoClearID:16;
3323#else /* __LITTLE_ENDIAN_BITFIELD */
3324 uint32_t autoClearID:16;
3325 uint32_t rsvd3:16;
3326#endif
3327 uint32_t rsvd4;
3328};
3329
3330/* SLI-2 Port Control Block */
3331
3332/* SLIM POINTER */
3333#define SLIMOFF 0x30 /* WORD */
3334
3335typedef struct _SLI2_RDSC {
3336 uint32_t cmdEntries;
3337 uint32_t cmdAddrLow;
3338 uint32_t cmdAddrHigh;
3339
3340 uint32_t rspEntries;
3341 uint32_t rspAddrLow;
3342 uint32_t rspAddrHigh;
3343} SLI2_RDSC;
3344
3345typedef struct _PCB {
3346#ifdef __BIG_ENDIAN_BITFIELD
3347 uint32_t type:8;
3348#define TYPE_NATIVE_SLI2 0x01
3349 uint32_t feature:8;
3350#define FEATURE_INITIAL_SLI2 0x01
3351 uint32_t rsvd:12;
3352 uint32_t maxRing:4;
3353#else /* __LITTLE_ENDIAN_BITFIELD */
3354 uint32_t maxRing:4;
3355 uint32_t rsvd:12;
3356 uint32_t feature:8;
3357#define FEATURE_INITIAL_SLI2 0x01
3358 uint32_t type:8;
3359#define TYPE_NATIVE_SLI2 0x01
3360#endif
3361
3362 uint32_t mailBoxSize;
3363 uint32_t mbAddrLow;
3364 uint32_t mbAddrHigh;
3365
3366 uint32_t hgpAddrLow;
3367 uint32_t hgpAddrHigh;
3368
3369 uint32_t pgpAddrLow;
3370 uint32_t pgpAddrHigh;
3371 SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3372} PCB_t;
3373
3374/* NEW_FEATURE */
3375typedef struct {
3376#ifdef __BIG_ENDIAN_BITFIELD
3377 uint32_t rsvd0:27;
3378 uint32_t discardFarp:1;
3379 uint32_t IPEnable:1;
3380 uint32_t nodeName:1;
3381 uint32_t portName:1;
3382 uint32_t filterEnable:1;
3383#else /* __LITTLE_ENDIAN_BITFIELD */
3384 uint32_t filterEnable:1;
3385 uint32_t portName:1;
3386 uint32_t nodeName:1;
3387 uint32_t IPEnable:1;
3388 uint32_t discardFarp:1;
3389 uint32_t rsvd:27;
3390#endif
3391
3392 uint8_t portname[8]; /* Used to be struct lpfc_name */
3393 uint8_t nodename[8];
3394 uint32_t rsvd1;
3395 uint32_t rsvd2;
3396 uint32_t rsvd3;
3397 uint32_t IPAddress;
3398} CONFIG_FARP_VAR;
3399
3400/* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3401
3402typedef struct {
3403#ifdef __BIG_ENDIAN_BITFIELD
3404 uint32_t rsvd:30;
3405 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3406#else /* __LITTLE_ENDIAN */
3407 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3408 uint32_t rsvd:30;
3409#endif
3410} ASYNCEVT_ENABLE_VAR;
3411
3412/* Union of all Mailbox Command types */
3413#define MAILBOX_CMD_WSIZE 32
3414#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3415/* ext_wsize times 4 bytes should not be greater than max xmit size */
3416#define MAILBOX_EXT_WSIZE 512
3417#define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3418#define MAILBOX_HBA_EXT_OFFSET 0x100
3419/* max mbox xmit size is a page size for sysfs IO operations */
3420#define MAILBOX_SYSFS_MAX 4096
3421
3422typedef union {
3423 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3424 * feature/max ring number
3425 */
3426 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3427 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3428 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
3429 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3430 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
3431 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
3432 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3433 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
3434 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3435 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3436 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3437 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3438 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3439 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
3440 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3441 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3442 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3443 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
3444 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3445 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
3446 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
3447 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3448 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3449 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3450 * NEW_FEATURE
3451 */
3452 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
3453 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3454 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
3455 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3456 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3457 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
3458 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3459 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3460 * (READ_EVENT_LOG)
3461 */
3462 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
3463} MAILVARIANTS;
3464
3465/*
3466 * SLI-2 specific structures
3467 */
3468
3469struct lpfc_hgp {
3470 __le32 cmdPutInx;
3471 __le32 rspGetInx;
3472};
3473
3474struct lpfc_pgp {
3475 __le32 cmdGetInx;
3476 __le32 rspPutInx;
3477};
3478
3479struct sli2_desc {
3480 uint32_t unused1[16];
3481 struct lpfc_hgp host[MAX_SLI3_RINGS];
3482 struct lpfc_pgp port[MAX_SLI3_RINGS];
3483};
3484
3485struct sli3_desc {
3486 struct lpfc_hgp host[MAX_SLI3_RINGS];
3487 uint32_t reserved[8];
3488 uint32_t hbq_put[16];
3489};
3490
3491struct sli3_pgp {
3492 struct lpfc_pgp port[MAX_SLI3_RINGS];
3493 uint32_t hbq_get[16];
3494};
3495
3496union sli_var {
3497 struct sli2_desc s2;
3498 struct sli3_desc s3;
3499 struct sli3_pgp s3_pgp;
3500};
3501
3502typedef struct {
3503#ifdef __BIG_ENDIAN_BITFIELD
3504 uint16_t mbxStatus;
3505 uint8_t mbxCommand;
3506 uint8_t mbxReserved:6;
3507 uint8_t mbxHc:1;
3508 uint8_t mbxOwner:1; /* Low order bit first word */
3509#else /* __LITTLE_ENDIAN_BITFIELD */
3510 uint8_t mbxOwner:1; /* Low order bit first word */
3511 uint8_t mbxHc:1;
3512 uint8_t mbxReserved:6;
3513 uint8_t mbxCommand;
3514 uint16_t mbxStatus;
3515#endif
3516
3517 MAILVARIANTS un;
3518 union sli_var us;
3519} MAILBOX_t;
3520
3521/*
3522 * Begin Structure Definitions for IOCB Commands
3523 */
3524
3525typedef struct {
3526#ifdef __BIG_ENDIAN_BITFIELD
3527 uint8_t statAction;
3528 uint8_t statRsn;
3529 uint8_t statBaExp;
3530 uint8_t statLocalError;
3531#else /* __LITTLE_ENDIAN_BITFIELD */
3532 uint8_t statLocalError;
3533 uint8_t statBaExp;
3534 uint8_t statRsn;
3535 uint8_t statAction;
3536#endif
3537 /* statRsn P/F_RJT reason codes */
3538#define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3539#define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3540#define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3541#define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3542#define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3543#define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3544#define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3545#define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3546#define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3547#define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3548#define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3549#define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3550#define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3551#define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3552#define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3553#define RJT_BAD_PARM 0x10 /* Param. field invalid */
3554#define RJT_XCHG_ERR 0x11 /* Exchange error */
3555#define RJT_PROT_ERR 0x12 /* Protocol error */
3556#define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3557#define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3558#define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3559#define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3560#define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3561#define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3562#define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3563#define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3564
3565#define IOERR_SUCCESS 0x00 /* statLocalError */
3566#define IOERR_MISSING_CONTINUE 0x01
3567#define IOERR_SEQUENCE_TIMEOUT 0x02
3568#define IOERR_INTERNAL_ERROR 0x03
3569#define IOERR_INVALID_RPI 0x04
3570#define IOERR_NO_XRI 0x05
3571#define IOERR_ILLEGAL_COMMAND 0x06
3572#define IOERR_XCHG_DROPPED 0x07
3573#define IOERR_ILLEGAL_FIELD 0x08
3574#define IOERR_BAD_CONTINUE 0x09
3575#define IOERR_TOO_MANY_BUFFERS 0x0A
3576#define IOERR_RCV_BUFFER_WAITING 0x0B
3577#define IOERR_NO_CONNECTION 0x0C
3578#define IOERR_TX_DMA_FAILED 0x0D
3579#define IOERR_RX_DMA_FAILED 0x0E
3580#define IOERR_ILLEGAL_FRAME 0x0F
3581#define IOERR_EXTRA_DATA 0x10
3582#define IOERR_NO_RESOURCES 0x11
3583#define IOERR_RESERVED 0x12
3584#define IOERR_ILLEGAL_LENGTH 0x13
3585#define IOERR_UNSUPPORTED_FEATURE 0x14
3586#define IOERR_ABORT_IN_PROGRESS 0x15
3587#define IOERR_ABORT_REQUESTED 0x16
3588#define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3589#define IOERR_LOOP_OPEN_FAILURE 0x18
3590#define IOERR_RING_RESET 0x19
3591#define IOERR_LINK_DOWN 0x1A
3592#define IOERR_CORRUPTED_DATA 0x1B
3593#define IOERR_CORRUPTED_RPI 0x1C
3594#define IOERR_OUT_OF_ORDER_DATA 0x1D
3595#define IOERR_OUT_OF_ORDER_ACK 0x1E
3596#define IOERR_DUP_FRAME 0x1F
3597#define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3598#define IOERR_BAD_HOST_ADDRESS 0x21
3599#define IOERR_RCV_HDRBUF_WAITING 0x22
3600#define IOERR_MISSING_HDR_BUFFER 0x23
3601#define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3602#define IOERR_ABORTMULT_REQUESTED 0x25
3603#define IOERR_BUFFER_SHORTAGE 0x28
3604#define IOERR_DEFAULT 0x29
3605#define IOERR_CNT 0x2A
3606#define IOERR_SLER_FAILURE 0x46
3607#define IOERR_SLER_CMD_RCV_FAILURE 0x47
3608#define IOERR_SLER_REC_RJT_ERR 0x48
3609#define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3610#define IOERR_SLER_SRR_RJT_ERR 0x4A
3611#define IOERR_SLER_RRQ_RJT_ERR 0x4C
3612#define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3613#define IOERR_SLER_ABTS_ERR 0x4E
3614#define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3615#define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3616#define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3617#define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3618#define IOERR_DRVR_MASK 0x100
3619#define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3620#define IOERR_SLI_BRESET 0x102
3621#define IOERR_SLI_ABORTED 0x103
3622#define IOERR_PARAM_MASK 0x1ff
3623} PARM_ERR;
3624
3625typedef union {
3626 struct {
3627#ifdef __BIG_ENDIAN_BITFIELD
3628 uint8_t Rctl; /* R_CTL field */
3629 uint8_t Type; /* TYPE field */
3630 uint8_t Dfctl; /* DF_CTL field */
3631 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3632#else /* __LITTLE_ENDIAN_BITFIELD */
3633 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3634 uint8_t Dfctl; /* DF_CTL field */
3635 uint8_t Type; /* TYPE field */
3636 uint8_t Rctl; /* R_CTL field */
3637#endif
3638
3639#define BC 0x02 /* Broadcast Received - Fctl */
3640#define SI 0x04 /* Sequence Initiative */
3641#define LA 0x08 /* Ignore Link Attention state */
3642#define LS 0x80 /* Last Sequence */
3643 } hcsw;
3644 uint32_t reserved;
3645} WORD5;
3646
3647/* IOCB Command template for a generic response */
3648typedef struct {
3649 uint32_t reserved[4];
3650 PARM_ERR perr;
3651} GENERIC_RSP;
3652
3653/* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3654typedef struct {
3655 struct ulp_bde xrsqbde[2];
3656 uint32_t xrsqRo; /* Starting Relative Offset */
3657 WORD5 w5; /* Header control/status word */
3658} XR_SEQ_FIELDS;
3659
3660/* IOCB Command template for ELS_REQUEST */
3661typedef struct {
3662 struct ulp_bde elsReq;
3663 struct ulp_bde elsRsp;
3664
3665#ifdef __BIG_ENDIAN_BITFIELD
3666 uint32_t word4Rsvd:7;
3667 uint32_t fl:1;
3668 uint32_t myID:24;
3669 uint32_t word5Rsvd:8;
3670 uint32_t remoteID:24;
3671#else /* __LITTLE_ENDIAN_BITFIELD */
3672 uint32_t myID:24;
3673 uint32_t fl:1;
3674 uint32_t word4Rsvd:7;
3675 uint32_t remoteID:24;
3676 uint32_t word5Rsvd:8;
3677#endif
3678} ELS_REQUEST;
3679
3680/* IOCB Command template for RCV_ELS_REQ */
3681typedef struct {
3682 struct ulp_bde elsReq[2];
3683 uint32_t parmRo;
3684
3685#ifdef __BIG_ENDIAN_BITFIELD
3686 uint32_t word5Rsvd:8;
3687 uint32_t remoteID:24;
3688#else /* __LITTLE_ENDIAN_BITFIELD */
3689 uint32_t remoteID:24;
3690 uint32_t word5Rsvd:8;
3691#endif
3692} RCV_ELS_REQ;
3693
3694/* IOCB Command template for ABORT / CLOSE_XRI */
3695typedef struct {
3696 uint32_t rsvd[3];
3697 uint32_t abortType;
3698#define ABORT_TYPE_ABTX 0x00000000
3699#define ABORT_TYPE_ABTS 0x00000001
3700 uint32_t parm;
3701#ifdef __BIG_ENDIAN_BITFIELD
3702 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3703 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3704#else /* __LITTLE_ENDIAN_BITFIELD */
3705 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3706 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3707#endif
3708} AC_XRI;
3709
3710/* IOCB Command template for ABORT_MXRI64 */
3711typedef struct {
3712 uint32_t rsvd[3];
3713 uint32_t abortType;
3714 uint32_t parm;
3715 uint32_t iotag32;
3716} A_MXRI64;
3717
3718/* IOCB Command template for GET_RPI */
3719typedef struct {
3720 uint32_t rsvd[4];
3721 uint32_t parmRo;
3722#ifdef __BIG_ENDIAN_BITFIELD
3723 uint32_t word5Rsvd:8;
3724 uint32_t remoteID:24;
3725#else /* __LITTLE_ENDIAN_BITFIELD */
3726 uint32_t remoteID:24;
3727 uint32_t word5Rsvd:8;
3728#endif
3729} GET_RPI;
3730
3731/* IOCB Command template for all FCP Initiator commands */
3732typedef struct {
3733 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3734 struct ulp_bde fcpi_rsp; /* Rcv buffer */
3735 uint32_t fcpi_parm;
3736 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3737} FCPI_FIELDS;
3738
3739/* IOCB Command template for all FCP Target commands */
3740typedef struct {
3741 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3742 uint32_t fcpt_Offset;
3743 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3744} FCPT_FIELDS;
3745
3746/* SLI-2 IOCB structure definitions */
3747
3748/* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3749typedef struct {
3750 ULP_BDL bdl;
3751 uint32_t xrsqRo; /* Starting Relative Offset */
3752 WORD5 w5; /* Header control/status word */
3753} XMT_SEQ_FIELDS64;
3754
3755/* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3756#define xmit_els_remoteID xrsqRo
3757
3758/* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3759typedef struct {
3760 struct ulp_bde64 rcvBde;
3761 uint32_t rsvd1;
3762 uint32_t xrsqRo; /* Starting Relative Offset */
3763 WORD5 w5; /* Header control/status word */
3764} RCV_SEQ_FIELDS64;
3765
3766/* IOCB Command template for ELS_REQUEST64 */
3767typedef struct {
3768 ULP_BDL bdl;
3769#ifdef __BIG_ENDIAN_BITFIELD
3770 uint32_t word4Rsvd:7;
3771 uint32_t fl:1;
3772 uint32_t myID:24;
3773 uint32_t word5Rsvd:8;
3774 uint32_t remoteID:24;
3775#else /* __LITTLE_ENDIAN_BITFIELD */
3776 uint32_t myID:24;
3777 uint32_t fl:1;
3778 uint32_t word4Rsvd:7;
3779 uint32_t remoteID:24;
3780 uint32_t word5Rsvd:8;
3781#endif
3782} ELS_REQUEST64;
3783
3784/* IOCB Command template for GEN_REQUEST64 */
3785typedef struct {
3786 ULP_BDL bdl;
3787 uint32_t xrsqRo; /* Starting Relative Offset */
3788 WORD5 w5; /* Header control/status word */
3789} GEN_REQUEST64;
3790
3791/* IOCB Command template for RCV_ELS_REQ64 */
3792typedef struct {
3793 struct ulp_bde64 elsReq;
3794 uint32_t rcvd1;
3795 uint32_t parmRo;
3796
3797#ifdef __BIG_ENDIAN_BITFIELD
3798 uint32_t word5Rsvd:8;
3799 uint32_t remoteID:24;
3800#else /* __LITTLE_ENDIAN_BITFIELD */
3801 uint32_t remoteID:24;
3802 uint32_t word5Rsvd:8;
3803#endif
3804} RCV_ELS_REQ64;
3805
3806/* IOCB Command template for RCV_SEQ64 */
3807struct rcv_seq64 {
3808 struct ulp_bde64 elsReq;
3809 uint32_t hbq_1;
3810 uint32_t parmRo;
3811#ifdef __BIG_ENDIAN_BITFIELD
3812 uint32_t rctl:8;
3813 uint32_t type:8;
3814 uint32_t dfctl:8;
3815 uint32_t ls:1;
3816 uint32_t fs:1;
3817 uint32_t rsvd2:3;
3818 uint32_t si:1;
3819 uint32_t bc:1;
3820 uint32_t rsvd3:1;
3821#else /* __LITTLE_ENDIAN_BITFIELD */
3822 uint32_t rsvd3:1;
3823 uint32_t bc:1;
3824 uint32_t si:1;
3825 uint32_t rsvd2:3;
3826 uint32_t fs:1;
3827 uint32_t ls:1;
3828 uint32_t dfctl:8;
3829 uint32_t type:8;
3830 uint32_t rctl:8;
3831#endif
3832};
3833
3834/* IOCB Command template for all 64 bit FCP Initiator commands */
3835typedef struct {
3836 ULP_BDL bdl;
3837 uint32_t fcpi_parm;
3838 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3839} FCPI_FIELDS64;
3840
3841/* IOCB Command template for all 64 bit FCP Target commands */
3842typedef struct {
3843 ULP_BDL bdl;
3844 uint32_t fcpt_Offset;
3845 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3846} FCPT_FIELDS64;
3847
3848/* IOCB Command template for Async Status iocb commands */
3849typedef struct {
3850 uint32_t rsvd[4];
3851 uint32_t param;
3852#ifdef __BIG_ENDIAN_BITFIELD
3853 uint16_t evt_code; /* High order bits word 5 */
3854 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3855#else /* __LITTLE_ENDIAN_BITFIELD */
3856 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3857 uint16_t evt_code; /* Low order bits word 5 */
3858#endif
3859} ASYNCSTAT_FIELDS;
3860#define ASYNC_TEMP_WARN 0x100
3861#define ASYNC_TEMP_SAFE 0x101
3862#define ASYNC_STATUS_CN 0x102
3863
3864/* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3865 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3866
3867struct rcv_sli3 {
3868#ifdef __BIG_ENDIAN_BITFIELD
3869 uint16_t ox_id;
3870 uint16_t seq_cnt;
3871
3872 uint16_t vpi;
3873 uint16_t word9Rsvd;
3874#else /* __LITTLE_ENDIAN */
3875 uint16_t seq_cnt;
3876 uint16_t ox_id;
3877
3878 uint16_t word9Rsvd;
3879 uint16_t vpi;
3880#endif
3881 uint32_t word10Rsvd;
3882 uint32_t acc_len; /* accumulated length */
3883 struct ulp_bde64 bde2;
3884};
3885
3886/* Structure used for a single HBQ entry */
3887struct lpfc_hbq_entry {
3888 struct ulp_bde64 bde;
3889 uint32_t buffer_tag;
3890};
3891
3892/* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3893typedef struct {
3894 struct lpfc_hbq_entry buff;
3895 uint32_t rsvd;
3896 uint32_t rsvd1;
3897} QUE_XRI64_CX_FIELDS;
3898
3899struct que_xri64cx_ext_fields {
3900 uint32_t iotag64_low;
3901 uint32_t iotag64_high;
3902 uint32_t ebde_count;
3903 uint32_t rsvd;
3904 struct lpfc_hbq_entry buff[5];
3905};
3906
3907struct sli3_bg_fields {
3908 uint32_t filler[6]; /* word 8-13 in IOCB */
3909 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
3910/* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3911#define BGS_BIDIR_BG_PROF_MASK 0xff000000
3912#define BGS_BIDIR_BG_PROF_SHIFT 24
3913#define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3914#define BGS_BIDIR_ERR_COND_SHIFT 16
3915#define BGS_BG_PROFILE_MASK 0x0000ff00
3916#define BGS_BG_PROFILE_SHIFT 8
3917#define BGS_INVALID_PROF_MASK 0x00000020
3918#define BGS_INVALID_PROF_SHIFT 5
3919#define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3920#define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3921#define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3922#define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3923#define BGS_REFTAG_ERR_MASK 0x00000004
3924#define BGS_REFTAG_ERR_SHIFT 2
3925#define BGS_APPTAG_ERR_MASK 0x00000002
3926#define BGS_APPTAG_ERR_SHIFT 1
3927#define BGS_GUARD_ERR_MASK 0x00000001
3928#define BGS_GUARD_ERR_SHIFT 0
3929 uint32_t bgstat; /* word 15 - BlockGuard Status */
3930};
3931
3932static inline uint32_t
3933lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3934{
3935 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
3936 BGS_BIDIR_BG_PROF_SHIFT;
3937}
3938
3939static inline uint32_t
3940lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3941{
3942 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3943 BGS_BIDIR_ERR_COND_SHIFT;
3944}
3945
3946static inline uint32_t
3947lpfc_bgs_get_bg_prof(uint32_t bgstat)
3948{
3949 return (bgstat & BGS_BG_PROFILE_MASK) >>
3950 BGS_BG_PROFILE_SHIFT;
3951}
3952
3953static inline uint32_t
3954lpfc_bgs_get_invalid_prof(uint32_t bgstat)
3955{
3956 return (bgstat & BGS_INVALID_PROF_MASK) >>
3957 BGS_INVALID_PROF_SHIFT;
3958}
3959
3960static inline uint32_t
3961lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
3962{
3963 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
3964 BGS_UNINIT_DIF_BLOCK_SHIFT;
3965}
3966
3967static inline uint32_t
3968lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
3969{
3970 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
3971 BGS_HI_WATER_MARK_PRESENT_SHIFT;
3972}
3973
3974static inline uint32_t
3975lpfc_bgs_get_reftag_err(uint32_t bgstat)
3976{
3977 return (bgstat & BGS_REFTAG_ERR_MASK) >>
3978 BGS_REFTAG_ERR_SHIFT;
3979}
3980
3981static inline uint32_t
3982lpfc_bgs_get_apptag_err(uint32_t bgstat)
3983{
3984 return (bgstat & BGS_APPTAG_ERR_MASK) >>
3985 BGS_APPTAG_ERR_SHIFT;
3986}
3987
3988static inline uint32_t
3989lpfc_bgs_get_guard_err(uint32_t bgstat)
3990{
3991 return (bgstat & BGS_GUARD_ERR_MASK) >>
3992 BGS_GUARD_ERR_SHIFT;
3993}
3994
3995#define LPFC_EXT_DATA_BDE_COUNT 3
3996struct fcp_irw_ext {
3997 uint32_t io_tag64_low;
3998 uint32_t io_tag64_high;
3999#ifdef __BIG_ENDIAN_BITFIELD
4000 uint8_t reserved1;
4001 uint8_t reserved2;
4002 uint8_t reserved3;
4003 uint8_t ebde_count;
4004#else /* __LITTLE_ENDIAN */
4005 uint8_t ebde_count;
4006 uint8_t reserved3;
4007 uint8_t reserved2;
4008 uint8_t reserved1;
4009#endif
4010 uint32_t reserved4;
4011 struct ulp_bde64 rbde; /* response bde */
4012 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
4013 uint8_t icd[32]; /* immediate command data (32 bytes) */
4014};
4015
4016typedef struct _IOCB { /* IOCB structure */
4017 union {
4018 GENERIC_RSP grsp; /* Generic response */
4019 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
4020 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
4021 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
4022 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
4023 A_MXRI64 amxri; /* abort multiple xri command overlay */
4024 GET_RPI getrpi; /* GET_RPI template */
4025 FCPI_FIELDS fcpi; /* FCP Initiator template */
4026 FCPT_FIELDS fcpt; /* FCP target template */
4027
4028 /* SLI-2 structures */
4029
4030 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
4031 * bde_64s */
4032 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
4033 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
4034 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
4035 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
4036 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
4037 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
4038 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
4039 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
4040 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
4041 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
4042 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
4043 } un;
4044 union {
4045 struct {
4046#ifdef __BIG_ENDIAN_BITFIELD
4047 uint16_t ulpContext; /* High order bits word 6 */
4048 uint16_t ulpIoTag; /* Low order bits word 6 */
4049#else /* __LITTLE_ENDIAN_BITFIELD */
4050 uint16_t ulpIoTag; /* Low order bits word 6 */
4051 uint16_t ulpContext; /* High order bits word 6 */
4052#endif
4053 } t1;
4054 struct {
4055#ifdef __BIG_ENDIAN_BITFIELD
4056 uint16_t ulpContext; /* High order bits word 6 */
4057 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4058 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4059#else /* __LITTLE_ENDIAN_BITFIELD */
4060 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4061 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4062 uint16_t ulpContext; /* High order bits word 6 */
4063#endif
4064 } t2;
4065 } un1;
4066#define ulpContext un1.t1.ulpContext
4067#define ulpIoTag un1.t1.ulpIoTag
4068#define ulpIoTag0 un1.t2.ulpIoTag0
4069
4070#ifdef __BIG_ENDIAN_BITFIELD
4071 uint32_t ulpTimeout:8;
4072 uint32_t ulpXS:1;
4073 uint32_t ulpFCP2Rcvy:1;
4074 uint32_t ulpPU:2;
4075 uint32_t ulpIr:1;
4076 uint32_t ulpClass:3;
4077 uint32_t ulpCommand:8;
4078 uint32_t ulpStatus:4;
4079 uint32_t ulpBdeCount:2;
4080 uint32_t ulpLe:1;
4081 uint32_t ulpOwner:1; /* Low order bit word 7 */
4082#else /* __LITTLE_ENDIAN_BITFIELD */
4083 uint32_t ulpOwner:1; /* Low order bit word 7 */
4084 uint32_t ulpLe:1;
4085 uint32_t ulpBdeCount:2;
4086 uint32_t ulpStatus:4;
4087 uint32_t ulpCommand:8;
4088 uint32_t ulpClass:3;
4089 uint32_t ulpIr:1;
4090 uint32_t ulpPU:2;
4091 uint32_t ulpFCP2Rcvy:1;
4092 uint32_t ulpXS:1;
4093 uint32_t ulpTimeout:8;
4094#endif
4095
4096 union {
4097 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
4098
4099 /* words 8-31 used for que_xri_cx iocb */
4100 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4101 struct fcp_irw_ext fcp_ext;
4102 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
4103
4104 /* words 8-15 for BlockGuard */
4105 struct sli3_bg_fields sli3_bg;
4106 } unsli3;
4107
4108#define ulpCt_h ulpXS
4109#define ulpCt_l ulpFCP2Rcvy
4110
4111#define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
4112#define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
4113#define PARM_UNUSED 0 /* PU field (Word 4) not used */
4114#define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
4115#define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
4116#define PARM_NPIV_DID 3
4117#define CLASS1 0 /* Class 1 */
4118#define CLASS2 1 /* Class 2 */
4119#define CLASS3 2 /* Class 3 */
4120#define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
4121
4122#define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
4123#define IOSTAT_FCP_RSP_ERROR 0x1
4124#define IOSTAT_REMOTE_STOP 0x2
4125#define IOSTAT_LOCAL_REJECT 0x3
4126#define IOSTAT_NPORT_RJT 0x4
4127#define IOSTAT_FABRIC_RJT 0x5
4128#define IOSTAT_NPORT_BSY 0x6
4129#define IOSTAT_FABRIC_BSY 0x7
4130#define IOSTAT_INTERMED_RSP 0x8
4131#define IOSTAT_LS_RJT 0x9
4132#define IOSTAT_BA_RJT 0xA
4133#define IOSTAT_RSVD1 0xB
4134#define IOSTAT_RSVD2 0xC
4135#define IOSTAT_RSVD3 0xD
4136#define IOSTAT_RSVD4 0xE
4137#define IOSTAT_NEED_BUFFER 0xF
4138#define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
4139#define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
4140#define IOSTAT_CNT 0x11
4141
4142} IOCB_t;
4143
4144
4145#define SLI1_SLIM_SIZE (4 * 1024)
4146
4147/* Up to 498 IOCBs will fit into 16k
4148 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
4149 */
4150#define SLI2_SLIM_SIZE (64 * 1024)
4151
4152/* Maximum IOCBs that will fit in SLI2 slim */
4153#define MAX_SLI2_IOCB 498
4154#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4155 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4156 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4157
4158/* HBQ entries are 4 words each = 4k */
4159#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
4160 lpfc_sli_hbq_count())
4161
4162struct lpfc_sli2_slim {
4163 MAILBOX_t mbx;
4164 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
4165 PCB_t pcb;
4166 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4167};
4168
4169/*
4170 * This function checks PCI device to allow special handling for LC HBAs.
4171 *
4172 * Parameters:
4173 * device : struct pci_dev 's device field
4174 *
4175 * return 1 => TRUE
4176 * 0 => FALSE
4177 */
4178static inline int
4179lpfc_is_LC_HBA(unsigned short device)
4180{
4181 if ((device == PCI_DEVICE_ID_TFLY) ||
4182 (device == PCI_DEVICE_ID_PFLY) ||
4183 (device == PCI_DEVICE_ID_LP101) ||
4184 (device == PCI_DEVICE_ID_BMID) ||
4185 (device == PCI_DEVICE_ID_BSMB) ||
4186 (device == PCI_DEVICE_ID_ZMID) ||
4187 (device == PCI_DEVICE_ID_ZSMB) ||
4188 (device == PCI_DEVICE_ID_SAT_MID) ||
4189 (device == PCI_DEVICE_ID_SAT_SMB) ||
4190 (device == PCI_DEVICE_ID_RFLY))
4191 return 1;
4192 else
4193 return 0;
4194}
4195
4196/*
4197 * Determine if an IOCB failed because of a link event or firmware reset.
4198 */
4199
4200static inline int
4201lpfc_error_lost_link(IOCB_t *iocbp)
4202{
4203 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
4204 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
4205 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
4206 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
4207}
4208
4209#define MENLO_TRANSPORT_TYPE 0xfe
4210#define MENLO_CONTEXT 0
4211#define MENLO_PU 3
4212#define MENLO_TIMEOUT 30
4213#define SETVAR_MLOMNT 0x103107
4214#define SETVAR_MLORST 0x103007
4215
4216#define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */