tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * Copyright 2014-2016 Toradex AG
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
14 *
15 * This file is distributed in the hope that it will be useful
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include <dt-bindings/gpio/gpio.h>
45
46/ {
47 model = "Toradex Apalis iMX6Q/D Module";
48 compatible = "toradex,apalis_imx6q", "fsl,imx6q";
49
50 backlight: backlight {
51 compatible = "pwm-backlight";
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_gpio_bl_on>;
54 pwms = <&pwm4 0 5000000>;
55 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
56 status = "disabled";
57 };
58
59 /* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */
60 i2cddc: i2c@0 {
61 compatible = "i2c-gpio";
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_i2c_ddc>;
64 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */
65 &gpio2 30 GPIO_ACTIVE_HIGH /* scl */
66 >;
67 i2c-gpio,delay-us = <2>; /* ~100 kHz */
68 status = "disabled";
69 };
70
71 reg_1p8v: regulator-1p8v {
72 compatible = "regulator-fixed";
73 regulator-name = "1P8V";
74 regulator-min-microvolt = <1800000>;
75 regulator-max-microvolt = <1800000>;
76 regulator-always-on;
77 };
78
79 reg_2p5v: regulator-2p5v {
80 compatible = "regulator-fixed";
81 regulator-name = "2P5V";
82 regulator-min-microvolt = <2500000>;
83 regulator-max-microvolt = <2500000>;
84 regulator-always-on;
85 };
86
87 reg_3p3v: regulator-3p3v {
88 compatible = "regulator-fixed";
89 regulator-name = "3P3V";
90 regulator-min-microvolt = <3300000>;
91 regulator-max-microvolt = <3300000>;
92 regulator-always-on;
93 };
94
95 reg_usb_otg_vbus: regulator-usb-otg-vbus {
96 compatible = "regulator-fixed";
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
99 regulator-name = "usb_otg_vbus";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
103 enable-active-high;
104 status = "disabled";
105 };
106
107 /* on module USB hub */
108 reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
109 compatible = "regulator-fixed";
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
112 regulator-name = "usb_host_vbus_hub";
113 regulator-min-microvolt = <5000000>;
114 regulator-max-microvolt = <5000000>;
115 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
116 startup-delay-us = <2000>;
117 enable-active-high;
118 status = "okay";
119 };
120
121 reg_usb_host_vbus: regulator-usb-host-vbus {
122 compatible = "regulator-fixed";
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
125 regulator-name = "usb_host_vbus";
126 regulator-min-microvolt = <5000000>;
127 regulator-max-microvolt = <5000000>;
128 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
129 enable-active-high;
130 vin-supply = <®_usb_host_vbus_hub>;
131 status = "disabled";
132 };
133
134 sound {
135 compatible = "fsl,imx-audio-sgtl5000";
136 model = "imx6q-apalis-sgtl5000";
137 ssi-controller = <&ssi1>;
138 audio-codec = <&codec>;
139 audio-routing =
140 "LINE_IN", "Line In Jack",
141 "MIC_IN", "Mic Jack",
142 "Mic Jack", "Mic Bias",
143 "Headphone Jack", "HP_OUT";
144 mux-int-port = <1>;
145 mux-ext-port = <4>;
146 };
147
148 sound_spdif: sound-spdif {
149 compatible = "fsl,imx-audio-spdif";
150 model = "imx-spdif";
151 spdif-controller = <&spdif>;
152 spdif-in;
153 spdif-out;
154 status = "disabled";
155 };
156};
157
158&audmux {
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_audmux>;
161 status = "okay";
162};
163
164&can1 {
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_flexcan1>;
167 status = "disabled";
168};
169
170&can2 {
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_flexcan2>;
173 status = "disabled";
174};
175
176/* Apalis SPI1 */
177&ecspi1 {
178 fsl,spi-num-chipselects = <1>;
179 cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_ecspi1>;
182 status = "disabled";
183};
184
185/* Apalis SPI2 */
186&ecspi2 {
187 fsl,spi-num-chipselects = <1>;
188 cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_ecspi2>;
191 status = "disabled";
192};
193
194&fec {
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_enet>;
197 phy-mode = "rgmii";
198 phy-handle = <ðphy>;
199 phy-reset-duration = <10>;
200 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
201 status = "okay";
202
203 mdio {
204 #address-cells = <1>;
205 #size-cells = <0>;
206
207 ethphy: ethernet-phy@7 {
208 interrupt-parent = <&gpio1>;
209 interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
210 reg = <7>;
211 };
212 };
213};
214
215/*
216 * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
217 * board)
218 */
219&i2c1 {
220 clock-frequency = <100000>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_i2c1>;
223 status = "disabled";
224};
225
226/*
227 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
228 * touch screen controller
229 */
230&i2c2 {
231 clock-frequency = <100000>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_i2c2>;
234 status = "okay";
235
236 pmic: pfuze100@08 {
237 compatible = "fsl,pfuze100";
238 reg = <0x08>;
239
240 regulators {
241 sw1a_reg: sw1ab {
242 regulator-min-microvolt = <300000>;
243 regulator-max-microvolt = <1875000>;
244 regulator-boot-on;
245 regulator-always-on;
246 regulator-ramp-delay = <6250>;
247 };
248
249 sw1c_reg: sw1c {
250 regulator-min-microvolt = <300000>;
251 regulator-max-microvolt = <1875000>;
252 regulator-boot-on;
253 regulator-always-on;
254 regulator-ramp-delay = <6250>;
255 };
256
257 sw3a_reg: sw3a {
258 regulator-min-microvolt = <400000>;
259 regulator-max-microvolt = <1975000>;
260 regulator-boot-on;
261 regulator-always-on;
262 };
263
264 swbst_reg: swbst {
265 regulator-min-microvolt = <5000000>;
266 regulator-max-microvolt = <5150000>;
267 regulator-boot-on;
268 regulator-always-on;
269 };
270
271 snvs_reg: vsnvs {
272 regulator-min-microvolt = <1000000>;
273 regulator-max-microvolt = <3000000>;
274 regulator-boot-on;
275 regulator-always-on;
276 };
277
278 vref_reg: vrefddr {
279 regulator-boot-on;
280 regulator-always-on;
281 };
282
283 vgen1_reg: vgen1 {
284 regulator-min-microvolt = <800000>;
285 regulator-max-microvolt = <1550000>;
286 regulator-boot-on;
287 regulator-always-on;
288 };
289
290 vgen2_reg: vgen2 {
291 regulator-min-microvolt = <800000>;
292 regulator-max-microvolt = <1550000>;
293 regulator-boot-on;
294 regulator-always-on;
295 };
296
297 vgen3_reg: vgen3 {
298 regulator-min-microvolt = <1800000>;
299 regulator-max-microvolt = <3300000>;
300 regulator-boot-on;
301 regulator-always-on;
302 };
303
304 vgen4_reg: vgen4 {
305 regulator-min-microvolt = <1800000>;
306 regulator-max-microvolt = <3300000>;
307 regulator-boot-on;
308 regulator-always-on;
309 };
310
311 vgen5_reg: vgen5 {
312 regulator-min-microvolt = <1800000>;
313 regulator-max-microvolt = <3300000>;
314 regulator-boot-on;
315 regulator-always-on;
316 };
317
318 vgen6_reg: vgen6 {
319 regulator-min-microvolt = <1800000>;
320 regulator-max-microvolt = <3300000>;
321 regulator-boot-on;
322 regulator-always-on;
323 };
324 };
325 };
326
327 codec: sgtl5000@0a {
328 compatible = "fsl,sgtl5000";
329 reg = <0x0a>;
330 clocks = <&clks IMX6QDL_CLK_CKO>;
331 VDDA-supply = <®_2p5v>;
332 VDDIO-supply = <®_3p3v>;
333 };
334
335 /* STMPE811 touch screen controller */
336 stmpe811@41 {
337 compatible = "st,stmpe811";
338 pinctrl-names = "default";
339 pinctrl-0 = <&pinctrl_touch_int>;
340 #address-cells = <1>;
341 #size-cells = <0>;
342 reg = <0x41>;
343 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
344 interrupt-parent = <&gpio4>;
345 interrupt-controller;
346 id = <0>;
347 blocks = <0x5>;
348 irq-trigger = <0x1>;
349
350 stmpe_touchscreen {
351 compatible = "st,stmpe-ts";
352 reg = <0>;
353 /* 3.25 MHz ADC clock speed */
354 st,adc-freq = <1>;
355 /* 8 sample average control */
356 st,ave-ctrl = <3>;
357 /* 7 length fractional part in z */
358 st,fraction-z = <7>;
359 /*
360 * 50 mA typical 80 mA max touchscreen drivers
361 * current limit value
362 */
363 st,i-drive = <1>;
364 /* 12-bit ADC */
365 st,mod-12b = <1>;
366 /* internal ADC reference */
367 st,ref-sel = <0>;
368 /* ADC converstion time: 80 clocks */
369 st,sample-time = <4>;
370 /* 1 ms panel driver settling time */
371 st,settling = <3>;
372 /* 5 ms touch detect interrupt delay */
373 st,touch-det-delay = <5>;
374 };
375 };
376};
377
378/*
379 * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused)
380 */
381&i2c3 {
382 clock-frequency = <100000>;
383 pinctrl-names = "default", "recovery";
384 pinctrl-0 = <&pinctrl_i2c3>;
385 pinctrl-1 = <&pinctrl_i2c3_recovery>;
386 scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
387 sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
388 status = "disabled";
389};
390
391&pwm1 {
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_pwm1>;
394 status = "disabled";
395};
396
397&pwm2 {
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_pwm2>;
400 status = "disabled";
401};
402
403&pwm3 {
404 pinctrl-names = "default";
405 pinctrl-0 = <&pinctrl_pwm3>;
406 status = "disabled";
407};
408
409&pwm4 {
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_pwm4>;
412 status = "disabled";
413};
414
415&spdif {
416 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_spdif>;
418 status = "disabled";
419};
420
421&ssi1 {
422 status = "okay";
423};
424
425&uart1 {
426 pinctrl-names = "default";
427 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
428 fsl,dte-mode;
429 uart-has-rtscts;
430 status = "disabled";
431};
432
433&uart2 {
434 pinctrl-names = "default";
435 pinctrl-0 = <&pinctrl_uart2_dte>;
436 fsl,dte-mode;
437 uart-has-rtscts;
438 status = "disabled";
439};
440
441&uart4 {
442 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_uart4_dte>;
444 fsl,dte-mode;
445 status = "disabled";
446};
447
448&uart5 {
449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_uart5_dte>;
451 fsl,dte-mode;
452 status = "disabled";
453};
454
455&usbotg {
456 pinctrl-names = "default";
457 pinctrl-0 = <&pinctrl_usbotg>;
458 disable-over-current;
459 status = "disabled";
460};
461
462/* MMC1 */
463&usdhc1 {
464 pinctrl-names = "default";
465 pinctrl-0 = <&pinctrl_usdhc1>;
466 vqmmc-supply = <®_3p3v>;
467 bus-width = <8>;
468 voltage-ranges = <3300 3300>;
469 status = "disabled";
470};
471
472/* SD1 */
473&usdhc2 {
474 pinctrl-names = "default";
475 pinctrl-0 = <&pinctrl_usdhc2>;
476 vqmmc-supply = <®_3p3v>;
477 bus-width = <4>;
478 voltage-ranges = <3300 3300>;
479 status = "disabled";
480};
481
482/* eMMC */
483&usdhc3 {
484 pinctrl-names = "default";
485 pinctrl-0 = <&pinctrl_usdhc3>;
486 vqmmc-supply = <®_3p3v>;
487 bus-width = <8>;
488 voltage-ranges = <3300 3300>;
489 non-removable;
490 status = "okay";
491};
492
493&weim {
494 status = "disabled";
495};
496
497&iomuxc {
498 /* pins used on module */
499 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_reset_moci>;
501
502 pinctrl_apalis_gpio1: gpio2io04grp {
503 fsl,pins = <
504 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
505 >;
506 };
507
508 pinctrl_apalis_gpio2: gpio2io05grp {
509 fsl,pins = <
510 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
511 >;
512 };
513
514 pinctrl_apalis_gpio3: gpio2io06grp {
515 fsl,pins = <
516 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
517 >;
518 };
519
520 pinctrl_apalis_gpio4: gpio2io07grp {
521 fsl,pins = <
522 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
523 >;
524 };
525
526 pinctrl_apalis_gpio5: gpio6io10grp {
527 fsl,pins = <
528 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
529 >;
530 };
531
532 pinctrl_apalis_gpio6: gpio6io09grp {
533 fsl,pins = <
534 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
535 >;
536 };
537
538 pinctrl_apalis_gpio7: gpio1io02grp {
539 fsl,pins = <
540 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
541 >;
542 };
543
544 pinctrl_apalis_gpio8: gpio1io06grp {
545 fsl,pins = <
546 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
547 >;
548 };
549
550 pinctrl_audmux: audmuxgrp {
551 fsl,pins = <
552 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
553 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
554 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
555 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
556 /* SGTL5000 sys_mclk */
557 MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
558 >;
559 };
560
561 pinctrl_cam_mclk: cammclkgrp {
562 fsl,pins = <
563 /* CAM sys_mclk */
564 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
565 >;
566 };
567
568 pinctrl_ecspi1: ecspi1grp {
569 fsl,pins = <
570 MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
571 MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
572 MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
573 /* SPI1 cs */
574 MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
575 >;
576 };
577
578 pinctrl_ecspi2: ecspi2grp {
579 fsl,pins = <
580 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
581 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
582 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
583 /* SPI2 cs */
584 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
585 >;
586 };
587
588 pinctrl_enet: enetgrp {
589 fsl,pins = <
590 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
591 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
592 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
593 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
594 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
595 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
596 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
597 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
598 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
599 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
600 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
601 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
602 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
603 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
604 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
605 /* Ethernet PHY reset */
606 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
607 /* Ethernet PHY interrupt */
608 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1
609 >;
610 };
611
612 pinctrl_flexcan1: flexcan1grp {
613 fsl,pins = <
614 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
615 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
616 >;
617 };
618
619 pinctrl_flexcan2: flexcan2grp {
620 fsl,pins = <
621 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
622 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
623 >;
624 };
625
626 pinctrl_gpio_bl_on: gpioblon {
627 fsl,pins = <
628 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
629 >;
630 };
631
632 pinctrl_gpio_keys: gpio1io04grp {
633 fsl,pins = <
634 /* Power button */
635 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
636 >;
637 };
638
639 pinctrl_hdmi_cec: hdmicecgrp {
640 fsl,pins = <
641 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
642 >;
643 };
644
645 pinctrl_i2c_ddc: gpioi2cddcgrp {
646 fsl,pins = <
647 /* DDC bitbang */
648 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
649 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0
650 >;
651 };
652
653 pinctrl_i2c1: i2c1grp {
654 fsl,pins = <
655 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
656 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
657 >;
658 };
659
660 pinctrl_i2c2: i2c2grp {
661 fsl,pins = <
662 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
663 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
664 >;
665 };
666
667 pinctrl_i2c3: i2c3grp {
668 fsl,pins = <
669 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
670 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
671 >;
672 };
673
674 pinctrl_i2c3_recovery: i2c3recoverygrp {
675 fsl,pins = <
676 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
677 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
678 >;
679 };
680
681 pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
682 fsl,pins = <
683 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1
684 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1
685 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1
686 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1
687 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1
688 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1
689 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1
690 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1
691 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
692 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1
693 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1
694 >;
695 };
696
697 pinctrl_ipu1_lcdif: ipu1lcdifgrp {
698 fsl,pins = <
699 MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61
700 /* DE */
701 MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61
702 /* HSync */
703 MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61
704 /* VSync */
705 MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61
706 MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61
707 MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61
708 MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61
709 MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61
710 MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61
711 MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61
712 MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61
713 MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61
714 MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61
715 MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61
716 MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61
717 MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61
718 MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61
719 MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61
720 MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61
721 MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61
722 MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61
723 MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61
724 MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61
725 MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61
726 MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61
727 MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61
728 MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61
729 MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61
730 >;
731 };
732
733 pinctrl_ipu2_vdac: ipu2vdacgrp {
734 fsl,pins = <
735 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
736 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1
737 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1
738 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1
739 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9
740 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9
741 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9
742 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9
743 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9
744 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9
745 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9
746 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9
747 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9
748 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9
749 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9
750 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9
751 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9
752 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9
753 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9
754 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9
755 >;
756 };
757
758 pinctrl_mmc_cd: gpiommccdgrp {
759 fsl,pins = <
760 /* MMC1 CD */
761 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
762 >;
763 };
764
765 pinctrl_pwm1: pwm1grp {
766 fsl,pins = <
767 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
768 >;
769 };
770
771 pinctrl_pwm2: pwm2grp {
772 fsl,pins = <
773 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
774 >;
775 };
776
777 pinctrl_pwm3: pwm3grp {
778 fsl,pins = <
779 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
780 >;
781 };
782
783 pinctrl_pwm4: pwm4grp {
784 fsl,pins = <
785 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
786 >;
787 };
788
789 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
790 fsl,pins = <
791 /* USBH_EN */
792 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
793 >;
794 };
795
796 pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
797 fsl,pins = <
798 /* USBH_HUB_EN */
799 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
800 >;
801 };
802
803 pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
804 fsl,pins = <
805 /* USBO1 power en */
806 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
807 >;
808 };
809
810 pinctrl_reset_moci: gpioresetmocigrp {
811 fsl,pins = <
812 /* RESET_MOCI control */
813 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
814 >;
815 };
816
817 pinctrl_sd_cd: gpiosdcdgrp {
818 fsl,pins = <
819 /* SD1 CD */
820 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
821 >;
822 };
823
824 pinctrl_spdif: spdifgrp {
825 fsl,pins = <
826 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
827 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
828 >;
829 };
830
831 pinctrl_touch_int: gpiotouchintgrp {
832 fsl,pins = <
833 /* STMPE811 interrupt */
834 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
835 >;
836 };
837
838 pinctrl_uart1_dce: uart1dcegrp {
839 fsl,pins = <
840 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
841 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
842 >;
843 };
844
845 /* DTE mode */
846 pinctrl_uart1_dte: uart1dtegrp {
847 fsl,pins = <
848 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
849 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
850 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
851 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
852 >;
853 };
854
855 /* Additional DTR, DSR, DCD */
856 pinctrl_uart1_ctrl: uart1ctrlgrp {
857 fsl,pins = <
858 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
859 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
860 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
861 >;
862 };
863
864 pinctrl_uart2_dce: uart2dcegrp {
865 fsl,pins = <
866 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
867 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
868 >;
869 };
870
871 /* DTE mode */
872 pinctrl_uart2_dte: uart2dtegrp {
873 fsl,pins = <
874 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
875 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
876 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
877 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
878 >;
879 };
880
881 pinctrl_uart4_dce: uart4dcegrp {
882 fsl,pins = <
883 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
884 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
885 >;
886 };
887
888 /* DTE mode */
889 pinctrl_uart4_dte: uart4dtegrp {
890 fsl,pins = <
891 MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
892 MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
893 >;
894 };
895
896 pinctrl_uart5_dce: uart5dcegrp {
897 fsl,pins = <
898 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
899 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
900 >;
901 };
902
903 /* DTE mode */
904 pinctrl_uart5_dte: uart5dtegrp {
905 fsl,pins = <
906 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
907 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
908 >;
909 };
910
911 pinctrl_usbotg: usbotggrp {
912 fsl,pins = <
913 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
914 >;
915 };
916
917 pinctrl_usdhc1: usdhc1grp {
918 fsl,pins = <
919 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
920 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
921 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
922 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
923 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
924 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
925 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
926 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
927 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
928 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
929 >;
930 };
931
932 pinctrl_usdhc2: usdhc2grp {
933 fsl,pins = <
934 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
935 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
936 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
937 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
938 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
939 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
940 >;
941 };
942
943 pinctrl_usdhc3: usdhc3grp {
944 fsl,pins = <
945 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
946 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
947 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
948 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
949 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
950 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
951 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
952 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
953 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
954 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
955 /* eMMC reset */
956 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
957 >;
958 };
959
960 pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
961 fsl,pins = <
962 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
963 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
964 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
965 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
966 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
967 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
968 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
969 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
970 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
971 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
972 /* eMMC reset */
973 MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9
974 >;
975 };
976
977 pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
978 fsl,pins = <
979 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
980 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
981 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
982 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
983 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
984 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
985 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
986 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
987 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
988 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
989 /* eMMC reset */
990 MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9
991 >;
992 };
993};