tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Driver for the Texas Instruments DP83867 PHY
3 *
4 * Copyright (C) 2015 Texas Instruments Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/ethtool.h>
17#include <linux/kernel.h>
18#include <linux/mii.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/phy.h>
22
23#include <dt-bindings/net/ti-dp83867.h>
24
25#define DP83867_PHY_ID 0x2000a231
26#define DP83867_DEVADDR 0x1f
27
28#define MII_DP83867_PHYCTRL 0x10
29#define MII_DP83867_MICR 0x12
30#define MII_DP83867_ISR 0x13
31#define DP83867_CTRL 0x1f
32
33/* Extended Registers */
34#define DP83867_RGMIICTL 0x0032
35#define DP83867_RGMIIDCTL 0x0086
36#define DP83867_IO_MUX_CFG 0x0170
37
38#define DP83867_SW_RESET BIT(15)
39#define DP83867_SW_RESTART BIT(14)
40
41/* MICR Interrupt bits */
42#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
43#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
44#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
45#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
46#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
47#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
48#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
49#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
50#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
51#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
52#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
53#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
54
55/* RGMIICTL bits */
56#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
57#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
58
59/* PHY CTRL bits */
60#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
61#define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14)
62
63/* RGMIIDCTL bits */
64#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
65
66/* IO_MUX_CFG bits */
67#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
68
69#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
70#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
71
72struct dp83867_private {
73 int rx_id_delay;
74 int tx_id_delay;
75 int fifo_depth;
76 int io_impedance;
77};
78
79static int dp83867_ack_interrupt(struct phy_device *phydev)
80{
81 int err = phy_read(phydev, MII_DP83867_ISR);
82
83 if (err < 0)
84 return err;
85
86 return 0;
87}
88
89static int dp83867_config_intr(struct phy_device *phydev)
90{
91 int micr_status;
92
93 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
94 micr_status = phy_read(phydev, MII_DP83867_MICR);
95 if (micr_status < 0)
96 return micr_status;
97
98 micr_status |=
99 (MII_DP83867_MICR_AN_ERR_INT_EN |
100 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
101 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
102 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
103
104 return phy_write(phydev, MII_DP83867_MICR, micr_status);
105 }
106
107 micr_status = 0x0;
108 return phy_write(phydev, MII_DP83867_MICR, micr_status);
109}
110
111#ifdef CONFIG_OF_MDIO
112static int dp83867_of_init(struct phy_device *phydev)
113{
114 struct dp83867_private *dp83867 = phydev->priv;
115 struct device *dev = &phydev->mdio.dev;
116 struct device_node *of_node = dev->of_node;
117 int ret;
118
119 if (!of_node)
120 return -ENODEV;
121
122 dp83867->io_impedance = -EINVAL;
123
124 /* Optional configuration */
125 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
126 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
127 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
128 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
129
130 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
131 &dp83867->rx_id_delay);
132 if (ret)
133 return ret;
134
135 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
136 &dp83867->tx_id_delay);
137 if (ret)
138 return ret;
139
140 return of_property_read_u32(of_node, "ti,fifo-depth",
141 &dp83867->fifo_depth);
142}
143#else
144static int dp83867_of_init(struct phy_device *phydev)
145{
146 return 0;
147}
148#endif /* CONFIG_OF_MDIO */
149
150static int dp83867_config_init(struct phy_device *phydev)
151{
152 struct dp83867_private *dp83867;
153 int ret, val;
154 u16 delay;
155
156 if (!phydev->priv) {
157 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
158 GFP_KERNEL);
159 if (!dp83867)
160 return -ENOMEM;
161
162 phydev->priv = dp83867;
163 ret = dp83867_of_init(phydev);
164 if (ret)
165 return ret;
166 } else {
167 dp83867 = (struct dp83867_private *)phydev->priv;
168 }
169
170 if (phy_interface_is_rgmii(phydev)) {
171 val = phy_read(phydev, MII_DP83867_PHYCTRL);
172 if (val < 0)
173 return val;
174 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
175 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
176 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
177 if (ret)
178 return ret;
179 }
180
181 if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
182 (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
183 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
184 DP83867_DEVADDR);
185
186 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
187 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
188
189 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
190 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
191
192 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
193 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
194
195 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
196 DP83867_DEVADDR, val);
197
198 delay = (dp83867->rx_id_delay |
199 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
200
201 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
202 DP83867_DEVADDR, delay);
203
204 if (dp83867->io_impedance >= 0) {
205 val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
206 DP83867_DEVADDR);
207
208 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
209 val |= dp83867->io_impedance &
210 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
211
212 phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
213 DP83867_DEVADDR, val);
214 }
215 }
216
217 return 0;
218}
219
220static int dp83867_phy_reset(struct phy_device *phydev)
221{
222 int err;
223
224 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
225 if (err < 0)
226 return err;
227
228 return dp83867_config_init(phydev);
229}
230
231static struct phy_driver dp83867_driver[] = {
232 {
233 .phy_id = DP83867_PHY_ID,
234 .phy_id_mask = 0xfffffff0,
235 .name = "TI DP83867",
236 .features = PHY_GBIT_FEATURES,
237 .flags = PHY_HAS_INTERRUPT,
238
239 .config_init = dp83867_config_init,
240 .soft_reset = dp83867_phy_reset,
241
242 /* IRQ related */
243 .ack_interrupt = dp83867_ack_interrupt,
244 .config_intr = dp83867_config_intr,
245
246 .config_aneg = genphy_config_aneg,
247 .read_status = genphy_read_status,
248 .suspend = genphy_suspend,
249 .resume = genphy_resume,
250 },
251};
252module_phy_driver(dp83867_driver);
253
254static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
255 { DP83867_PHY_ID, 0xfffffff0 },
256 { }
257};
258
259MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
260
261MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
262MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
263MODULE_LICENSE("GPL");