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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __AMD_SHARED_H__
24#define __AMD_SHARED_H__
25
26#define AMD_MAX_USEC_TIMEOUT 100000 /* 100 ms */
27
28/*
29 * Supported ASIC types
30 */
31enum amd_asic_type {
32 CHIP_TAHITI = 0,
33 CHIP_PITCAIRN,
34 CHIP_VERDE,
35 CHIP_OLAND,
36 CHIP_HAINAN,
37 CHIP_BONAIRE,
38 CHIP_KAVERI,
39 CHIP_KABINI,
40 CHIP_HAWAII,
41 CHIP_MULLINS,
42 CHIP_TOPAZ,
43 CHIP_TONGA,
44 CHIP_FIJI,
45 CHIP_CARRIZO,
46 CHIP_STONEY,
47 CHIP_POLARIS10,
48 CHIP_POLARIS11,
49 CHIP_LAST,
50};
51
52/*
53 * Chip flags
54 */
55enum amd_chip_flags {
56 AMD_ASIC_MASK = 0x0000ffffUL,
57 AMD_FLAGS_MASK = 0xffff0000UL,
58 AMD_IS_MOBILITY = 0x00010000UL,
59 AMD_IS_APU = 0x00020000UL,
60 AMD_IS_PX = 0x00040000UL,
61 AMD_EXP_HW_SUPPORT = 0x00080000UL,
62};
63
64enum amd_ip_block_type {
65 AMD_IP_BLOCK_TYPE_COMMON,
66 AMD_IP_BLOCK_TYPE_GMC,
67 AMD_IP_BLOCK_TYPE_IH,
68 AMD_IP_BLOCK_TYPE_SMC,
69 AMD_IP_BLOCK_TYPE_DCE,
70 AMD_IP_BLOCK_TYPE_GFX,
71 AMD_IP_BLOCK_TYPE_SDMA,
72 AMD_IP_BLOCK_TYPE_UVD,
73 AMD_IP_BLOCK_TYPE_VCE,
74 AMD_IP_BLOCK_TYPE_ACP,
75};
76
77enum amd_clockgating_state {
78 AMD_CG_STATE_GATE = 0,
79 AMD_CG_STATE_UNGATE,
80};
81
82enum amd_powergating_state {
83 AMD_PG_STATE_GATE = 0,
84 AMD_PG_STATE_UNGATE,
85};
86
87struct amd_vce_state {
88 /* vce clocks */
89 u32 evclk;
90 u32 ecclk;
91 /* gpu clocks */
92 u32 sclk;
93 u32 mclk;
94 u8 clk_idx;
95 u8 pstate;
96};
97
98
99#define AMD_MAX_VCE_LEVELS 6
100
101enum amd_vce_level {
102 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
103 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
104 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
105 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
106 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
107 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
108};
109
110/* CG flags */
111#define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
112#define AMD_CG_SUPPORT_GFX_MGLS (1 << 1)
113#define AMD_CG_SUPPORT_GFX_CGCG (1 << 2)
114#define AMD_CG_SUPPORT_GFX_CGLS (1 << 3)
115#define AMD_CG_SUPPORT_GFX_CGTS (1 << 4)
116#define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
117#define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6)
118#define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7)
119#define AMD_CG_SUPPORT_MC_LS (1 << 8)
120#define AMD_CG_SUPPORT_MC_MGCG (1 << 9)
121#define AMD_CG_SUPPORT_SDMA_LS (1 << 10)
122#define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11)
123#define AMD_CG_SUPPORT_BIF_LS (1 << 12)
124#define AMD_CG_SUPPORT_UVD_MGCG (1 << 13)
125#define AMD_CG_SUPPORT_VCE_MGCG (1 << 14)
126#define AMD_CG_SUPPORT_HDP_LS (1 << 15)
127#define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
128#define AMD_CG_SUPPORT_ROM_MGCG (1 << 17)
129#define AMD_CG_SUPPORT_DRM_LS (1 << 18)
130#define AMD_CG_SUPPORT_BIF_MGCG (1 << 19)
131#define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20)
132#define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21)
133
134/* PG flags */
135#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
136#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
137#define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
138#define AMD_PG_SUPPORT_UVD (1 << 3)
139#define AMD_PG_SUPPORT_VCE (1 << 4)
140#define AMD_PG_SUPPORT_CP (1 << 5)
141#define AMD_PG_SUPPORT_GDS (1 << 6)
142#define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
143#define AMD_PG_SUPPORT_SDMA (1 << 8)
144#define AMD_PG_SUPPORT_ACP (1 << 9)
145#define AMD_PG_SUPPORT_SAMU (1 << 10)
146#define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)
147#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
148
149enum amd_pm_state_type {
150 /* not used for dpm */
151 POWER_STATE_TYPE_DEFAULT,
152 POWER_STATE_TYPE_POWERSAVE,
153 /* user selectable states */
154 POWER_STATE_TYPE_BATTERY,
155 POWER_STATE_TYPE_BALANCED,
156 POWER_STATE_TYPE_PERFORMANCE,
157 /* internal states */
158 POWER_STATE_TYPE_INTERNAL_UVD,
159 POWER_STATE_TYPE_INTERNAL_UVD_SD,
160 POWER_STATE_TYPE_INTERNAL_UVD_HD,
161 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
162 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
163 POWER_STATE_TYPE_INTERNAL_BOOT,
164 POWER_STATE_TYPE_INTERNAL_THERMAL,
165 POWER_STATE_TYPE_INTERNAL_ACPI,
166 POWER_STATE_TYPE_INTERNAL_ULV,
167 POWER_STATE_TYPE_INTERNAL_3DPERF,
168};
169
170struct amd_ip_funcs {
171 /* Name of IP block */
172 char *name;
173 /* sets up early driver state (pre sw_init), does not configure hw - Optional */
174 int (*early_init)(void *handle);
175 /* sets up late driver/hw state (post hw_init) - Optional */
176 int (*late_init)(void *handle);
177 /* sets up driver state, does not configure hw */
178 int (*sw_init)(void *handle);
179 /* tears down driver state, does not configure hw */
180 int (*sw_fini)(void *handle);
181 /* sets up the hw state */
182 int (*hw_init)(void *handle);
183 /* tears down the hw state */
184 int (*hw_fini)(void *handle);
185 void (*late_fini)(void *handle);
186 /* handles IP specific hw/sw changes for suspend */
187 int (*suspend)(void *handle);
188 /* handles IP specific hw/sw changes for resume */
189 int (*resume)(void *handle);
190 /* returns current IP block idle status */
191 bool (*is_idle)(void *handle);
192 /* poll for idle */
193 int (*wait_for_idle)(void *handle);
194 /* check soft reset the IP block */
195 bool (*check_soft_reset)(void *handle);
196 /* pre soft reset the IP block */
197 int (*pre_soft_reset)(void *handle);
198 /* soft reset the IP block */
199 int (*soft_reset)(void *handle);
200 /* post soft reset the IP block */
201 int (*post_soft_reset)(void *handle);
202 /* enable/disable cg for the IP block */
203 int (*set_clockgating_state)(void *handle,
204 enum amd_clockgating_state state);
205 /* enable/disable pg for the IP block */
206 int (*set_powergating_state)(void *handle,
207 enum amd_powergating_state state);
208};
209
210#endif /* __AMD_SHARED_H__ */