tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König
23 */
24#ifndef __AMDGPU_RING_H__
25#define __AMDGPU_RING_H__
26
27#include "gpu_scheduler.h"
28
29/* max number of rings */
30#define AMDGPU_MAX_RINGS 16
31#define AMDGPU_MAX_GFX_RINGS 1
32#define AMDGPU_MAX_COMPUTE_RINGS 8
33#define AMDGPU_MAX_VCE_RINGS 3
34
35/* some special values for the owner field */
36#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
37#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
38
39#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
40#define AMDGPU_FENCE_FLAG_INT (1 << 1)
41
42enum amdgpu_ring_type {
43 AMDGPU_RING_TYPE_GFX,
44 AMDGPU_RING_TYPE_COMPUTE,
45 AMDGPU_RING_TYPE_SDMA,
46 AMDGPU_RING_TYPE_UVD,
47 AMDGPU_RING_TYPE_VCE,
48 AMDGPU_RING_TYPE_KIQ
49};
50
51struct amdgpu_device;
52struct amdgpu_ring;
53struct amdgpu_ib;
54struct amdgpu_cs_parser;
55
56/*
57 * Fences.
58 */
59struct amdgpu_fence_driver {
60 uint64_t gpu_addr;
61 volatile uint32_t *cpu_addr;
62 /* sync_seq is protected by ring emission lock */
63 uint32_t sync_seq;
64 atomic_t last_seq;
65 bool initialized;
66 struct amdgpu_irq_src *irq_src;
67 unsigned irq_type;
68 struct timer_list fallback_timer;
69 unsigned num_fences_mask;
70 spinlock_t lock;
71 struct dma_fence **fences;
72};
73
74int amdgpu_fence_driver_init(struct amdgpu_device *adev);
75void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
76void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
77
78int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
79 unsigned num_hw_submission);
80int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
81 struct amdgpu_irq_src *irq_src,
82 unsigned irq_type);
83void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
84void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
85int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence);
86void amdgpu_fence_process(struct amdgpu_ring *ring);
87int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
88unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
89
90/*
91 * Rings.
92 */
93
94/* provided by hw blocks that expose a ring buffer for commands */
95struct amdgpu_ring_funcs {
96 enum amdgpu_ring_type type;
97 uint32_t align_mask;
98 u32 nop;
99
100 /* ring read/write ptr handling */
101 u32 (*get_rptr)(struct amdgpu_ring *ring);
102 u32 (*get_wptr)(struct amdgpu_ring *ring);
103 void (*set_wptr)(struct amdgpu_ring *ring);
104 /* validating and patching of IBs */
105 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
106 /* constants to calculate how many DW are needed for an emit */
107 unsigned emit_frame_size;
108 unsigned emit_ib_size;
109 /* command emit functions */
110 void (*emit_ib)(struct amdgpu_ring *ring,
111 struct amdgpu_ib *ib,
112 unsigned vm_id, bool ctx_switch);
113 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
114 uint64_t seq, unsigned flags);
115 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
116 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
117 uint64_t pd_addr);
118 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
119 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
120 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
121 uint32_t gds_base, uint32_t gds_size,
122 uint32_t gws_base, uint32_t gws_size,
123 uint32_t oa_base, uint32_t oa_size);
124 /* testing functions */
125 int (*test_ring)(struct amdgpu_ring *ring);
126 int (*test_ib)(struct amdgpu_ring *ring, long timeout);
127 /* insert NOP packets */
128 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
129 /* pad the indirect buffer to the necessary number of dw */
130 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
131 unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
132 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
133 /* note usage for clock and power gating */
134 void (*begin_use)(struct amdgpu_ring *ring);
135 void (*end_use)(struct amdgpu_ring *ring);
136 void (*emit_switch_buffer) (struct amdgpu_ring *ring);
137 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
138};
139
140struct amdgpu_ring {
141 struct amdgpu_device *adev;
142 const struct amdgpu_ring_funcs *funcs;
143 struct amdgpu_fence_driver fence_drv;
144 struct amd_gpu_scheduler sched;
145
146 struct amdgpu_bo *ring_obj;
147 volatile uint32_t *ring;
148 unsigned rptr_offs;
149 unsigned wptr;
150 unsigned wptr_old;
151 unsigned ring_size;
152 unsigned max_dw;
153 int count_dw;
154 uint64_t gpu_addr;
155 uint32_t ptr_mask;
156 bool ready;
157 u32 idx;
158 u32 me;
159 u32 pipe;
160 u32 queue;
161 struct amdgpu_bo *mqd_obj;
162 u32 doorbell_index;
163 bool use_doorbell;
164 unsigned wptr_offs;
165 unsigned fence_offs;
166 uint64_t current_ctx;
167 char name[16];
168 unsigned cond_exe_offs;
169 u64 cond_exe_gpu_addr;
170 volatile u32 *cond_exe_cpu_addr;
171#if defined(CONFIG_DEBUG_FS)
172 struct dentry *ent;
173#endif
174};
175
176int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
177void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
178void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
179void amdgpu_ring_commit(struct amdgpu_ring *ring);
180void amdgpu_ring_undo(struct amdgpu_ring *ring);
181int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
182 unsigned ring_size, struct amdgpu_irq_src *irq_src,
183 unsigned irq_type);
184void amdgpu_ring_fini(struct amdgpu_ring *ring);
185
186#endif