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kernel
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linux
1KVM Lock Overview
2=================
3
41. Acquisition Orders
5---------------------
6
7The acquisition orders for mutexes are as follows:
8
9- kvm->lock is taken outside vcpu->mutex
10
11- kvm->lock is taken outside kvm->slots_lock and kvm->irq_lock
12
13- kvm->slots_lock is taken outside kvm->irq_lock, though acquiring
14 them together is quite rare.
15
16On x86, vcpu->mutex is taken outside kvm->arch.hyperv.hv_lock.
17
18For spinlocks, kvm_lock is taken outside kvm->mmu_lock.
19
20Everything else is a leaf: no other lock is taken inside the critical
21sections.
22
232: Exception
24------------
25
26Fast page fault:
27
28Fast page fault is the fast path which fixes the guest page fault out of
29the mmu-lock on x86. Currently, the page fault can be fast only if the
30shadow page table is present and it is caused by write-protect, that means
31we just need change the W bit of the spte.
32
33What we use to avoid all the race is the SPTE_HOST_WRITEABLE bit and
34SPTE_MMU_WRITEABLE bit on the spte:
35- SPTE_HOST_WRITEABLE means the gfn is writable on host.
36- SPTE_MMU_WRITEABLE means the gfn is writable on mmu. The bit is set when
37 the gfn is writable on guest mmu and it is not write-protected by shadow
38 page write-protection.
39
40On fast page fault path, we will use cmpxchg to atomically set the spte W
41bit if spte.SPTE_HOST_WRITEABLE = 1 and spte.SPTE_WRITE_PROTECT = 1, this
42is safe because whenever changing these bits can be detected by cmpxchg.
43
44But we need carefully check these cases:
451): The mapping from gfn to pfn
46The mapping from gfn to pfn may be changed since we can only ensure the pfn
47is not changed during cmpxchg. This is a ABA problem, for example, below case
48will happen:
49
50At the beginning:
51gpte = gfn1
52gfn1 is mapped to pfn1 on host
53spte is the shadow page table entry corresponding with gpte and
54spte = pfn1
55
56 VCPU 0 VCPU0
57on fast page fault path:
58
59 old_spte = *spte;
60 pfn1 is swapped out:
61 spte = 0;
62
63 pfn1 is re-alloced for gfn2.
64
65 gpte is changed to point to
66 gfn2 by the guest:
67 spte = pfn1;
68
69 if (cmpxchg(spte, old_spte, old_spte+W)
70 mark_page_dirty(vcpu->kvm, gfn1)
71 OOPS!!!
72
73We dirty-log for gfn1, that means gfn2 is lost in dirty-bitmap.
74
75For direct sp, we can easily avoid it since the spte of direct sp is fixed
76to gfn. For indirect sp, before we do cmpxchg, we call gfn_to_pfn_atomic()
77to pin gfn to pfn, because after gfn_to_pfn_atomic():
78- We have held the refcount of pfn that means the pfn can not be freed and
79 be reused for another gfn.
80- The pfn is writable that means it can not be shared between different gfns
81 by KSM.
82
83Then, we can ensure the dirty bitmaps is correctly set for a gfn.
84
85Currently, to simplify the whole things, we disable fast page fault for
86indirect shadow page.
87
882): Dirty bit tracking
89In the origin code, the spte can be fast updated (non-atomically) if the
90spte is read-only and the Accessed bit has already been set since the
91Accessed bit and Dirty bit can not be lost.
92
93But it is not true after fast page fault since the spte can be marked
94writable between reading spte and updating spte. Like below case:
95
96At the beginning:
97spte.W = 0
98spte.Accessed = 1
99
100 VCPU 0 VCPU0
101In mmu_spte_clear_track_bits():
102
103 old_spte = *spte;
104
105 /* 'if' condition is satisfied. */
106 if (old_spte.Accessed == 1 &&
107 old_spte.W == 0)
108 spte = 0ull;
109 on fast page fault path:
110 spte.W = 1
111 memory write on the spte:
112 spte.Dirty = 1
113
114
115 else
116 old_spte = xchg(spte, 0ull)
117
118
119 if (old_spte.Accessed == 1)
120 kvm_set_pfn_accessed(spte.pfn);
121 if (old_spte.Dirty == 1)
122 kvm_set_pfn_dirty(spte.pfn);
123 OOPS!!!
124
125The Dirty bit is lost in this case.
126
127In order to avoid this kind of issue, we always treat the spte as "volatile"
128if it can be updated out of mmu-lock, see spte_has_volatile_bits(), it means,
129the spte is always atomically updated in this case.
130
1313): flush tlbs due to spte updated
132If the spte is updated from writable to readonly, we should flush all TLBs,
133otherwise rmap_write_protect will find a read-only spte, even though the
134writable spte might be cached on a CPU's TLB.
135
136As mentioned before, the spte can be updated to writable out of mmu-lock on
137fast page fault path, in order to easily audit the path, we see if TLBs need
138be flushed caused by this reason in mmu_spte_update() since this is a common
139function to update spte (present -> present).
140
141Since the spte is "volatile" if it can be updated out of mmu-lock, we always
142atomically update the spte, the race caused by fast page fault can be avoided,
143See the comments in spte_has_volatile_bits() and mmu_spte_update().
144
1453. Reference
146------------
147
148Name: kvm_lock
149Type: spinlock_t
150Arch: any
151Protects: - vm_list
152
153Name: kvm_count_lock
154Type: raw_spinlock_t
155Arch: any
156Protects: - hardware virtualization enable/disable
157Comment: 'raw' because hardware enabling/disabling must be atomic /wrt
158 migration.
159
160Name: kvm_arch::tsc_write_lock
161Type: raw_spinlock
162Arch: x86
163Protects: - kvm_arch::{last_tsc_write,last_tsc_nsec,last_tsc_offset}
164 - tsc offset in vmcb
165Comment: 'raw' because updating the tsc offsets must not be preempted.
166
167Name: kvm->mmu_lock
168Type: spinlock_t
169Arch: any
170Protects: -shadow page/shadow tlb entry
171Comment: it is a spinlock since it is used in mmu notifier.
172
173Name: kvm->srcu
174Type: srcu lock
175Arch: any
176Protects: - kvm->memslots
177 - kvm->buses
178Comment: The srcu read lock must be held while accessing memslots (e.g.
179 when using gfn_to_* functions) and while accessing in-kernel
180 MMIO/PIO address->device structure mapping (kvm->buses).
181 The srcu index can be stored in kvm_vcpu->srcu_idx per vcpu
182 if it is needed by multiple functions.
183
184Name: blocked_vcpu_on_cpu_lock
185Type: spinlock_t
186Arch: x86
187Protects: blocked_vcpu_on_cpu
188Comment: This is a per-CPU lock and it is used for VT-d posted-interrupts.
189 When VT-d posted-interrupts is supported and the VM has assigned
190 devices, we put the blocked vCPU on the list blocked_vcpu_on_cpu
191 protected by blocked_vcpu_on_cpu_lock, when VT-d hardware issues
192 wakeup notification event since external interrupts from the
193 assigned devices happens, we will find the vCPU on the list to
194 wakeup.