tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, see <http://www.gnu.org/licenses/>.
22 .
23 . Information contained in this file was obtained from the LAN91C111
24 . manual from SMC. To get a copy, if you really want one, you can find
25 . information under www.smsc.com.
26 .
27 . Authors
28 . Erik Stahlman <erik@vt.edu>
29 . Daris A Nevil <dnevil@snmc.com>
30 . Nicolas Pitre <nico@fluxnic.net>
31 .
32 ---------------------------------------------------------------------------*/
33#ifndef _SMC91X_H_
34#define _SMC91X_H_
35
36#include <linux/smc91x.h>
37
38/*
39 * Define your architecture specific bus configuration parameters here.
40 */
41
42#if defined(CONFIG_ARM)
43
44#include <asm/mach-types.h>
45
46/* Now the bus width is specified in the platform data
47 * pretend here to support all I/O access types
48 */
49#define SMC_CAN_USE_8BIT 1
50#define SMC_CAN_USE_16BIT 1
51#define SMC_CAN_USE_32BIT 1
52#define SMC_NOWAIT 1
53
54#define SMC_IO_SHIFT (lp->io_shift)
55
56#define SMC_inb(a, r) readb((a) + (r))
57#define SMC_inw(a, r) readw((a) + (r))
58#define SMC_inl(a, r) readl((a) + (r))
59#define SMC_outb(v, a, r) writeb(v, (a) + (r))
60#define SMC_outl(v, a, r) writel(v, (a) + (r))
61#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
62#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
63#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
64#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
65#define SMC_IRQ_FLAGS (-1) /* from resource */
66
67/* We actually can't write halfwords properly if not word aligned */
68static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
69{
70 if ((machine_is_mainstone() || machine_is_stargate2() ||
71 machine_is_pxa_idp()) && reg & 2) {
72 unsigned int v = val << 16;
73 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
74 writel(v, ioaddr + (reg & ~2));
75 } else {
76 writew(val, ioaddr + reg);
77 }
78}
79
80#elif defined(CONFIG_SH_SH4202_MICRODEV)
81
82#define SMC_CAN_USE_8BIT 0
83#define SMC_CAN_USE_16BIT 1
84#define SMC_CAN_USE_32BIT 0
85
86#define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
87#define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
88#define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
89#define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
90#define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
91#define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
92#define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
93#define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
94#define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
95#define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
96
97#define SMC_IRQ_FLAGS (0)
98
99#elif defined(CONFIG_M32R)
100
101#define SMC_CAN_USE_8BIT 0
102#define SMC_CAN_USE_16BIT 1
103#define SMC_CAN_USE_32BIT 0
104
105#define SMC_inb(a, r) inb(((u32)a) + (r))
106#define SMC_inw(a, r) inw(((u32)a) + (r))
107#define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
108#define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
109#define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
110#define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
111
112#define SMC_IRQ_FLAGS (0)
113
114#define RPC_LSA_DEFAULT RPC_LED_TX_RX
115#define RPC_LSB_DEFAULT RPC_LED_100_10
116
117#elif defined(CONFIG_MN10300)
118
119/*
120 * MN10300/AM33 configuration
121 */
122
123#include <unit/smc91111.h>
124
125#elif defined(CONFIG_ATARI)
126
127#define SMC_CAN_USE_8BIT 1
128#define SMC_CAN_USE_16BIT 1
129#define SMC_CAN_USE_32BIT 1
130#define SMC_NOWAIT 1
131
132#define SMC_inb(a, r) readb((a) + (r))
133#define SMC_inw(a, r) readw((a) + (r))
134#define SMC_inl(a, r) readl((a) + (r))
135#define SMC_outb(v, a, r) writeb(v, (a) + (r))
136#define SMC_outw(v, a, r) writew(v, (a) + (r))
137#define SMC_outl(v, a, r) writel(v, (a) + (r))
138#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
139#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
140#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
141#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
142
143#define RPC_LSA_DEFAULT RPC_LED_100_10
144#define RPC_LSB_DEFAULT RPC_LED_TX_RX
145
146#elif defined(CONFIG_COLDFIRE)
147
148#define SMC_CAN_USE_8BIT 0
149#define SMC_CAN_USE_16BIT 1
150#define SMC_CAN_USE_32BIT 0
151#define SMC_NOWAIT 1
152
153static inline void mcf_insw(void *a, unsigned char *p, int l)
154{
155 u16 *wp = (u16 *) p;
156 while (l-- > 0)
157 *wp++ = readw(a);
158}
159
160static inline void mcf_outsw(void *a, unsigned char *p, int l)
161{
162 u16 *wp = (u16 *) p;
163 while (l-- > 0)
164 writew(*wp++, a);
165}
166
167#define SMC_inw(a, r) _swapw(readw((a) + (r)))
168#define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r))
169#define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l)
170#define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l)
171
172#define SMC_IRQ_FLAGS 0
173
174#else
175
176/*
177 * Default configuration
178 */
179
180#define SMC_CAN_USE_8BIT 1
181#define SMC_CAN_USE_16BIT 1
182#define SMC_CAN_USE_32BIT 1
183#define SMC_NOWAIT 1
184
185#define SMC_IO_SHIFT (lp->io_shift)
186
187#define SMC_inb(a, r) ioread8((a) + (r))
188#define SMC_inw(a, r) ioread16((a) + (r))
189#define SMC_inl(a, r) ioread32((a) + (r))
190#define SMC_outb(v, a, r) iowrite8(v, (a) + (r))
191#define SMC_outw(v, a, r) iowrite16(v, (a) + (r))
192#define SMC_outl(v, a, r) iowrite32(v, (a) + (r))
193#define SMC_insw(a, r, p, l) ioread16_rep((a) + (r), p, l)
194#define SMC_outsw(a, r, p, l) iowrite16_rep((a) + (r), p, l)
195#define SMC_insl(a, r, p, l) ioread32_rep((a) + (r), p, l)
196#define SMC_outsl(a, r, p, l) iowrite32_rep((a) + (r), p, l)
197
198#define RPC_LSA_DEFAULT RPC_LED_100_10
199#define RPC_LSB_DEFAULT RPC_LED_TX_RX
200
201#endif
202
203
204/* store this information for the driver.. */
205struct smc_local {
206 /*
207 * If I have to wait until memory is available to send a
208 * packet, I will store the skbuff here, until I get the
209 * desired memory. Then, I'll send it out and free it.
210 */
211 struct sk_buff *pending_tx_skb;
212 struct tasklet_struct tx_task;
213
214 struct gpio_desc *power_gpio;
215 struct gpio_desc *reset_gpio;
216
217 /* version/revision of the SMC91x chip */
218 int version;
219
220 /* Contains the current active transmission mode */
221 int tcr_cur_mode;
222
223 /* Contains the current active receive mode */
224 int rcr_cur_mode;
225
226 /* Contains the current active receive/phy mode */
227 int rpc_cur_mode;
228 int ctl_rfduplx;
229 int ctl_rspeed;
230
231 u32 msg_enable;
232 u32 phy_type;
233 struct mii_if_info mii;
234
235 /* work queue */
236 struct work_struct phy_configure;
237 struct net_device *dev;
238 int work_pending;
239
240 spinlock_t lock;
241
242#ifdef CONFIG_ARCH_PXA
243 /* DMA needs the physical address of the chip */
244 u_long physaddr;
245 struct device *device;
246#endif
247 void __iomem *base;
248 void __iomem *datacs;
249
250 /* the low address lines on some platforms aren't connected... */
251 int io_shift;
252
253 struct smc91x_platdata cfg;
254};
255
256#define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
257#define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
258#define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
259
260#ifdef CONFIG_ARCH_PXA
261/*
262 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
263 * always happening in irq context so no need to worry about races. TX is
264 * different and probably not worth it for that reason, and not as critical
265 * as RX which can overrun memory and lose packets.
266 */
267#include <linux/dma-mapping.h>
268#include <mach/dma.h>
269
270#ifdef SMC_insl
271#undef SMC_insl
272#define SMC_insl(a, r, p, l) \
273 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
274static inline void
275smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
276 u_char *buf, int len)
277{
278 u_long physaddr = lp->physaddr;
279 dma_addr_t dmabuf;
280
281 /* fallback if no DMA available */
282 if (dma == (unsigned char)-1) {
283 readsl(ioaddr + reg, buf, len);
284 return;
285 }
286
287 /* 64 bit alignment is required for memory to memory DMA */
288 if ((long)buf & 4) {
289 *((u32 *)buf) = SMC_inl(ioaddr, reg);
290 buf += 4;
291 len--;
292 }
293
294 len *= 4;
295 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
296 DCSR(dma) = DCSR_NODESC;
297 DTADR(dma) = dmabuf;
298 DSADR(dma) = physaddr + reg;
299 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
300 DCMD_WIDTH4 | (DCMD_LENGTH & len));
301 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
302 while (!(DCSR(dma) & DCSR_STOPSTATE))
303 cpu_relax();
304 DCSR(dma) = 0;
305 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
306}
307#endif
308
309#ifdef SMC_insw
310#undef SMC_insw
311#define SMC_insw(a, r, p, l) \
312 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
313static inline void
314smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
315 u_char *buf, int len)
316{
317 u_long physaddr = lp->physaddr;
318 dma_addr_t dmabuf;
319
320 /* fallback if no DMA available */
321 if (dma == (unsigned char)-1) {
322 readsw(ioaddr + reg, buf, len);
323 return;
324 }
325
326 /* 64 bit alignment is required for memory to memory DMA */
327 while ((long)buf & 6) {
328 *((u16 *)buf) = SMC_inw(ioaddr, reg);
329 buf += 2;
330 len--;
331 }
332
333 len *= 2;
334 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
335 DCSR(dma) = DCSR_NODESC;
336 DTADR(dma) = dmabuf;
337 DSADR(dma) = physaddr + reg;
338 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
339 DCMD_WIDTH2 | (DCMD_LENGTH & len));
340 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
341 while (!(DCSR(dma) & DCSR_STOPSTATE))
342 cpu_relax();
343 DCSR(dma) = 0;
344 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
345}
346#endif
347
348static void
349smc_pxa_dma_irq(int dma, void *dummy)
350{
351 DCSR(dma) = 0;
352}
353#endif /* CONFIG_ARCH_PXA */
354
355
356/*
357 * Everything a particular hardware setup needs should have been defined
358 * at this point. Add stubs for the undefined cases, mainly to avoid
359 * compilation warnings since they'll be optimized away, or to prevent buggy
360 * use of them.
361 */
362
363#if ! SMC_CAN_USE_32BIT
364#define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
365#define SMC_outl(x, ioaddr, reg) BUG()
366#define SMC_insl(a, r, p, l) BUG()
367#define SMC_outsl(a, r, p, l) BUG()
368#endif
369
370#if !defined(SMC_insl) || !defined(SMC_outsl)
371#define SMC_insl(a, r, p, l) BUG()
372#define SMC_outsl(a, r, p, l) BUG()
373#endif
374
375#if ! SMC_CAN_USE_16BIT
376
377/*
378 * Any 16-bit access is performed with two 8-bit accesses if the hardware
379 * can't do it directly. Most registers are 16-bit so those are mandatory.
380 */
381#define SMC_outw(x, ioaddr, reg) \
382 do { \
383 unsigned int __val16 = (x); \
384 SMC_outb( __val16, ioaddr, reg ); \
385 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
386 } while (0)
387#define SMC_inw(ioaddr, reg) \
388 ({ \
389 unsigned int __val16; \
390 __val16 = SMC_inb( ioaddr, reg ); \
391 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
392 __val16; \
393 })
394
395#define SMC_insw(a, r, p, l) BUG()
396#define SMC_outsw(a, r, p, l) BUG()
397
398#endif
399
400#if !defined(SMC_insw) || !defined(SMC_outsw)
401#define SMC_insw(a, r, p, l) BUG()
402#define SMC_outsw(a, r, p, l) BUG()
403#endif
404
405#if ! SMC_CAN_USE_8BIT
406#define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
407#define SMC_outb(x, ioaddr, reg) BUG()
408#define SMC_insb(a, r, p, l) BUG()
409#define SMC_outsb(a, r, p, l) BUG()
410#endif
411
412#if !defined(SMC_insb) || !defined(SMC_outsb)
413#define SMC_insb(a, r, p, l) BUG()
414#define SMC_outsb(a, r, p, l) BUG()
415#endif
416
417#ifndef SMC_CAN_USE_DATACS
418#define SMC_CAN_USE_DATACS 0
419#endif
420
421#ifndef SMC_IO_SHIFT
422#define SMC_IO_SHIFT 0
423#endif
424
425#ifndef SMC_IRQ_FLAGS
426#define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
427#endif
428
429#ifndef SMC_INTERRUPT_PREAMBLE
430#define SMC_INTERRUPT_PREAMBLE
431#endif
432
433
434/* Because of bank switching, the LAN91x uses only 16 I/O ports */
435#define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
436#define SMC_DATA_EXTENT (4)
437
438/*
439 . Bank Select Register:
440 .
441 . yyyy yyyy 0000 00xx
442 . xx = bank number
443 . yyyy yyyy = 0x33, for identification purposes.
444*/
445#define BANK_SELECT (14 << SMC_IO_SHIFT)
446
447
448// Transmit Control Register
449/* BANK 0 */
450#define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
451#define TCR_ENABLE 0x0001 // When 1 we can transmit
452#define TCR_LOOP 0x0002 // Controls output pin LBK
453#define TCR_FORCOL 0x0004 // When 1 will force a collision
454#define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
455#define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
456#define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
457#define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
458#define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
459#define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
460#define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
461
462#define TCR_CLEAR 0 /* do NOTHING */
463/* the default settings for the TCR register : */
464#define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
465
466
467// EPH Status Register
468/* BANK 0 */
469#define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
470#define ES_TX_SUC 0x0001 // Last TX was successful
471#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
472#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
473#define ES_LTX_MULT 0x0008 // Last tx was a multicast
474#define ES_16COL 0x0010 // 16 Collisions Reached
475#define ES_SQET 0x0020 // Signal Quality Error Test
476#define ES_LTXBRD 0x0040 // Last tx was a broadcast
477#define ES_TXDEFR 0x0080 // Transmit Deferred
478#define ES_LATCOL 0x0200 // Late collision detected on last tx
479#define ES_LOSTCARR 0x0400 // Lost Carrier Sense
480#define ES_EXC_DEF 0x0800 // Excessive Deferral
481#define ES_CTR_ROL 0x1000 // Counter Roll Over indication
482#define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
483#define ES_TXUNRN 0x8000 // Tx Underrun
484
485
486// Receive Control Register
487/* BANK 0 */
488#define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
489#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
490#define RCR_PRMS 0x0002 // Enable promiscuous mode
491#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
492#define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
493#define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
494#define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
495#define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
496#define RCR_SOFTRST 0x8000 // resets the chip
497
498/* the normal settings for the RCR register : */
499#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
500#define RCR_CLEAR 0x0 // set it to a base state
501
502
503// Counter Register
504/* BANK 0 */
505#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
506
507
508// Memory Information Register
509/* BANK 0 */
510#define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
511
512
513// Receive/Phy Control Register
514/* BANK 0 */
515#define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
516#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
517#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
518#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
519#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
520#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
521
522#ifndef RPC_LSA_DEFAULT
523#define RPC_LSA_DEFAULT RPC_LED_100
524#endif
525#ifndef RPC_LSB_DEFAULT
526#define RPC_LSB_DEFAULT RPC_LED_FD
527#endif
528
529#define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
530
531
532/* Bank 0 0x0C is reserved */
533
534// Bank Select Register
535/* All Banks */
536#define BSR_REG 0x000E
537
538
539// Configuration Reg
540/* BANK 1 */
541#define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
542#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
543#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
544#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
545#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
546
547// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
548#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
549
550
551// Base Address Register
552/* BANK 1 */
553#define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
554
555
556// Individual Address Registers
557/* BANK 1 */
558#define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
559#define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
560#define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
561
562
563// General Purpose Register
564/* BANK 1 */
565#define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
566
567
568// Control Register
569/* BANK 1 */
570#define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
571#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
572#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
573#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
574#define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
575#define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
576#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
577#define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
578#define CTL_STORE 0x0001 // When set stores registers into EEPROM
579
580
581// MMU Command Register
582/* BANK 2 */
583#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
584#define MC_BUSY 1 // When 1 the last release has not completed
585#define MC_NOP (0<<5) // No Op
586#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
587#define MC_RESET (2<<5) // Reset MMU to initial state
588#define MC_REMOVE (3<<5) // Remove the current rx packet
589#define MC_RELEASE (4<<5) // Remove and release the current rx packet
590#define MC_FREEPKT (5<<5) // Release packet in PNR register
591#define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
592#define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
593
594
595// Packet Number Register
596/* BANK 2 */
597#define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
598
599
600// Allocation Result Register
601/* BANK 2 */
602#define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
603#define AR_FAILED 0x80 // Alocation Failed
604
605
606// TX FIFO Ports Register
607/* BANK 2 */
608#define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
609#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
610
611// RX FIFO Ports Register
612/* BANK 2 */
613#define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
614#define RXFIFO_REMPTY 0x80 // RX FIFO Empty
615
616#define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
617
618// Pointer Register
619/* BANK 2 */
620#define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
621#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
622#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
623#define PTR_READ 0x2000 // When 1 the operation is a read
624
625
626// Data Register
627/* BANK 2 */
628#define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
629
630
631// Interrupt Status/Acknowledge Register
632/* BANK 2 */
633#define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
634
635
636// Interrupt Mask Register
637/* BANK 2 */
638#define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
639#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
640#define IM_ERCV_INT 0x40 // Early Receive Interrupt
641#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
642#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
643#define IM_ALLOC_INT 0x08 // Set when allocation request is completed
644#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
645#define IM_TX_INT 0x02 // Transmit Interrupt
646#define IM_RCV_INT 0x01 // Receive Interrupt
647
648
649// Multicast Table Registers
650/* BANK 3 */
651#define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
652#define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
653#define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
654#define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
655
656
657// Management Interface Register (MII)
658/* BANK 3 */
659#define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
660#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
661#define MII_MDOE 0x0008 // MII Output Enable
662#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
663#define MII_MDI 0x0002 // MII Input, pin MDI
664#define MII_MDO 0x0001 // MII Output, pin MDO
665
666
667// Revision Register
668/* BANK 3 */
669/* ( hi: chip id low: rev # ) */
670#define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
671
672
673// Early RCV Register
674/* BANK 3 */
675/* this is NOT on SMC9192 */
676#define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
677#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
678#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
679
680
681// External Register
682/* BANK 7 */
683#define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
684
685
686#define CHIP_9192 3
687#define CHIP_9194 4
688#define CHIP_9195 5
689#define CHIP_9196 6
690#define CHIP_91100 7
691#define CHIP_91100FD 8
692#define CHIP_91111FD 9
693
694static const char * chip_ids[ 16 ] = {
695 NULL, NULL, NULL,
696 /* 3 */ "SMC91C90/91C92",
697 /* 4 */ "SMC91C94",
698 /* 5 */ "SMC91C95",
699 /* 6 */ "SMC91C96",
700 /* 7 */ "SMC91C100",
701 /* 8 */ "SMC91C100FD",
702 /* 9 */ "SMC91C11xFD",
703 NULL, NULL, NULL,
704 NULL, NULL, NULL};
705
706
707/*
708 . Receive status bits
709*/
710#define RS_ALGNERR 0x8000
711#define RS_BRODCAST 0x4000
712#define RS_BADCRC 0x2000
713#define RS_ODDFRAME 0x1000
714#define RS_TOOLONG 0x0800
715#define RS_TOOSHORT 0x0400
716#define RS_MULTICAST 0x0001
717#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
718
719
720/*
721 * PHY IDs
722 * LAN83C183 == LAN91C111 Internal PHY
723 */
724#define PHY_LAN83C183 0x0016f840
725#define PHY_LAN83C180 0x02821c50
726
727/*
728 * PHY Register Addresses (LAN91C111 Internal PHY)
729 *
730 * Generic PHY registers can be found in <linux/mii.h>
731 *
732 * These phy registers are specific to our on-board phy.
733 */
734
735// PHY Configuration Register 1
736#define PHY_CFG1_REG 0x10
737#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
738#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
739#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
740#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
741#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
742#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
743#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
744#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
745#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
746#define PHY_CFG1_TLVL_MASK 0x003C
747#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
748
749
750// PHY Configuration Register 2
751#define PHY_CFG2_REG 0x11
752#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
753#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
754#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
755#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
756
757// PHY Status Output (and Interrupt status) Register
758#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
759#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
760#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
761#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
762#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
763#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
764#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
765#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
766#define PHY_INT_JAB 0x0100 // 1=Jabber detected
767#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
768#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
769
770// PHY Interrupt/Status Mask Register
771#define PHY_MASK_REG 0x13 // Interrupt Mask
772// Uses the same bit definitions as PHY_INT_REG
773
774
775/*
776 * SMC91C96 ethernet config and status registers.
777 * These are in the "attribute" space.
778 */
779#define ECOR 0x8000
780#define ECOR_RESET 0x80
781#define ECOR_LEVEL_IRQ 0x40
782#define ECOR_WR_ATTRIB 0x04
783#define ECOR_ENABLE 0x01
784
785#define ECSR 0x8002
786#define ECSR_IOIS8 0x20
787#define ECSR_PWRDWN 0x04
788#define ECSR_INT 0x02
789
790#define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
791
792
793/*
794 * Macros to abstract register access according to the data bus
795 * capabilities. Please use those and not the in/out primitives.
796 * Note: the following macros do *not* select the bank -- this must
797 * be done separately as needed in the main code. The SMC_REG() macro
798 * only uses the bank argument for debugging purposes (when enabled).
799 *
800 * Note: despite inline functions being safer, everything leading to this
801 * should preferably be macros to let BUG() display the line number in
802 * the core source code since we're interested in the top call site
803 * not in any inline function location.
804 */
805
806#if SMC_DEBUG > 0
807#define SMC_REG(lp, reg, bank) \
808 ({ \
809 int __b = SMC_CURRENT_BANK(lp); \
810 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
811 pr_err("%s: bank reg screwed (0x%04x)\n", \
812 CARDNAME, __b); \
813 BUG(); \
814 } \
815 reg<<SMC_IO_SHIFT; \
816 })
817#else
818#define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
819#endif
820
821/*
822 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
823 * aligned to a 32 bit boundary. I tell you that does exist!
824 * Fortunately the affected register accesses can be easily worked around
825 * since we can write zeroes to the preceding 16 bits without adverse
826 * effects and use a 32-bit access.
827 *
828 * Enforce it on any 32-bit capable setup for now.
829 */
830#define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
831
832#define SMC_GET_PN(lp) \
833 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
834 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
835
836#define SMC_SET_PN(lp, x) \
837 do { \
838 if (SMC_MUST_ALIGN_WRITE(lp)) \
839 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
840 else if (SMC_8BIT(lp)) \
841 SMC_outb(x, ioaddr, PN_REG(lp)); \
842 else \
843 SMC_outw(x, ioaddr, PN_REG(lp)); \
844 } while (0)
845
846#define SMC_GET_AR(lp) \
847 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
848 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
849
850#define SMC_GET_TXFIFO(lp) \
851 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
852 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
853
854#define SMC_GET_RXFIFO(lp) \
855 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
856 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
857
858#define SMC_GET_INT(lp) \
859 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
860 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
861
862#define SMC_ACK_INT(lp, x) \
863 do { \
864 if (SMC_8BIT(lp)) \
865 SMC_outb(x, ioaddr, INT_REG(lp)); \
866 else { \
867 unsigned long __flags; \
868 int __mask; \
869 local_irq_save(__flags); \
870 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
871 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
872 local_irq_restore(__flags); \
873 } \
874 } while (0)
875
876#define SMC_GET_INT_MASK(lp) \
877 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
878 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
879
880#define SMC_SET_INT_MASK(lp, x) \
881 do { \
882 if (SMC_8BIT(lp)) \
883 SMC_outb(x, ioaddr, IM_REG(lp)); \
884 else \
885 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
886 } while (0)
887
888#define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
889
890#define SMC_SELECT_BANK(lp, x) \
891 do { \
892 if (SMC_MUST_ALIGN_WRITE(lp)) \
893 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
894 else \
895 SMC_outw(x, ioaddr, BANK_SELECT); \
896 } while (0)
897
898#define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
899
900#define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
901
902#define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
903
904#define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
905
906#define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
907
908#define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
909
910#define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
911
912#define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
913
914#define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp))
915
916#define SMC_SET_GP(lp, x) \
917 do { \
918 if (SMC_MUST_ALIGN_WRITE(lp)) \
919 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
920 else \
921 SMC_outw(x, ioaddr, GP_REG(lp)); \
922 } while (0)
923
924#define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
925
926#define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
927
928#define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
929
930#define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
931
932#define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
933
934#define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
935
936#define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
937
938#define SMC_SET_PTR(lp, x) \
939 do { \
940 if (SMC_MUST_ALIGN_WRITE(lp)) \
941 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
942 else \
943 SMC_outw(x, ioaddr, PTR_REG(lp)); \
944 } while (0)
945
946#define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
947
948#define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
949
950#define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
951
952#define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
953
954#define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
955
956#define SMC_SET_RPC(lp, x) \
957 do { \
958 if (SMC_MUST_ALIGN_WRITE(lp)) \
959 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
960 else \
961 SMC_outw(x, ioaddr, RPC_REG(lp)); \
962 } while (0)
963
964#define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
965
966#define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
967
968#ifndef SMC_GET_MAC_ADDR
969#define SMC_GET_MAC_ADDR(lp, addr) \
970 do { \
971 unsigned int __v; \
972 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
973 addr[0] = __v; addr[1] = __v >> 8; \
974 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
975 addr[2] = __v; addr[3] = __v >> 8; \
976 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
977 addr[4] = __v; addr[5] = __v >> 8; \
978 } while (0)
979#endif
980
981#define SMC_SET_MAC_ADDR(lp, addr) \
982 do { \
983 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
984 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
985 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
986 } while (0)
987
988#define SMC_SET_MCAST(lp, x) \
989 do { \
990 const unsigned char *mt = (x); \
991 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
992 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
993 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
994 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
995 } while (0)
996
997#define SMC_PUT_PKT_HDR(lp, status, length) \
998 do { \
999 if (SMC_32BIT(lp)) \
1000 SMC_outl((status) | (length)<<16, ioaddr, \
1001 DATA_REG(lp)); \
1002 else { \
1003 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1004 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1005 } \
1006 } while (0)
1007
1008#define SMC_GET_PKT_HDR(lp, status, length) \
1009 do { \
1010 if (SMC_32BIT(lp)) { \
1011 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1012 (status) = __val & 0xffff; \
1013 (length) = __val >> 16; \
1014 } else { \
1015 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1016 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1017 } \
1018 } while (0)
1019
1020#define SMC_PUSH_DATA(lp, p, l) \
1021 do { \
1022 if (SMC_32BIT(lp)) { \
1023 void *__ptr = (p); \
1024 int __len = (l); \
1025 void __iomem *__ioaddr = ioaddr; \
1026 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1027 __len -= 2; \
1028 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1029 __ptr += 2; \
1030 } \
1031 if (SMC_CAN_USE_DATACS && lp->datacs) \
1032 __ioaddr = lp->datacs; \
1033 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1034 if (__len & 2) { \
1035 __ptr += (__len & ~3); \
1036 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1037 } \
1038 } else if (SMC_16BIT(lp)) \
1039 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1040 else if (SMC_8BIT(lp)) \
1041 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1042 } while (0)
1043
1044#define SMC_PULL_DATA(lp, p, l) \
1045 do { \
1046 if (SMC_32BIT(lp)) { \
1047 void *__ptr = (p); \
1048 int __len = (l); \
1049 void __iomem *__ioaddr = ioaddr; \
1050 if ((unsigned long)__ptr & 2) { \
1051 /* \
1052 * We want 32bit alignment here. \
1053 * Since some buses perform a full \
1054 * 32bit fetch even for 16bit data \
1055 * we can't use SMC_inw() here. \
1056 * Back both source (on-chip) and \
1057 * destination pointers of 2 bytes. \
1058 * This is possible since the call to \
1059 * SMC_GET_PKT_HDR() already advanced \
1060 * the source pointer of 4 bytes, and \
1061 * the skb_reserve(skb, 2) advanced \
1062 * the destination pointer of 2 bytes. \
1063 */ \
1064 __ptr -= 2; \
1065 __len += 2; \
1066 SMC_SET_PTR(lp, \
1067 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1068 } \
1069 if (SMC_CAN_USE_DATACS && lp->datacs) \
1070 __ioaddr = lp->datacs; \
1071 __len += 2; \
1072 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1073 } else if (SMC_16BIT(lp)) \
1074 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1075 else if (SMC_8BIT(lp)) \
1076 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1077 } while (0)
1078
1079#endif /* _SMC91X_H_ */