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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
8 */
9#ifndef __ASM_CPU_FEATURES_H
10#define __ASM_CPU_FEATURES_H
11
12#include <asm/cpu.h>
13#include <asm/cpu-info.h>
14#include <cpu-feature-overrides.h>
15
16/*
17 * SMP assumption: Options of CPU 0 are a superset of all processors.
18 * This is true for all known MIPS systems.
19 */
20#ifndef cpu_has_tlb
21#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
22#endif
23#ifndef cpu_has_tlbinv
24#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
25#endif
26#ifndef cpu_has_segments
27#define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
28#endif
29#ifndef cpu_has_eva
30#define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA)
31#endif
32#ifndef cpu_has_htw
33#define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
34#endif
35#ifndef cpu_has_rixiex
36#define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
37#endif
38#ifndef cpu_has_maar
39#define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR)
40#endif
41#ifndef cpu_has_rw_llb
42#define cpu_has_rw_llb (cpu_data[0].options & MIPS_CPU_RW_LLB)
43#endif
44
45/*
46 * For the moment we don't consider R6000 and R8000 so we can assume that
47 * anything that doesn't support R4000-style exceptions and interrupts is
48 * R3000-like. Users should still treat these two macro definitions as
49 * opaque.
50 */
51#ifndef cpu_has_3kex
52#define cpu_has_3kex (!cpu_has_4kex)
53#endif
54#ifndef cpu_has_4kex
55#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
56#endif
57#ifndef cpu_has_3k_cache
58#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
59#endif
60#define cpu_has_6k_cache 0
61#define cpu_has_8k_cache 0
62#ifndef cpu_has_4k_cache
63#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
64#endif
65#ifndef cpu_has_tx39_cache
66#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
67#endif
68#ifndef cpu_has_octeon_cache
69#define cpu_has_octeon_cache 0
70#endif
71#ifndef cpu_has_fpu
72#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
73#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
74#else
75#define raw_cpu_has_fpu cpu_has_fpu
76#endif
77#ifndef cpu_has_32fpr
78#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
79#endif
80#ifndef cpu_has_counter
81#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
82#endif
83#ifndef cpu_has_watch
84#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
85#endif
86#ifndef cpu_has_divec
87#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
88#endif
89#ifndef cpu_has_vce
90#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
91#endif
92#ifndef cpu_has_cache_cdex_p
93#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
94#endif
95#ifndef cpu_has_cache_cdex_s
96#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
97#endif
98#ifndef cpu_has_prefetch
99#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
100#endif
101#ifndef cpu_has_mcheck
102#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
103#endif
104#ifndef cpu_has_ejtag
105#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
106#endif
107#ifndef cpu_has_llsc
108#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
109#endif
110#ifndef kernel_uses_llsc
111#define kernel_uses_llsc cpu_has_llsc
112#endif
113#ifndef cpu_has_mips16
114#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
115#endif
116#ifndef cpu_has_mdmx
117#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
118#endif
119#ifndef cpu_has_mips3d
120#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
121#endif
122#ifndef cpu_has_smartmips
123#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
124#endif
125
126#ifndef cpu_has_rixi
127# ifdef CONFIG_64BIT
128# define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
129# else /* CONFIG_32BIT */
130# define cpu_has_rixi ((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits)
131# endif
132#endif
133
134#ifndef cpu_has_mmips
135# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
136# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
137# else
138# define cpu_has_mmips 0
139# endif
140#endif
141
142#ifndef cpu_has_vtag_icache
143#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
144#endif
145#ifndef cpu_has_dc_aliases
146#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
147#endif
148#ifndef cpu_has_ic_fills_f_dc
149#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
150#endif
151#ifndef cpu_has_pindexed_dcache
152#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
153#endif
154#ifndef cpu_has_local_ebase
155#define cpu_has_local_ebase 1
156#endif
157
158/*
159 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
160 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
161 * don't. For maintaining I-cache coherency this means we need to flush the
162 * D-cache all the way back to whever the I-cache does refills from, so the
163 * I-cache has a chance to see the new data at all. Then we have to flush the
164 * I-cache also.
165 * Note we may have been rescheduled and may no longer be running on the CPU
166 * that did the store so we can't optimize this into only doing the flush on
167 * the local CPU.
168 */
169#ifndef cpu_icache_snoops_remote_store
170#ifdef CONFIG_SMP
171#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
172#else
173#define cpu_icache_snoops_remote_store 1
174#endif
175#endif
176
177#ifndef cpu_has_mips_1
178# define cpu_has_mips_1 (!cpu_has_mips_r6)
179#endif
180#ifndef cpu_has_mips_2
181# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
182#endif
183#ifndef cpu_has_mips_3
184# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
185#endif
186#ifndef cpu_has_mips_4
187# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
188#endif
189#ifndef cpu_has_mips_5
190# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
191#endif
192#ifndef cpu_has_mips32r1
193# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
194#endif
195#ifndef cpu_has_mips32r2
196# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
197#endif
198#ifndef cpu_has_mips32r6
199# define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
200#endif
201#ifndef cpu_has_mips64r1
202# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
203#endif
204#ifndef cpu_has_mips64r2
205# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
206#endif
207#ifndef cpu_has_mips64r6
208# define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
209#endif
210
211/*
212 * Shortcuts ...
213 */
214#define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5)
215#define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5)
216#define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5)
217
218#define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
219#define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r)
220#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
221#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
222
223#define cpu_has_mips_4_5_r2_r6 (cpu_has_mips_4_5 | cpu_has_mips_r2 | \
224 cpu_has_mips_r6)
225
226#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
227#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
228#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
229#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
230#define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
231#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
232 cpu_has_mips32r6 | cpu_has_mips64r1 | \
233 cpu_has_mips64r2 | cpu_has_mips64r6)
234
235/* MIPSR2 and MIPSR6 have a lot of similarities */
236#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6)
237
238#ifndef cpu_has_mips_r2_exec_hazard
239#define cpu_has_mips_r2_exec_hazard (cpu_has_mips_r2 | cpu_has_mips_r6)
240#endif
241
242/*
243 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
244 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
245 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
246 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
247 */
248#ifndef cpu_has_clo_clz
249#define cpu_has_clo_clz cpu_has_mips_r
250#endif
251
252/*
253 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
254 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
255 * This indicates the availability of WSBH and in case of 64 bit CPUs also
256 * DSBH and DSHD.
257 */
258#ifndef cpu_has_wsbh
259#define cpu_has_wsbh cpu_has_mips_r2
260#endif
261
262#ifndef cpu_has_dsp
263#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
264#endif
265
266#ifndef cpu_has_dsp2
267#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
268#endif
269
270#ifndef cpu_has_mipsmt
271#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
272#endif
273
274#ifndef cpu_has_userlocal
275#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
276#endif
277
278#ifdef CONFIG_32BIT
279# ifndef cpu_has_nofpuex
280# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
281# endif
282# ifndef cpu_has_64bits
283# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
284# endif
285# ifndef cpu_has_64bit_zero_reg
286# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
287# endif
288# ifndef cpu_has_64bit_gp_regs
289# define cpu_has_64bit_gp_regs 0
290# endif
291# ifndef cpu_has_64bit_addresses
292# define cpu_has_64bit_addresses 0
293# endif
294# ifndef cpu_vmbits
295# define cpu_vmbits 31
296# endif
297#endif
298
299#ifdef CONFIG_64BIT
300# ifndef cpu_has_nofpuex
301# define cpu_has_nofpuex 0
302# endif
303# ifndef cpu_has_64bits
304# define cpu_has_64bits 1
305# endif
306# ifndef cpu_has_64bit_zero_reg
307# define cpu_has_64bit_zero_reg 1
308# endif
309# ifndef cpu_has_64bit_gp_regs
310# define cpu_has_64bit_gp_regs 1
311# endif
312# ifndef cpu_has_64bit_addresses
313# define cpu_has_64bit_addresses 1
314# endif
315# ifndef cpu_vmbits
316# define cpu_vmbits cpu_data[0].vmbits
317# define __NEED_VMBITS_PROBE
318# endif
319#endif
320
321#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
322# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
323#elif !defined(cpu_has_vint)
324# define cpu_has_vint 0
325#endif
326
327#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
328# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
329#elif !defined(cpu_has_veic)
330# define cpu_has_veic 0
331#endif
332
333#ifndef cpu_has_inclusive_pcaches
334#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
335#endif
336
337#ifndef cpu_dcache_line_size
338#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
339#endif
340#ifndef cpu_icache_line_size
341#define cpu_icache_line_size() cpu_data[0].icache.linesz
342#endif
343#ifndef cpu_scache_line_size
344#define cpu_scache_line_size() cpu_data[0].scache.linesz
345#endif
346
347#ifndef cpu_hwrena_impl_bits
348#define cpu_hwrena_impl_bits 0
349#endif
350
351#ifndef cpu_has_perf_cntr_intr_bit
352#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
353#endif
354
355#ifndef cpu_has_vz
356#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
357#endif
358
359#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
360# define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA)
361#elif !defined(cpu_has_msa)
362# define cpu_has_msa 0
363#endif
364
365#ifndef cpu_has_fre
366# define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE)
367#endif
368
369#endif /* __ASM_CPU_FEATURES_H */