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1/*
2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef _LINUX_NVME_H
20#define _LINUX_NVME_H
21
22#include <linux/types.h>
23
24struct nvme_bar {
25 __u64 cap; /* Controller Capabilities */
26 __u32 vs; /* Version */
27 __u32 intms; /* Interrupt Mask Set */
28 __u32 intmc; /* Interrupt Mask Clear */
29 __u32 cc; /* Controller Configuration */
30 __u32 rsvd1; /* Reserved */
31 __u32 csts; /* Controller Status */
32 __u32 rsvd2; /* Reserved */
33 __u32 aqa; /* Admin Queue Attributes */
34 __u64 asq; /* Admin SQ Base Address */
35 __u64 acq; /* Admin CQ Base Address */
36};
37
38#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
39#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
40#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
41#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
42
43enum {
44 NVME_CC_ENABLE = 1 << 0,
45 NVME_CC_CSS_NVM = 0 << 4,
46 NVME_CC_MPS_SHIFT = 7,
47 NVME_CC_ARB_RR = 0 << 11,
48 NVME_CC_ARB_WRRU = 1 << 11,
49 NVME_CC_ARB_VS = 7 << 11,
50 NVME_CC_SHN_NONE = 0 << 14,
51 NVME_CC_SHN_NORMAL = 1 << 14,
52 NVME_CC_SHN_ABRUPT = 2 << 14,
53 NVME_CC_IOSQES = 6 << 16,
54 NVME_CC_IOCQES = 4 << 20,
55 NVME_CSTS_RDY = 1 << 0,
56 NVME_CSTS_CFS = 1 << 1,
57 NVME_CSTS_SHST_NORMAL = 0 << 2,
58 NVME_CSTS_SHST_OCCUR = 1 << 2,
59 NVME_CSTS_SHST_CMPLT = 2 << 2,
60};
61
62struct nvme_id_power_state {
63 __le16 max_power; /* centiwatts */
64 __u16 rsvd2;
65 __le32 entry_lat; /* microseconds */
66 __le32 exit_lat; /* microseconds */
67 __u8 read_tput;
68 __u8 read_lat;
69 __u8 write_tput;
70 __u8 write_lat;
71 __u8 rsvd16[16];
72};
73
74#define NVME_VS(major, minor) (major << 16 | minor)
75
76struct nvme_id_ctrl {
77 __le16 vid;
78 __le16 ssvid;
79 char sn[20];
80 char mn[40];
81 char fr[8];
82 __u8 rab;
83 __u8 ieee[3];
84 __u8 mic;
85 __u8 mdts;
86 __u8 rsvd78[178];
87 __le16 oacs;
88 __u8 acl;
89 __u8 aerl;
90 __u8 frmw;
91 __u8 lpa;
92 __u8 elpe;
93 __u8 npss;
94 __u8 rsvd264[248];
95 __u8 sqes;
96 __u8 cqes;
97 __u8 rsvd514[2];
98 __le32 nn;
99 __le16 oncs;
100 __le16 fuses;
101 __u8 fna;
102 __u8 vwc;
103 __le16 awun;
104 __le16 awupf;
105 __u8 rsvd530[1518];
106 struct nvme_id_power_state psd[32];
107 __u8 vs[1024];
108};
109
110struct nvme_lbaf {
111 __le16 ms;
112 __u8 ds;
113 __u8 rp;
114};
115
116struct nvme_id_ns {
117 __le64 nsze;
118 __le64 ncap;
119 __le64 nuse;
120 __u8 nsfeat;
121 __u8 nlbaf;
122 __u8 flbas;
123 __u8 mc;
124 __u8 dpc;
125 __u8 dps;
126 __u8 rsvd30[98];
127 struct nvme_lbaf lbaf[16];
128 __u8 rsvd192[192];
129 __u8 vs[3712];
130};
131
132enum {
133 NVME_NS_FEAT_THIN = 1 << 0,
134 NVME_LBAF_RP_BEST = 0,
135 NVME_LBAF_RP_BETTER = 1,
136 NVME_LBAF_RP_GOOD = 2,
137 NVME_LBAF_RP_DEGRADED = 3,
138};
139
140struct nvme_smart_log {
141 __u8 critical_warning;
142 __u8 temperature[2];
143 __u8 avail_spare;
144 __u8 spare_thresh;
145 __u8 percent_used;
146 __u8 rsvd6[26];
147 __u8 data_units_read[16];
148 __u8 data_units_written[16];
149 __u8 host_reads[16];
150 __u8 host_writes[16];
151 __u8 ctrl_busy_time[16];
152 __u8 power_cycles[16];
153 __u8 power_on_hours[16];
154 __u8 unsafe_shutdowns[16];
155 __u8 media_errors[16];
156 __u8 num_err_log_entries[16];
157 __u8 rsvd192[320];
158};
159
160enum {
161 NVME_SMART_CRIT_SPARE = 1 << 0,
162 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
163 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
164 NVME_SMART_CRIT_MEDIA = 1 << 3,
165 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
166};
167
168struct nvme_lba_range_type {
169 __u8 type;
170 __u8 attributes;
171 __u8 rsvd2[14];
172 __u64 slba;
173 __u64 nlb;
174 __u8 guid[16];
175 __u8 rsvd48[16];
176};
177
178enum {
179 NVME_LBART_TYPE_FS = 0x01,
180 NVME_LBART_TYPE_RAID = 0x02,
181 NVME_LBART_TYPE_CACHE = 0x03,
182 NVME_LBART_TYPE_SWAP = 0x04,
183
184 NVME_LBART_ATTRIB_TEMP = 1 << 0,
185 NVME_LBART_ATTRIB_HIDE = 1 << 1,
186};
187
188/* I/O commands */
189
190enum nvme_opcode {
191 nvme_cmd_flush = 0x00,
192 nvme_cmd_write = 0x01,
193 nvme_cmd_read = 0x02,
194 nvme_cmd_write_uncor = 0x04,
195 nvme_cmd_compare = 0x05,
196 nvme_cmd_dsm = 0x09,
197};
198
199struct nvme_common_command {
200 __u8 opcode;
201 __u8 flags;
202 __u16 command_id;
203 __le32 nsid;
204 __u32 cdw2[2];
205 __le64 metadata;
206 __le64 prp1;
207 __le64 prp2;
208 __u32 cdw10[6];
209};
210
211struct nvme_rw_command {
212 __u8 opcode;
213 __u8 flags;
214 __u16 command_id;
215 __le32 nsid;
216 __u64 rsvd2;
217 __le64 metadata;
218 __le64 prp1;
219 __le64 prp2;
220 __le64 slba;
221 __le16 length;
222 __le16 control;
223 __le32 dsmgmt;
224 __le32 reftag;
225 __le16 apptag;
226 __le16 appmask;
227};
228
229enum {
230 NVME_RW_LR = 1 << 15,
231 NVME_RW_FUA = 1 << 14,
232 NVME_RW_DSM_FREQ_UNSPEC = 0,
233 NVME_RW_DSM_FREQ_TYPICAL = 1,
234 NVME_RW_DSM_FREQ_RARE = 2,
235 NVME_RW_DSM_FREQ_READS = 3,
236 NVME_RW_DSM_FREQ_WRITES = 4,
237 NVME_RW_DSM_FREQ_RW = 5,
238 NVME_RW_DSM_FREQ_ONCE = 6,
239 NVME_RW_DSM_FREQ_PREFETCH = 7,
240 NVME_RW_DSM_FREQ_TEMP = 8,
241 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
242 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
243 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
244 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
245 NVME_RW_DSM_SEQ_REQ = 1 << 6,
246 NVME_RW_DSM_COMPRESSED = 1 << 7,
247};
248
249/* Admin commands */
250
251enum nvme_admin_opcode {
252 nvme_admin_delete_sq = 0x00,
253 nvme_admin_create_sq = 0x01,
254 nvme_admin_get_log_page = 0x02,
255 nvme_admin_delete_cq = 0x04,
256 nvme_admin_create_cq = 0x05,
257 nvme_admin_identify = 0x06,
258 nvme_admin_abort_cmd = 0x08,
259 nvme_admin_set_features = 0x09,
260 nvme_admin_get_features = 0x0a,
261 nvme_admin_async_event = 0x0c,
262 nvme_admin_activate_fw = 0x10,
263 nvme_admin_download_fw = 0x11,
264 nvme_admin_format_nvm = 0x80,
265 nvme_admin_security_send = 0x81,
266 nvme_admin_security_recv = 0x82,
267};
268
269enum {
270 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
271 NVME_CQ_IRQ_ENABLED = (1 << 1),
272 NVME_SQ_PRIO_URGENT = (0 << 1),
273 NVME_SQ_PRIO_HIGH = (1 << 1),
274 NVME_SQ_PRIO_MEDIUM = (2 << 1),
275 NVME_SQ_PRIO_LOW = (3 << 1),
276 NVME_FEAT_ARBITRATION = 0x01,
277 NVME_FEAT_POWER_MGMT = 0x02,
278 NVME_FEAT_LBA_RANGE = 0x03,
279 NVME_FEAT_TEMP_THRESH = 0x04,
280 NVME_FEAT_ERR_RECOVERY = 0x05,
281 NVME_FEAT_VOLATILE_WC = 0x06,
282 NVME_FEAT_NUM_QUEUES = 0x07,
283 NVME_FEAT_IRQ_COALESCE = 0x08,
284 NVME_FEAT_IRQ_CONFIG = 0x09,
285 NVME_FEAT_WRITE_ATOMIC = 0x0a,
286 NVME_FEAT_ASYNC_EVENT = 0x0b,
287 NVME_FEAT_SW_PROGRESS = 0x0c,
288};
289
290struct nvme_identify {
291 __u8 opcode;
292 __u8 flags;
293 __u16 command_id;
294 __le32 nsid;
295 __u64 rsvd2[2];
296 __le64 prp1;
297 __le64 prp2;
298 __le32 cns;
299 __u32 rsvd11[5];
300};
301
302struct nvme_features {
303 __u8 opcode;
304 __u8 flags;
305 __u16 command_id;
306 __le32 nsid;
307 __u64 rsvd2[2];
308 __le64 prp1;
309 __le64 prp2;
310 __le32 fid;
311 __le32 dword11;
312 __u32 rsvd12[4];
313};
314
315struct nvme_create_cq {
316 __u8 opcode;
317 __u8 flags;
318 __u16 command_id;
319 __u32 rsvd1[5];
320 __le64 prp1;
321 __u64 rsvd8;
322 __le16 cqid;
323 __le16 qsize;
324 __le16 cq_flags;
325 __le16 irq_vector;
326 __u32 rsvd12[4];
327};
328
329struct nvme_create_sq {
330 __u8 opcode;
331 __u8 flags;
332 __u16 command_id;
333 __u32 rsvd1[5];
334 __le64 prp1;
335 __u64 rsvd8;
336 __le16 sqid;
337 __le16 qsize;
338 __le16 sq_flags;
339 __le16 cqid;
340 __u32 rsvd12[4];
341};
342
343struct nvme_delete_queue {
344 __u8 opcode;
345 __u8 flags;
346 __u16 command_id;
347 __u32 rsvd1[9];
348 __le16 qid;
349 __u16 rsvd10;
350 __u32 rsvd11[5];
351};
352
353struct nvme_download_firmware {
354 __u8 opcode;
355 __u8 flags;
356 __u16 command_id;
357 __u32 rsvd1[5];
358 __le64 prp1;
359 __le64 prp2;
360 __le32 numd;
361 __le32 offset;
362 __u32 rsvd12[4];
363};
364
365struct nvme_command {
366 union {
367 struct nvme_common_command common;
368 struct nvme_rw_command rw;
369 struct nvme_identify identify;
370 struct nvme_features features;
371 struct nvme_create_cq create_cq;
372 struct nvme_create_sq create_sq;
373 struct nvme_delete_queue delete_queue;
374 struct nvme_download_firmware dlfw;
375 };
376};
377
378enum {
379 NVME_SC_SUCCESS = 0x0,
380 NVME_SC_INVALID_OPCODE = 0x1,
381 NVME_SC_INVALID_FIELD = 0x2,
382 NVME_SC_CMDID_CONFLICT = 0x3,
383 NVME_SC_DATA_XFER_ERROR = 0x4,
384 NVME_SC_POWER_LOSS = 0x5,
385 NVME_SC_INTERNAL = 0x6,
386 NVME_SC_ABORT_REQ = 0x7,
387 NVME_SC_ABORT_QUEUE = 0x8,
388 NVME_SC_FUSED_FAIL = 0x9,
389 NVME_SC_FUSED_MISSING = 0xa,
390 NVME_SC_INVALID_NS = 0xb,
391 NVME_SC_LBA_RANGE = 0x80,
392 NVME_SC_CAP_EXCEEDED = 0x81,
393 NVME_SC_NS_NOT_READY = 0x82,
394 NVME_SC_CQ_INVALID = 0x100,
395 NVME_SC_QID_INVALID = 0x101,
396 NVME_SC_QUEUE_SIZE = 0x102,
397 NVME_SC_ABORT_LIMIT = 0x103,
398 NVME_SC_ABORT_MISSING = 0x104,
399 NVME_SC_ASYNC_LIMIT = 0x105,
400 NVME_SC_FIRMWARE_SLOT = 0x106,
401 NVME_SC_FIRMWARE_IMAGE = 0x107,
402 NVME_SC_INVALID_VECTOR = 0x108,
403 NVME_SC_INVALID_LOG_PAGE = 0x109,
404 NVME_SC_INVALID_FORMAT = 0x10a,
405 NVME_SC_BAD_ATTRIBUTES = 0x180,
406 NVME_SC_WRITE_FAULT = 0x280,
407 NVME_SC_READ_ERROR = 0x281,
408 NVME_SC_GUARD_CHECK = 0x282,
409 NVME_SC_APPTAG_CHECK = 0x283,
410 NVME_SC_REFTAG_CHECK = 0x284,
411 NVME_SC_COMPARE_FAILED = 0x285,
412 NVME_SC_ACCESS_DENIED = 0x286,
413};
414
415struct nvme_completion {
416 __le32 result; /* Used by admin commands to return data */
417 __u32 rsvd;
418 __le16 sq_head; /* how much of this queue may be reclaimed */
419 __le16 sq_id; /* submission queue that generated this entry */
420 __u16 command_id; /* of the command which completed */
421 __le16 status; /* did the command fail, and if so, why? */
422};
423
424struct nvme_user_io {
425 __u8 opcode;
426 __u8 flags;
427 __u16 control;
428 __u16 nblocks;
429 __u16 rsvd;
430 __u64 metadata;
431 __u64 addr;
432 __u64 slba;
433 __u32 dsmgmt;
434 __u32 reftag;
435 __u16 apptag;
436 __u16 appmask;
437};
438
439struct nvme_admin_cmd {
440 __u8 opcode;
441 __u8 flags;
442 __u16 rsvd1;
443 __u32 nsid;
444 __u32 cdw2;
445 __u32 cdw3;
446 __u64 metadata;
447 __u64 addr;
448 __u32 metadata_len;
449 __u32 data_len;
450 __u32 cdw10;
451 __u32 cdw11;
452 __u32 cdw12;
453 __u32 cdw13;
454 __u32 cdw14;
455 __u32 cdw15;
456 __u32 timeout_ms;
457 __u32 result;
458};
459
460#define NVME_IOCTL_ID _IO('N', 0x40)
461#define NVME_IOCTL_ADMIN_CMD _IOWR('N', 0x41, struct nvme_admin_cmd)
462#define NVME_IOCTL_SUBMIT_IO _IOW('N', 0x42, struct nvme_user_io)
463
464#endif /* _LINUX_NVME_H */