tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom
kernel / include / linux / mfd / palmas.h
at v3.9 2845 lines 112 kB view raw
1/* 2 * TI Palmas 3 * 4 * Copyright 2011 Texas Instruments Inc. 5 * 6 * Author: Graeme Gregory <gg@slimlogic.co.uk> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 15#ifndef __LINUX_MFD_PALMAS_H 16#define __LINUX_MFD_PALMAS_H 17 18#include <linux/usb/otg.h> 19#include <linux/leds.h> 20#include <linux/regmap.h> 21#include <linux/regulator/driver.h> 22 23#define PALMAS_NUM_CLIENTS 3 24 25struct palmas_pmic; 26struct palmas_gpadc; 27struct palmas_resource; 28struct palmas_usb; 29 30struct palmas { 31 struct device *dev; 32 33 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS]; 34 struct regmap *regmap[PALMAS_NUM_CLIENTS]; 35 36 /* Stored chip id */ 37 int id; 38 39 /* IRQ Data */ 40 int irq; 41 u32 irq_mask; 42 struct mutex irq_lock; 43 struct regmap_irq_chip_data *irq_data; 44 45 /* Child Devices */ 46 struct palmas_pmic *pmic; 47 struct palmas_gpadc *gpadc; 48 struct palmas_resource *resource; 49 struct palmas_usb *usb; 50 51 /* GPIO MUXing */ 52 u8 gpio_muxed; 53 u8 led_muxed; 54 u8 pwm_muxed; 55}; 56 57struct palmas_gpadc_platform_data { 58 /* Channel 3 current source is only enabled during conversion */ 59 int ch3_current; 60 61 /* Channel 0 current source can be used for battery detection. 62 * If used for battery detection this will cause a permanent current 63 * consumption depending on current level set here. 64 */ 65 int ch0_current; 66 67 /* default BAT_REMOVAL_DAT setting on device probe */ 68 int bat_removal; 69 70 /* Sets the START_POLARITY bit in the RT_CTRL register */ 71 int start_polarity; 72}; 73 74struct palmas_reg_init { 75 /* warm_rest controls the voltage levels after a warm reset 76 * 77 * 0: reload default values from OTP on warm reset 78 * 1: maintain voltage from VSEL on warm reset 79 */ 80 int warm_reset; 81 82 /* roof_floor controls whether the regulator uses the i2c style 83 * of DVS or uses the method where a GPIO or other control method is 84 * attached to the NSLEEP/ENABLE1/ENABLE2 pins 85 * 86 * For SMPS 87 * 88 * 0: i2c selection of voltage 89 * 1: pin selection of voltage. 90 * 91 * For LDO unused 92 */ 93 int roof_floor; 94 95 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in 96 * the data sheet. 97 * 98 * For SMPS 99 * 100 * 0: Off 101 * 1: AUTO 102 * 2: ECO 103 * 3: Forced PWM 104 * 105 * For LDO 106 * 107 * 0: Off 108 * 1: On 109 */ 110 int mode_sleep; 111 112 /* tstep is the timestep loaded to the TSTEP register 113 * 114 * For SMPS 115 * 116 * 0: Jump (no slope control) 117 * 1: 10mV/us 118 * 2: 5mV/us 119 * 3: 2.5mV/us 120 * 121 * For LDO unused 122 */ 123 int tstep; 124 125 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE 126 * register. Set this is the default voltage set in OTP needs 127 * to be overridden. 128 */ 129 u8 vsel; 130 131}; 132 133enum palmas_regulators { 134 /* SMPS regulators */ 135 PALMAS_REG_SMPS12, 136 PALMAS_REG_SMPS123, 137 PALMAS_REG_SMPS3, 138 PALMAS_REG_SMPS45, 139 PALMAS_REG_SMPS457, 140 PALMAS_REG_SMPS6, 141 PALMAS_REG_SMPS7, 142 PALMAS_REG_SMPS8, 143 PALMAS_REG_SMPS9, 144 PALMAS_REG_SMPS10, 145 /* LDO regulators */ 146 PALMAS_REG_LDO1, 147 PALMAS_REG_LDO2, 148 PALMAS_REG_LDO3, 149 PALMAS_REG_LDO4, 150 PALMAS_REG_LDO5, 151 PALMAS_REG_LDO6, 152 PALMAS_REG_LDO7, 153 PALMAS_REG_LDO8, 154 PALMAS_REG_LDO9, 155 PALMAS_REG_LDOLN, 156 PALMAS_REG_LDOUSB, 157 /* Total number of regulators */ 158 PALMAS_NUM_REGS, 159}; 160 161struct palmas_pmic_platform_data { 162 /* An array of pointers to regulator init data indexed by regulator 163 * ID 164 */ 165 struct regulator_init_data *reg_data[PALMAS_NUM_REGS]; 166 167 /* An array of pointers to structures containing sleep mode and DVS 168 * configuration for regulators indexed by ID 169 */ 170 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS]; 171 172 /* use LDO6 for vibrator control */ 173 int ldo6_vibrator; 174}; 175 176struct palmas_usb_platform_data { 177 /* Set this if platform wishes its own vbus control */ 178 int no_control_vbus; 179 180 /* Do we enable the wakeup comparator on probe */ 181 int wakeup; 182}; 183 184struct palmas_resource_platform_data { 185 int regen1_mode_sleep; 186 int regen2_mode_sleep; 187 int sysen1_mode_sleep; 188 int sysen2_mode_sleep; 189 190 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */ 191 u8 nsleep_res; 192 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */ 193 u8 nsleep_smps; 194 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */ 195 u8 nsleep_ldo1; 196 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */ 197 u8 nsleep_ldo2; 198 199 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */ 200 u8 enable1_res; 201 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */ 202 u8 enable1_smps; 203 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */ 204 u8 enable1_ldo1; 205 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */ 206 u8 enable1_ldo2; 207 208 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */ 209 u8 enable2_res; 210 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */ 211 u8 enable2_smps; 212 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */ 213 u8 enable2_ldo1; 214 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */ 215 u8 enable2_ldo2; 216}; 217 218struct palmas_clk_platform_data { 219 int clk32kg_mode_sleep; 220 int clk32kgaudio_mode_sleep; 221}; 222 223struct palmas_platform_data { 224 int irq_flags; 225 int gpio_base; 226 227 /* bit value to be loaded to the POWER_CTRL register */ 228 u8 power_ctrl; 229 230 /* 231 * boolean to select if we want to configure muxing here 232 * then the two value to load into the registers if true 233 */ 234 int mux_from_pdata; 235 u8 pad1, pad2; 236 237 struct palmas_pmic_platform_data *pmic_pdata; 238 struct palmas_gpadc_platform_data *gpadc_pdata; 239 struct palmas_usb_platform_data *usb_pdata; 240 struct palmas_resource_platform_data *resource_pdata; 241 struct palmas_clk_platform_data *clk_pdata; 242}; 243 244struct palmas_gpadc_calibration { 245 s32 gain; 246 s32 gain_error; 247 s32 offset_error; 248}; 249 250struct palmas_gpadc { 251 struct device *dev; 252 struct palmas *palmas; 253 254 int ch3_current; 255 int ch0_current; 256 257 int gpadc_force; 258 259 int bat_removal; 260 261 struct mutex reading_lock; 262 struct completion irq_complete; 263 264 int eoc_sw_irq; 265 266 struct palmas_gpadc_calibration *palmas_cal_tbl; 267 268 int conv0_channel; 269 int conv1_channel; 270 int rt_channel; 271}; 272 273struct palmas_gpadc_result { 274 s32 raw_code; 275 s32 corrected_code; 276 s32 result; 277}; 278 279#define PALMAS_MAX_CHANNELS 16 280 281/* Define the palmas IRQ numbers */ 282enum palmas_irqs { 283 /* INT1 registers */ 284 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ, 285 PALMAS_PWRON_IRQ, 286 PALMAS_LONG_PRESS_KEY_IRQ, 287 PALMAS_RPWRON_IRQ, 288 PALMAS_PWRDOWN_IRQ, 289 PALMAS_HOTDIE_IRQ, 290 PALMAS_VSYS_MON_IRQ, 291 PALMAS_VBAT_MON_IRQ, 292 /* INT2 registers */ 293 PALMAS_RTC_ALARM_IRQ, 294 PALMAS_RTC_TIMER_IRQ, 295 PALMAS_WDT_IRQ, 296 PALMAS_BATREMOVAL_IRQ, 297 PALMAS_RESET_IN_IRQ, 298 PALMAS_FBI_BB_IRQ, 299 PALMAS_SHORT_IRQ, 300 PALMAS_VAC_ACOK_IRQ, 301 /* INT3 registers */ 302 PALMAS_GPADC_AUTO_0_IRQ, 303 PALMAS_GPADC_AUTO_1_IRQ, 304 PALMAS_GPADC_EOC_SW_IRQ, 305 PALMAS_GPADC_EOC_RT_IRQ, 306 PALMAS_ID_OTG_IRQ, 307 PALMAS_ID_IRQ, 308 PALMAS_VBUS_OTG_IRQ, 309 PALMAS_VBUS_IRQ, 310 /* INT4 registers */ 311 PALMAS_GPIO_0_IRQ, 312 PALMAS_GPIO_1_IRQ, 313 PALMAS_GPIO_2_IRQ, 314 PALMAS_GPIO_3_IRQ, 315 PALMAS_GPIO_4_IRQ, 316 PALMAS_GPIO_5_IRQ, 317 PALMAS_GPIO_6_IRQ, 318 PALMAS_GPIO_7_IRQ, 319 /* Total Number IRQs */ 320 PALMAS_NUM_IRQ, 321}; 322 323struct palmas_pmic { 324 struct palmas *palmas; 325 struct device *dev; 326 struct regulator_desc desc[PALMAS_NUM_REGS]; 327 struct regulator_dev *rdev[PALMAS_NUM_REGS]; 328 struct mutex mutex; 329 330 int smps123; 331 int smps457; 332 333 int range[PALMAS_REG_SMPS10]; 334}; 335 336struct palmas_resource { 337 struct palmas *palmas; 338 struct device *dev; 339}; 340 341struct palmas_usb { 342 struct palmas *palmas; 343 struct device *dev; 344 345 /* for vbus reporting with irqs disabled */ 346 spinlock_t lock; 347 348 struct regulator *vbus_reg; 349 350 /* used to set vbus, in atomic path */ 351 struct work_struct set_vbus_work; 352 353 int irq1; 354 int irq2; 355 int irq3; 356 int irq4; 357 358 int vbus_enable; 359 360 u8 linkstat; 361}; 362 363#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator) 364 365enum usb_irq_events { 366 /* Wakeup events from INT3 */ 367 PALMAS_USB_ID_WAKEPUP, 368 PALMAS_USB_VBUS_WAKEUP, 369 370 /* ID_OTG_EVENTS */ 371 PALMAS_USB_ID_GND, 372 N_PALMAS_USB_ID_GND, 373 PALMAS_USB_ID_C, 374 N_PALMAS_USB_ID_C, 375 PALMAS_USB_ID_B, 376 N_PALMAS_USB_ID_B, 377 PALMAS_USB_ID_A, 378 N_PALMAS_USB_ID_A, 379 PALMAS_USB_ID_FLOAT, 380 N_PALMAS_USB_ID_FLOAT, 381 382 /* VBUS_OTG_EVENTS */ 383 PALMAS_USB_VB_SESS_END, 384 N_PALMAS_USB_VB_SESS_END, 385 PALMAS_USB_VB_SESS_VLD, 386 N_PALMAS_USB_VB_SESS_VLD, 387 PALMAS_USB_VA_SESS_VLD, 388 N_PALMAS_USB_VA_SESS_VLD, 389 PALMAS_USB_VA_VBUS_VLD, 390 N_PALMAS_USB_VA_VBUS_VLD, 391 PALMAS_USB_VADP_SNS, 392 N_PALMAS_USB_VADP_SNS, 393 PALMAS_USB_VADP_PRB, 394 N_PALMAS_USB_VADP_PRB, 395 PALMAS_USB_VOTG_SESS_VLD, 396 N_PALMAS_USB_VOTG_SESS_VLD, 397}; 398 399/* defines so we can store the mux settings */ 400#define PALMAS_GPIO_0_MUXED (1 << 0) 401#define PALMAS_GPIO_1_MUXED (1 << 1) 402#define PALMAS_GPIO_2_MUXED (1 << 2) 403#define PALMAS_GPIO_3_MUXED (1 << 3) 404#define PALMAS_GPIO_4_MUXED (1 << 4) 405#define PALMAS_GPIO_5_MUXED (1 << 5) 406#define PALMAS_GPIO_6_MUXED (1 << 6) 407#define PALMAS_GPIO_7_MUXED (1 << 7) 408 409#define PALMAS_LED1_MUXED (1 << 0) 410#define PALMAS_LED2_MUXED (1 << 1) 411 412#define PALMAS_PWM1_MUXED (1 << 0) 413#define PALMAS_PWM2_MUXED (1 << 1) 414 415/* helper macro to get correct slave number */ 416#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1) 417#define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y) 418 419/* Base addresses of IP blocks in Palmas */ 420#define PALMAS_SMPS_DVS_BASE 0x20 421#define PALMAS_RTC_BASE 0x100 422#define PALMAS_VALIDITY_BASE 0x118 423#define PALMAS_SMPS_BASE 0x120 424#define PALMAS_LDO_BASE 0x150 425#define PALMAS_DVFS_BASE 0x180 426#define PALMAS_PMU_CONTROL_BASE 0x1A0 427#define PALMAS_RESOURCE_BASE 0x1D4 428#define PALMAS_PU_PD_OD_BASE 0x1F4 429#define PALMAS_LED_BASE 0x200 430#define PALMAS_INTERRUPT_BASE 0x210 431#define PALMAS_USB_OTG_BASE 0x250 432#define PALMAS_VIBRATOR_BASE 0x270 433#define PALMAS_GPIO_BASE 0x280 434#define PALMAS_USB_BASE 0x290 435#define PALMAS_GPADC_BASE 0x2C0 436#define PALMAS_TRIM_GPADC_BASE 0x3CD 437 438/* Registers for function RTC */ 439#define PALMAS_SECONDS_REG 0x0 440#define PALMAS_MINUTES_REG 0x1 441#define PALMAS_HOURS_REG 0x2 442#define PALMAS_DAYS_REG 0x3 443#define PALMAS_MONTHS_REG 0x4 444#define PALMAS_YEARS_REG 0x5 445#define PALMAS_WEEKS_REG 0x6 446#define PALMAS_ALARM_SECONDS_REG 0x8 447#define PALMAS_ALARM_MINUTES_REG 0x9 448#define PALMAS_ALARM_HOURS_REG 0xA 449#define PALMAS_ALARM_DAYS_REG 0xB 450#define PALMAS_ALARM_MONTHS_REG 0xC 451#define PALMAS_ALARM_YEARS_REG 0xD 452#define PALMAS_RTC_CTRL_REG 0x10 453#define PALMAS_RTC_STATUS_REG 0x11 454#define PALMAS_RTC_INTERRUPTS_REG 0x12 455#define PALMAS_RTC_COMP_LSB_REG 0x13 456#define PALMAS_RTC_COMP_MSB_REG 0x14 457#define PALMAS_RTC_RES_PROG_REG 0x15 458#define PALMAS_RTC_RESET_STATUS_REG 0x16 459 460/* Bit definitions for SECONDS_REG */ 461#define PALMAS_SECONDS_REG_SEC1_MASK 0x70 462#define PALMAS_SECONDS_REG_SEC1_SHIFT 4 463#define PALMAS_SECONDS_REG_SEC0_MASK 0x0f 464#define PALMAS_SECONDS_REG_SEC0_SHIFT 0 465 466/* Bit definitions for MINUTES_REG */ 467#define PALMAS_MINUTES_REG_MIN1_MASK 0x70 468#define PALMAS_MINUTES_REG_MIN1_SHIFT 4 469#define PALMAS_MINUTES_REG_MIN0_MASK 0x0f 470#define PALMAS_MINUTES_REG_MIN0_SHIFT 0 471 472/* Bit definitions for HOURS_REG */ 473#define PALMAS_HOURS_REG_PM_NAM 0x80 474#define PALMAS_HOURS_REG_PM_NAM_SHIFT 7 475#define PALMAS_HOURS_REG_HOUR1_MASK 0x30 476#define PALMAS_HOURS_REG_HOUR1_SHIFT 4 477#define PALMAS_HOURS_REG_HOUR0_MASK 0x0f 478#define PALMAS_HOURS_REG_HOUR0_SHIFT 0 479 480/* Bit definitions for DAYS_REG */ 481#define PALMAS_DAYS_REG_DAY1_MASK 0x30 482#define PALMAS_DAYS_REG_DAY1_SHIFT 4 483#define PALMAS_DAYS_REG_DAY0_MASK 0x0f 484#define PALMAS_DAYS_REG_DAY0_SHIFT 0 485 486/* Bit definitions for MONTHS_REG */ 487#define PALMAS_MONTHS_REG_MONTH1 0x10 488#define PALMAS_MONTHS_REG_MONTH1_SHIFT 4 489#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f 490#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0 491 492/* Bit definitions for YEARS_REG */ 493#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0 494#define PALMAS_YEARS_REG_YEAR1_SHIFT 4 495#define PALMAS_YEARS_REG_YEAR0_MASK 0x0f 496#define PALMAS_YEARS_REG_YEAR0_SHIFT 0 497 498/* Bit definitions for WEEKS_REG */ 499#define PALMAS_WEEKS_REG_WEEK_MASK 0x07 500#define PALMAS_WEEKS_REG_WEEK_SHIFT 0 501 502/* Bit definitions for ALARM_SECONDS_REG */ 503#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70 504#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4 505#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f 506#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0 507 508/* Bit definitions for ALARM_MINUTES_REG */ 509#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70 510#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4 511#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f 512#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0 513 514/* Bit definitions for ALARM_HOURS_REG */ 515#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80 516#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7 517#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30 518#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4 519#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f 520#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0 521 522/* Bit definitions for ALARM_DAYS_REG */ 523#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30 524#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4 525#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f 526#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0 527 528/* Bit definitions for ALARM_MONTHS_REG */ 529#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10 530#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4 531#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f 532#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0 533 534/* Bit definitions for ALARM_YEARS_REG */ 535#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0 536#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4 537#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f 538#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0 539 540/* Bit definitions for RTC_CTRL_REG */ 541#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80 542#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7 543#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40 544#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6 545#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20 546#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5 547#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10 548#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4 549#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08 550#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3 551#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04 552#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2 553#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02 554#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1 555#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01 556#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0 557 558/* Bit definitions for RTC_STATUS_REG */ 559#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80 560#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7 561#define PALMAS_RTC_STATUS_REG_ALARM 0x40 562#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6 563#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20 564#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5 565#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10 566#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4 567#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08 568#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3 569#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04 570#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2 571#define PALMAS_RTC_STATUS_REG_RUN 0x02 572#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1 573 574/* Bit definitions for RTC_INTERRUPTS_REG */ 575#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10 576#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4 577#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08 578#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3 579#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04 580#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2 581#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03 582#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0 583 584/* Bit definitions for RTC_COMP_LSB_REG */ 585#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff 586#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0 587 588/* Bit definitions for RTC_COMP_MSB_REG */ 589#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff 590#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0 591 592/* Bit definitions for RTC_RES_PROG_REG */ 593#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f 594#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0 595 596/* Bit definitions for RTC_RESET_STATUS_REG */ 597#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01 598#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0 599 600/* Registers for function BACKUP */ 601#define PALMAS_BACKUP0 0x0 602#define PALMAS_BACKUP1 0x1 603#define PALMAS_BACKUP2 0x2 604#define PALMAS_BACKUP3 0x3 605#define PALMAS_BACKUP4 0x4 606#define PALMAS_BACKUP5 0x5 607#define PALMAS_BACKUP6 0x6 608#define PALMAS_BACKUP7 0x7 609 610/* Bit definitions for BACKUP0 */ 611#define PALMAS_BACKUP0_BACKUP_MASK 0xff 612#define PALMAS_BACKUP0_BACKUP_SHIFT 0 613 614/* Bit definitions for BACKUP1 */ 615#define PALMAS_BACKUP1_BACKUP_MASK 0xff 616#define PALMAS_BACKUP1_BACKUP_SHIFT 0 617 618/* Bit definitions for BACKUP2 */ 619#define PALMAS_BACKUP2_BACKUP_MASK 0xff 620#define PALMAS_BACKUP2_BACKUP_SHIFT 0 621 622/* Bit definitions for BACKUP3 */ 623#define PALMAS_BACKUP3_BACKUP_MASK 0xff 624#define PALMAS_BACKUP3_BACKUP_SHIFT 0 625 626/* Bit definitions for BACKUP4 */ 627#define PALMAS_BACKUP4_BACKUP_MASK 0xff 628#define PALMAS_BACKUP4_BACKUP_SHIFT 0 629 630/* Bit definitions for BACKUP5 */ 631#define PALMAS_BACKUP5_BACKUP_MASK 0xff 632#define PALMAS_BACKUP5_BACKUP_SHIFT 0 633 634/* Bit definitions for BACKUP6 */ 635#define PALMAS_BACKUP6_BACKUP_MASK 0xff 636#define PALMAS_BACKUP6_BACKUP_SHIFT 0 637 638/* Bit definitions for BACKUP7 */ 639#define PALMAS_BACKUP7_BACKUP_MASK 0xff 640#define PALMAS_BACKUP7_BACKUP_SHIFT 0 641 642/* Registers for function SMPS */ 643#define PALMAS_SMPS12_CTRL 0x0 644#define PALMAS_SMPS12_TSTEP 0x1 645#define PALMAS_SMPS12_FORCE 0x2 646#define PALMAS_SMPS12_VOLTAGE 0x3 647#define PALMAS_SMPS3_CTRL 0x4 648#define PALMAS_SMPS3_VOLTAGE 0x7 649#define PALMAS_SMPS45_CTRL 0x8 650#define PALMAS_SMPS45_TSTEP 0x9 651#define PALMAS_SMPS45_FORCE 0xA 652#define PALMAS_SMPS45_VOLTAGE 0xB 653#define PALMAS_SMPS6_CTRL 0xC 654#define PALMAS_SMPS6_TSTEP 0xD 655#define PALMAS_SMPS6_FORCE 0xE 656#define PALMAS_SMPS6_VOLTAGE 0xF 657#define PALMAS_SMPS7_CTRL 0x10 658#define PALMAS_SMPS7_VOLTAGE 0x13 659#define PALMAS_SMPS8_CTRL 0x14 660#define PALMAS_SMPS8_TSTEP 0x15 661#define PALMAS_SMPS8_FORCE 0x16 662#define PALMAS_SMPS8_VOLTAGE 0x17 663#define PALMAS_SMPS9_CTRL 0x18 664#define PALMAS_SMPS9_VOLTAGE 0x1B 665#define PALMAS_SMPS10_CTRL 0x1C 666#define PALMAS_SMPS10_STATUS 0x1F 667#define PALMAS_SMPS_CTRL 0x24 668#define PALMAS_SMPS_PD_CTRL 0x25 669#define PALMAS_SMPS_DITHER_EN 0x26 670#define PALMAS_SMPS_THERMAL_EN 0x27 671#define PALMAS_SMPS_THERMAL_STATUS 0x28 672#define PALMAS_SMPS_SHORT_STATUS 0x29 673#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A 674#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B 675#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C 676 677/* Bit definitions for SMPS12_CTRL */ 678#define PALMAS_SMPS12_CTRL_WR_S 0x80 679#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7 680#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40 681#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6 682#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30 683#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4 684#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c 685#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2 686#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03 687#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0 688 689/* Bit definitions for SMPS12_TSTEP */ 690#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03 691#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0 692 693/* Bit definitions for SMPS12_FORCE */ 694#define PALMAS_SMPS12_FORCE_CMD 0x80 695#define PALMAS_SMPS12_FORCE_CMD_SHIFT 7 696#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f 697#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0 698 699/* Bit definitions for SMPS12_VOLTAGE */ 700#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80 701#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7 702#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f 703#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0 704 705/* Bit definitions for SMPS3_CTRL */ 706#define PALMAS_SMPS3_CTRL_WR_S 0x80 707#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7 708#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30 709#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4 710#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c 711#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2 712#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 713#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0 714 715/* Bit definitions for SMPS3_VOLTAGE */ 716#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80 717#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7 718#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f 719#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0 720 721/* Bit definitions for SMPS45_CTRL */ 722#define PALMAS_SMPS45_CTRL_WR_S 0x80 723#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7 724#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40 725#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6 726#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30 727#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4 728#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c 729#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2 730#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03 731#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0 732 733/* Bit definitions for SMPS45_TSTEP */ 734#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03 735#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0 736 737/* Bit definitions for SMPS45_FORCE */ 738#define PALMAS_SMPS45_FORCE_CMD 0x80 739#define PALMAS_SMPS45_FORCE_CMD_SHIFT 7 740#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f 741#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0 742 743/* Bit definitions for SMPS45_VOLTAGE */ 744#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80 745#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7 746#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f 747#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0 748 749/* Bit definitions for SMPS6_CTRL */ 750#define PALMAS_SMPS6_CTRL_WR_S 0x80 751#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7 752#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40 753#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6 754#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30 755#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4 756#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c 757#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2 758#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03 759#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0 760 761/* Bit definitions for SMPS6_TSTEP */ 762#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03 763#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0 764 765/* Bit definitions for SMPS6_FORCE */ 766#define PALMAS_SMPS6_FORCE_CMD 0x80 767#define PALMAS_SMPS6_FORCE_CMD_SHIFT 7 768#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f 769#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0 770 771/* Bit definitions for SMPS6_VOLTAGE */ 772#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80 773#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7 774#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f 775#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0 776 777/* Bit definitions for SMPS7_CTRL */ 778#define PALMAS_SMPS7_CTRL_WR_S 0x80 779#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7 780#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30 781#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4 782#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c 783#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2 784#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03 785#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0 786 787/* Bit definitions for SMPS7_VOLTAGE */ 788#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80 789#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7 790#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f 791#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0 792 793/* Bit definitions for SMPS8_CTRL */ 794#define PALMAS_SMPS8_CTRL_WR_S 0x80 795#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7 796#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40 797#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6 798#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30 799#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4 800#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c 801#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2 802#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03 803#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0 804 805/* Bit definitions for SMPS8_TSTEP */ 806#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03 807#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0 808 809/* Bit definitions for SMPS8_FORCE */ 810#define PALMAS_SMPS8_FORCE_CMD 0x80 811#define PALMAS_SMPS8_FORCE_CMD_SHIFT 7 812#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f 813#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0 814 815/* Bit definitions for SMPS8_VOLTAGE */ 816#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80 817#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7 818#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f 819#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0 820 821/* Bit definitions for SMPS9_CTRL */ 822#define PALMAS_SMPS9_CTRL_WR_S 0x80 823#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7 824#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30 825#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4 826#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c 827#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2 828#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03 829#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0 830 831/* Bit definitions for SMPS9_VOLTAGE */ 832#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80 833#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7 834#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f 835#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0 836 837/* Bit definitions for SMPS10_CTRL */ 838#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0 839#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4 840#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f 841#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0 842 843/* Bit definitions for SMPS10_STATUS */ 844#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f 845#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0 846 847/* Bit definitions for SMPS_CTRL */ 848#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20 849#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5 850#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10 851#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4 852#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c 853#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2 854#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03 855#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0 856 857/* Bit definitions for SMPS_PD_CTRL */ 858#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40 859#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6 860#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20 861#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5 862#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10 863#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4 864#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08 865#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3 866#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04 867#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2 868#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02 869#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1 870#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01 871#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0 872 873/* Bit definitions for SMPS_THERMAL_EN */ 874#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40 875#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6 876#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20 877#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5 878#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08 879#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3 880#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04 881#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2 882#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01 883#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0 884 885/* Bit definitions for SMPS_THERMAL_STATUS */ 886#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40 887#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6 888#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20 889#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5 890#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08 891#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3 892#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04 893#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2 894#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01 895#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0 896 897/* Bit definitions for SMPS_SHORT_STATUS */ 898#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80 899#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7 900#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40 901#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6 902#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20 903#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5 904#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10 905#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4 906#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08 907#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3 908#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04 909#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2 910#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02 911#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1 912#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01 913#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0 914 915/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ 916#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40 917#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6 918#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20 919#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5 920#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10 921#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4 922#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08 923#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3 924#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04 925#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2 926#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02 927#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1 928#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01 929#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0 930 931/* Bit definitions for SMPS_POWERGOOD_MASK1 */ 932#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80 933#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7 934#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40 935#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6 936#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20 937#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5 938#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10 939#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4 940#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08 941#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3 942#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04 943#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2 944#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02 945#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1 946#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01 947#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0 948 949/* Bit definitions for SMPS_POWERGOOD_MASK2 */ 950#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 951#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7 952#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04 953#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2 954#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02 955#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1 956#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01 957#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0 958 959/* Registers for function LDO */ 960#define PALMAS_LDO1_CTRL 0x0 961#define PALMAS_LDO1_VOLTAGE 0x1 962#define PALMAS_LDO2_CTRL 0x2 963#define PALMAS_LDO2_VOLTAGE 0x3 964#define PALMAS_LDO3_CTRL 0x4 965#define PALMAS_LDO3_VOLTAGE 0x5 966#define PALMAS_LDO4_CTRL 0x6 967#define PALMAS_LDO4_VOLTAGE 0x7 968#define PALMAS_LDO5_CTRL 0x8 969#define PALMAS_LDO5_VOLTAGE 0x9 970#define PALMAS_LDO6_CTRL 0xA 971#define PALMAS_LDO6_VOLTAGE 0xB 972#define PALMAS_LDO7_CTRL 0xC 973#define PALMAS_LDO7_VOLTAGE 0xD 974#define PALMAS_LDO8_CTRL 0xE 975#define PALMAS_LDO8_VOLTAGE 0xF 976#define PALMAS_LDO9_CTRL 0x10 977#define PALMAS_LDO9_VOLTAGE 0x11 978#define PALMAS_LDOLN_CTRL 0x12 979#define PALMAS_LDOLN_VOLTAGE 0x13 980#define PALMAS_LDOUSB_CTRL 0x14 981#define PALMAS_LDOUSB_VOLTAGE 0x15 982#define PALMAS_LDO_CTRL 0x1A 983#define PALMAS_LDO_PD_CTRL1 0x1B 984#define PALMAS_LDO_PD_CTRL2 0x1C 985#define PALMAS_LDO_SHORT_STATUS1 0x1D 986#define PALMAS_LDO_SHORT_STATUS2 0x1E 987 988/* Bit definitions for LDO1_CTRL */ 989#define PALMAS_LDO1_CTRL_WR_S 0x80 990#define PALMAS_LDO1_CTRL_WR_S_SHIFT 7 991#define PALMAS_LDO1_CTRL_STATUS 0x10 992#define PALMAS_LDO1_CTRL_STATUS_SHIFT 4 993#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04 994#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2 995#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01 996#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0 997 998/* Bit definitions for LDO1_VOLTAGE */ 999#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f 1000#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0 1001 1002/* Bit definitions for LDO2_CTRL */ 1003#define PALMAS_LDO2_CTRL_WR_S 0x80 1004#define PALMAS_LDO2_CTRL_WR_S_SHIFT 7 1005#define PALMAS_LDO2_CTRL_STATUS 0x10 1006#define PALMAS_LDO2_CTRL_STATUS_SHIFT 4 1007#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04 1008#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2 1009#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01 1010#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0 1011 1012/* Bit definitions for LDO2_VOLTAGE */ 1013#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f 1014#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0 1015 1016/* Bit definitions for LDO3_CTRL */ 1017#define PALMAS_LDO3_CTRL_WR_S 0x80 1018#define PALMAS_LDO3_CTRL_WR_S_SHIFT 7 1019#define PALMAS_LDO3_CTRL_STATUS 0x10 1020#define PALMAS_LDO3_CTRL_STATUS_SHIFT 4 1021#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04 1022#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2 1023#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01 1024#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0 1025 1026/* Bit definitions for LDO3_VOLTAGE */ 1027#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f 1028#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0 1029 1030/* Bit definitions for LDO4_CTRL */ 1031#define PALMAS_LDO4_CTRL_WR_S 0x80 1032#define PALMAS_LDO4_CTRL_WR_S_SHIFT 7 1033#define PALMAS_LDO4_CTRL_STATUS 0x10 1034#define PALMAS_LDO4_CTRL_STATUS_SHIFT 4 1035#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04 1036#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2 1037#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01 1038#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0 1039 1040/* Bit definitions for LDO4_VOLTAGE */ 1041#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f 1042#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0 1043 1044/* Bit definitions for LDO5_CTRL */ 1045#define PALMAS_LDO5_CTRL_WR_S 0x80 1046#define PALMAS_LDO5_CTRL_WR_S_SHIFT 7 1047#define PALMAS_LDO5_CTRL_STATUS 0x10 1048#define PALMAS_LDO5_CTRL_STATUS_SHIFT 4 1049#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04 1050#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2 1051#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01 1052#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0 1053 1054/* Bit definitions for LDO5_VOLTAGE */ 1055#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f 1056#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0 1057 1058/* Bit definitions for LDO6_CTRL */ 1059#define PALMAS_LDO6_CTRL_WR_S 0x80 1060#define PALMAS_LDO6_CTRL_WR_S_SHIFT 7 1061#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40 1062#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6 1063#define PALMAS_LDO6_CTRL_STATUS 0x10 1064#define PALMAS_LDO6_CTRL_STATUS_SHIFT 4 1065#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04 1066#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2 1067#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01 1068#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0 1069 1070/* Bit definitions for LDO6_VOLTAGE */ 1071#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f 1072#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0 1073 1074/* Bit definitions for LDO7_CTRL */ 1075#define PALMAS_LDO7_CTRL_WR_S 0x80 1076#define PALMAS_LDO7_CTRL_WR_S_SHIFT 7 1077#define PALMAS_LDO7_CTRL_STATUS 0x10 1078#define PALMAS_LDO7_CTRL_STATUS_SHIFT 4 1079#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04 1080#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2 1081#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01 1082#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0 1083 1084/* Bit definitions for LDO7_VOLTAGE */ 1085#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f 1086#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0 1087 1088/* Bit definitions for LDO8_CTRL */ 1089#define PALMAS_LDO8_CTRL_WR_S 0x80 1090#define PALMAS_LDO8_CTRL_WR_S_SHIFT 7 1091#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40 1092#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6 1093#define PALMAS_LDO8_CTRL_STATUS 0x10 1094#define PALMAS_LDO8_CTRL_STATUS_SHIFT 4 1095#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04 1096#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2 1097#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01 1098#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0 1099 1100/* Bit definitions for LDO8_VOLTAGE */ 1101#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f 1102#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0 1103 1104/* Bit definitions for LDO9_CTRL */ 1105#define PALMAS_LDO9_CTRL_WR_S 0x80 1106#define PALMAS_LDO9_CTRL_WR_S_SHIFT 7 1107#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40 1108#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6 1109#define PALMAS_LDO9_CTRL_STATUS 0x10 1110#define PALMAS_LDO9_CTRL_STATUS_SHIFT 4 1111#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04 1112#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2 1113#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01 1114#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0 1115 1116/* Bit definitions for LDO9_VOLTAGE */ 1117#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f 1118#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0 1119 1120/* Bit definitions for LDOLN_CTRL */ 1121#define PALMAS_LDOLN_CTRL_WR_S 0x80 1122#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7 1123#define PALMAS_LDOLN_CTRL_STATUS 0x10 1124#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4 1125#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04 1126#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2 1127#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01 1128#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0 1129 1130/* Bit definitions for LDOLN_VOLTAGE */ 1131#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f 1132#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0 1133 1134/* Bit definitions for LDOUSB_CTRL */ 1135#define PALMAS_LDOUSB_CTRL_WR_S 0x80 1136#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7 1137#define PALMAS_LDOUSB_CTRL_STATUS 0x10 1138#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4 1139#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04 1140#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2 1141#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01 1142#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0 1143 1144/* Bit definitions for LDOUSB_VOLTAGE */ 1145#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f 1146#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0 1147 1148/* Bit definitions for LDO_CTRL */ 1149#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01 1150#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0 1151 1152/* Bit definitions for LDO_PD_CTRL1 */ 1153#define PALMAS_LDO_PD_CTRL1_LDO8 0x80 1154#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7 1155#define PALMAS_LDO_PD_CTRL1_LDO7 0x40 1156#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6 1157#define PALMAS_LDO_PD_CTRL1_LDO6 0x20 1158#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5 1159#define PALMAS_LDO_PD_CTRL1_LDO5 0x10 1160#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4 1161#define PALMAS_LDO_PD_CTRL1_LDO4 0x08 1162#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3 1163#define PALMAS_LDO_PD_CTRL1_LDO3 0x04 1164#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2 1165#define PALMAS_LDO_PD_CTRL1_LDO2 0x02 1166#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1 1167#define PALMAS_LDO_PD_CTRL1_LDO1 0x01 1168#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0 1169 1170/* Bit definitions for LDO_PD_CTRL2 */ 1171#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04 1172#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2 1173#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02 1174#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1 1175#define PALMAS_LDO_PD_CTRL2_LDO9 0x01 1176#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0 1177 1178/* Bit definitions for LDO_SHORT_STATUS1 */ 1179#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80 1180#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7 1181#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40 1182#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6 1183#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20 1184#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5 1185#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10 1186#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4 1187#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08 1188#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3 1189#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04 1190#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2 1191#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02 1192#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1 1193#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01 1194#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0 1195 1196/* Bit definitions for LDO_SHORT_STATUS2 */ 1197#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08 1198#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3 1199#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04 1200#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2 1201#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02 1202#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1 1203#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01 1204#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0 1205 1206/* Registers for function PMU_CONTROL */ 1207#define PALMAS_DEV_CTRL 0x0 1208#define PALMAS_POWER_CTRL 0x1 1209#define PALMAS_VSYS_LO 0x2 1210#define PALMAS_VSYS_MON 0x3 1211#define PALMAS_VBAT_MON 0x4 1212#define PALMAS_WATCHDOG 0x5 1213#define PALMAS_BOOT_STATUS 0x6 1214#define PALMAS_BATTERY_BOUNCE 0x7 1215#define PALMAS_BACKUP_BATTERY_CTRL 0x8 1216#define PALMAS_LONG_PRESS_KEY 0x9 1217#define PALMAS_OSC_THERM_CTRL 0xA 1218#define PALMAS_BATDEBOUNCING 0xB 1219#define PALMAS_SWOFF_HWRST 0xF 1220#define PALMAS_SWOFF_COLDRST 0x10 1221#define PALMAS_SWOFF_STATUS 0x11 1222#define PALMAS_PMU_CONFIG 0x12 1223#define PALMAS_SPARE 0x14 1224#define PALMAS_PMU_SECONDARY_INT 0x15 1225#define PALMAS_SW_REVISION 0x17 1226#define PALMAS_EXT_CHRG_CTRL 0x18 1227#define PALMAS_PMU_SECONDARY_INT2 0x19 1228 1229/* Bit definitions for DEV_CTRL */ 1230#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c 1231#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2 1232#define PALMAS_DEV_CTRL_SW_RST 0x02 1233#define PALMAS_DEV_CTRL_SW_RST_SHIFT 1 1234#define PALMAS_DEV_CTRL_DEV_ON 0x01 1235#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0 1236 1237/* Bit definitions for POWER_CTRL */ 1238#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04 1239#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2 1240#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02 1241#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1 1242#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01 1243#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0 1244 1245/* Bit definitions for VSYS_LO */ 1246#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f 1247#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0 1248 1249/* Bit definitions for VSYS_MON */ 1250#define PALMAS_VSYS_MON_ENABLE 0x80 1251#define PALMAS_VSYS_MON_ENABLE_SHIFT 7 1252#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f 1253#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0 1254 1255/* Bit definitions for VBAT_MON */ 1256#define PALMAS_VBAT_MON_ENABLE 0x80 1257#define PALMAS_VBAT_MON_ENABLE_SHIFT 7 1258#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f 1259#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0 1260 1261/* Bit definitions for WATCHDOG */ 1262#define PALMAS_WATCHDOG_LOCK 0x20 1263#define PALMAS_WATCHDOG_LOCK_SHIFT 5 1264#define PALMAS_WATCHDOG_ENABLE 0x10 1265#define PALMAS_WATCHDOG_ENABLE_SHIFT 4 1266#define PALMAS_WATCHDOG_MODE 0x08 1267#define PALMAS_WATCHDOG_MODE_SHIFT 3 1268#define PALMAS_WATCHDOG_TIMER_MASK 0x07 1269#define PALMAS_WATCHDOG_TIMER_SHIFT 0 1270 1271/* Bit definitions for BOOT_STATUS */ 1272#define PALMAS_BOOT_STATUS_BOOT1 0x02 1273#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1 1274#define PALMAS_BOOT_STATUS_BOOT0 0x01 1275#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0 1276 1277/* Bit definitions for BATTERY_BOUNCE */ 1278#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f 1279#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0 1280 1281/* Bit definitions for BACKUP_BATTERY_CTRL */ 1282#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80 1283#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7 1284#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40 1285#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6 1286#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20 1287#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5 1288#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10 1289#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4 1290#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08 1291#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3 1292#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06 1293#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1 1294#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01 1295#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0 1296 1297/* Bit definitions for LONG_PRESS_KEY */ 1298#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80 1299#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7 1300#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10 1301#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4 1302#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c 1303#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2 1304#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03 1305#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0 1306 1307/* Bit definitions for OSC_THERM_CTRL */ 1308#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80 1309#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7 1310#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40 1311#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6 1312#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20 1313#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5 1314#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10 1315#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4 1316#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c 1317#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2 1318#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02 1319#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1 1320#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01 1321#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0 1322 1323/* Bit definitions for BATDEBOUNCING */ 1324#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80 1325#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7 1326#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78 1327#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3 1328#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07 1329#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0 1330 1331/* Bit definitions for SWOFF_HWRST */ 1332#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80 1333#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7 1334#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40 1335#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6 1336#define PALMAS_SWOFF_HWRST_WTD 0x20 1337#define PALMAS_SWOFF_HWRST_WTD_SHIFT 5 1338#define PALMAS_SWOFF_HWRST_TSHUT 0x10 1339#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4 1340#define PALMAS_SWOFF_HWRST_RESET_IN 0x08 1341#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3 1342#define PALMAS_SWOFF_HWRST_SW_RST 0x04 1343#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2 1344#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02 1345#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1 1346#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01 1347#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0 1348 1349/* Bit definitions for SWOFF_COLDRST */ 1350#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80 1351#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7 1352#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40 1353#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6 1354#define PALMAS_SWOFF_COLDRST_WTD 0x20 1355#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5 1356#define PALMAS_SWOFF_COLDRST_TSHUT 0x10 1357#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4 1358#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08 1359#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3 1360#define PALMAS_SWOFF_COLDRST_SW_RST 0x04 1361#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2 1362#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02 1363#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1 1364#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01 1365#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0 1366 1367/* Bit definitions for SWOFF_STATUS */ 1368#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80 1369#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7 1370#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40 1371#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6 1372#define PALMAS_SWOFF_STATUS_WTD 0x20 1373#define PALMAS_SWOFF_STATUS_WTD_SHIFT 5 1374#define PALMAS_SWOFF_STATUS_TSHUT 0x10 1375#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4 1376#define PALMAS_SWOFF_STATUS_RESET_IN 0x08 1377#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3 1378#define PALMAS_SWOFF_STATUS_SW_RST 0x04 1379#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2 1380#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02 1381#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1 1382#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01 1383#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0 1384 1385/* Bit definitions for PMU_CONFIG */ 1386#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40 1387#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6 1388#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30 1389#define PALMAS_PMU_CONFIG_SPARE_SHIFT 4 1390#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c 1391#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2 1392#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02 1393#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1 1394#define PALMAS_PMU_CONFIG_AUTODEVON 0x01 1395#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0 1396 1397/* Bit definitions for SPARE */ 1398#define PALMAS_SPARE_SPARE_MASK 0xf8 1399#define PALMAS_SPARE_SPARE_SHIFT 3 1400#define PALMAS_SPARE_REGEN3_OD 0x04 1401#define PALMAS_SPARE_REGEN3_OD_SHIFT 2 1402#define PALMAS_SPARE_REGEN2_OD 0x02 1403#define PALMAS_SPARE_REGEN2_OD_SHIFT 1 1404#define PALMAS_SPARE_REGEN1_OD 0x01 1405#define PALMAS_SPARE_REGEN1_OD_SHIFT 0 1406 1407/* Bit definitions for PMU_SECONDARY_INT */ 1408#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80 1409#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7 1410#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40 1411#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6 1412#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20 1413#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5 1414#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10 1415#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4 1416#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08 1417#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3 1418#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04 1419#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2 1420#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02 1421#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1 1422#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01 1423#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0 1424 1425/* Bit definitions for SW_REVISION */ 1426#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff 1427#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0 1428 1429/* Bit definitions for EXT_CHRG_CTRL */ 1430#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80 1431#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7 1432#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40 1433#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6 1434#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08 1435#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3 1436#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04 1437#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2 1438#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02 1439#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1 1440#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01 1441#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0 1442 1443/* Bit definitions for PMU_SECONDARY_INT2 */ 1444#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20 1445#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5 1446#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10 1447#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4 1448#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02 1449#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1 1450#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01 1451#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0 1452 1453/* Registers for function RESOURCE */ 1454#define PALMAS_CLK32KG_CTRL 0x0 1455#define PALMAS_CLK32KGAUDIO_CTRL 0x1 1456#define PALMAS_REGEN1_CTRL 0x2 1457#define PALMAS_REGEN2_CTRL 0x3 1458#define PALMAS_SYSEN1_CTRL 0x4 1459#define PALMAS_SYSEN2_CTRL 0x5 1460#define PALMAS_NSLEEP_RES_ASSIGN 0x6 1461#define PALMAS_NSLEEP_SMPS_ASSIGN 0x7 1462#define PALMAS_NSLEEP_LDO_ASSIGN1 0x8 1463#define PALMAS_NSLEEP_LDO_ASSIGN2 0x9 1464#define PALMAS_ENABLE1_RES_ASSIGN 0xA 1465#define PALMAS_ENABLE1_SMPS_ASSIGN 0xB 1466#define PALMAS_ENABLE1_LDO_ASSIGN1 0xC 1467#define PALMAS_ENABLE1_LDO_ASSIGN2 0xD 1468#define PALMAS_ENABLE2_RES_ASSIGN 0xE 1469#define PALMAS_ENABLE2_SMPS_ASSIGN 0xF 1470#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10 1471#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11 1472#define PALMAS_REGEN3_CTRL 0x12 1473 1474/* Bit definitions for CLK32KG_CTRL */ 1475#define PALMAS_CLK32KG_CTRL_STATUS 0x10 1476#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4 1477#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04 1478#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2 1479#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01 1480#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0 1481 1482/* Bit definitions for CLK32KGAUDIO_CTRL */ 1483#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10 1484#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4 1485#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08 1486#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3 1487#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04 1488#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2 1489#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01 1490#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0 1491 1492/* Bit definitions for REGEN1_CTRL */ 1493#define PALMAS_REGEN1_CTRL_STATUS 0x10 1494#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4 1495#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04 1496#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2 1497#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01 1498#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0 1499 1500/* Bit definitions for REGEN2_CTRL */ 1501#define PALMAS_REGEN2_CTRL_STATUS 0x10 1502#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4 1503#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04 1504#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2 1505#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01 1506#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0 1507 1508/* Bit definitions for SYSEN1_CTRL */ 1509#define PALMAS_SYSEN1_CTRL_STATUS 0x10 1510#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4 1511#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04 1512#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2 1513#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01 1514#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0 1515 1516/* Bit definitions for SYSEN2_CTRL */ 1517#define PALMAS_SYSEN2_CTRL_STATUS 0x10 1518#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4 1519#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04 1520#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2 1521#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01 1522#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0 1523 1524/* Bit definitions for NSLEEP_RES_ASSIGN */ 1525#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40 1526#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6 1527#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20 1528#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1529#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10 1530#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4 1531#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08 1532#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3 1533#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04 1534#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2 1535#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02 1536#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1 1537#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01 1538#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0 1539 1540/* Bit definitions for NSLEEP_SMPS_ASSIGN */ 1541#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80 1542#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7 1543#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40 1544#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6 1545#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20 1546#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5 1547#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10 1548#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4 1549#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08 1550#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3 1551#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04 1552#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2 1553#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02 1554#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1 1555#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01 1556#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0 1557 1558/* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 1559#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80 1560#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7 1561#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40 1562#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6 1563#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20 1564#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5 1565#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10 1566#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4 1567#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08 1568#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3 1569#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04 1570#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2 1571#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02 1572#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1 1573#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01 1574#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0 1575 1576/* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 1577#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04 1578#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2 1579#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02 1580#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1 1581#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01 1582#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0 1583 1584/* Bit definitions for ENABLE1_RES_ASSIGN */ 1585#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40 1586#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6 1587#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20 1588#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1589#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10 1590#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4 1591#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08 1592#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3 1593#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04 1594#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2 1595#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02 1596#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1 1597#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01 1598#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0 1599 1600/* Bit definitions for ENABLE1_SMPS_ASSIGN */ 1601#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80 1602#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7 1603#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40 1604#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6 1605#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20 1606#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5 1607#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10 1608#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4 1609#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08 1610#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3 1611#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04 1612#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2 1613#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02 1614#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1 1615#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01 1616#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0 1617 1618/* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 1619#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80 1620#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7 1621#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40 1622#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6 1623#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20 1624#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5 1625#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10 1626#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4 1627#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08 1628#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3 1629#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04 1630#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2 1631#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02 1632#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1 1633#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01 1634#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0 1635 1636/* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 1637#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04 1638#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2 1639#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02 1640#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1 1641#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01 1642#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0 1643 1644/* Bit definitions for ENABLE2_RES_ASSIGN */ 1645#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40 1646#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6 1647#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20 1648#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1649#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10 1650#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4 1651#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08 1652#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3 1653#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04 1654#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2 1655#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02 1656#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1 1657#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01 1658#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0 1659 1660/* Bit definitions for ENABLE2_SMPS_ASSIGN */ 1661#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80 1662#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7 1663#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40 1664#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6 1665#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20 1666#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5 1667#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10 1668#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4 1669#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08 1670#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3 1671#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04 1672#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2 1673#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02 1674#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1 1675#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01 1676#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0 1677 1678/* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 1679#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80 1680#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7 1681#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40 1682#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6 1683#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20 1684#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5 1685#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10 1686#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4 1687#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08 1688#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3 1689#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04 1690#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2 1691#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02 1692#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1 1693#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01 1694#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0 1695 1696/* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 1697#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04 1698#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2 1699#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02 1700#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1 1701#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01 1702#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0 1703 1704/* Bit definitions for REGEN3_CTRL */ 1705#define PALMAS_REGEN3_CTRL_STATUS 0x10 1706#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4 1707#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04 1708#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2 1709#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01 1710#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0 1711 1712/* Registers for function PAD_CONTROL */ 1713#define PALMAS_PU_PD_INPUT_CTRL1 0x0 1714#define PALMAS_PU_PD_INPUT_CTRL2 0x1 1715#define PALMAS_PU_PD_INPUT_CTRL3 0x2 1716#define PALMAS_OD_OUTPUT_CTRL 0x4 1717#define PALMAS_POLARITY_CTRL 0x5 1718#define PALMAS_PRIMARY_SECONDARY_PAD1 0x6 1719#define PALMAS_PRIMARY_SECONDARY_PAD2 0x7 1720#define PALMAS_I2C_SPI 0x8 1721#define PALMAS_PU_PD_INPUT_CTRL4 0x9 1722#define PALMAS_PRIMARY_SECONDARY_PAD3 0xA 1723 1724/* Bit definitions for PU_PD_INPUT_CTRL1 */ 1725#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 1726#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6 1727#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20 1728#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5 1729#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10 1730#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4 1731#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04 1732#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2 1733#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02 1734#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1 1735 1736/* Bit definitions for PU_PD_INPUT_CTRL2 */ 1737#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20 1738#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5 1739#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10 1740#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4 1741#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08 1742#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3 1743#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04 1744#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2 1745#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02 1746#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1 1747#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01 1748#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0 1749 1750/* Bit definitions for PU_PD_INPUT_CTRL3 */ 1751#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40 1752#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6 1753#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10 1754#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4 1755#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04 1756#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2 1757#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01 1758#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0 1759 1760/* Bit definitions for OD_OUTPUT_CTRL */ 1761#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80 1762#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7 1763#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40 1764#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6 1765#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20 1766#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5 1767#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08 1768#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3 1769 1770/* Bit definitions for POLARITY_CTRL */ 1771#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80 1772#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7 1773#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40 1774#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6 1775#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20 1776#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5 1777#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10 1778#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4 1779#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08 1780#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3 1781#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04 1782#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2 1783#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02 1784#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1 1785#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01 1786#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0 1787 1788/* Bit definitions for PRIMARY_SECONDARY_PAD1 */ 1789#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80 1790#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7 1791#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60 1792#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5 1793#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18 1794#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3 1795#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04 1796#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2 1797#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02 1798#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1 1799#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01 1800#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0 1801 1802/* Bit definitions for PRIMARY_SECONDARY_PAD2 */ 1803#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30 1804#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4 1805#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08 1806#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3 1807#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06 1808#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1 1809#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01 1810#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0 1811 1812/* Bit definitions for I2C_SPI */ 1813#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80 1814#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7 1815#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40 1816#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6 1817#define PALMAS_I2C_SPI_ID_I2C2 0x20 1818#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5 1819#define PALMAS_I2C_SPI_I2C_SPI 0x10 1820#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4 1821#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f 1822#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0 1823 1824/* Bit definitions for PU_PD_INPUT_CTRL4 */ 1825#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40 1826#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6 1827#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10 1828#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4 1829#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04 1830#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2 1831#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01 1832#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0 1833 1834/* Bit definitions for PRIMARY_SECONDARY_PAD3 */ 1835#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02 1836#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1 1837#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01 1838#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0 1839 1840/* Registers for function LED_PWM */ 1841#define PALMAS_LED_PERIOD_CTRL 0x0 1842#define PALMAS_LED_CTRL 0x1 1843#define PALMAS_PWM_CTRL1 0x2 1844#define PALMAS_PWM_CTRL2 0x3 1845 1846/* Bit definitions for LED_PERIOD_CTRL */ 1847#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38 1848#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3 1849#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07 1850#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0 1851 1852/* Bit definitions for LED_CTRL */ 1853#define PALMAS_LED_CTRL_LED_2_SEQ 0x20 1854#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5 1855#define PALMAS_LED_CTRL_LED_1_SEQ 0x10 1856#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4 1857#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c 1858#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2 1859#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03 1860#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0 1861 1862/* Bit definitions for PWM_CTRL1 */ 1863#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02 1864#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1 1865#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01 1866#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0 1867 1868/* Bit definitions for PWM_CTRL2 */ 1869#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff 1870#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0 1871 1872/* Registers for function INTERRUPT */ 1873#define PALMAS_INT1_STATUS 0x0 1874#define PALMAS_INT1_MASK 0x1 1875#define PALMAS_INT1_LINE_STATE 0x2 1876#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3 1877#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4 1878#define PALMAS_INT2_STATUS 0x5 1879#define PALMAS_INT2_MASK 0x6 1880#define PALMAS_INT2_LINE_STATE 0x7 1881#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8 1882#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9 1883#define PALMAS_INT3_STATUS 0xA 1884#define PALMAS_INT3_MASK 0xB 1885#define PALMAS_INT3_LINE_STATE 0xC 1886#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD 1887#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE 1888#define PALMAS_INT4_STATUS 0xF 1889#define PALMAS_INT4_MASK 0x10 1890#define PALMAS_INT4_LINE_STATE 0x11 1891#define PALMAS_INT4_EDGE_DETECT1 0x12 1892#define PALMAS_INT4_EDGE_DETECT2 0x13 1893#define PALMAS_INT_CTRL 0x14 1894 1895/* Bit definitions for INT1_STATUS */ 1896#define PALMAS_INT1_STATUS_VBAT_MON 0x80 1897#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7 1898#define PALMAS_INT1_STATUS_VSYS_MON 0x40 1899#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6 1900#define PALMAS_INT1_STATUS_HOTDIE 0x20 1901#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5 1902#define PALMAS_INT1_STATUS_PWRDOWN 0x10 1903#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4 1904#define PALMAS_INT1_STATUS_RPWRON 0x08 1905#define PALMAS_INT1_STATUS_RPWRON_SHIFT 3 1906#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04 1907#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2 1908#define PALMAS_INT1_STATUS_PWRON 0x02 1909#define PALMAS_INT1_STATUS_PWRON_SHIFT 1 1910#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01 1911#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0 1912 1913/* Bit definitions for INT1_MASK */ 1914#define PALMAS_INT1_MASK_VBAT_MON 0x80 1915#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7 1916#define PALMAS_INT1_MASK_VSYS_MON 0x40 1917#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6 1918#define PALMAS_INT1_MASK_HOTDIE 0x20 1919#define PALMAS_INT1_MASK_HOTDIE_SHIFT 5 1920#define PALMAS_INT1_MASK_PWRDOWN 0x10 1921#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4 1922#define PALMAS_INT1_MASK_RPWRON 0x08 1923#define PALMAS_INT1_MASK_RPWRON_SHIFT 3 1924#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04 1925#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2 1926#define PALMAS_INT1_MASK_PWRON 0x02 1927#define PALMAS_INT1_MASK_PWRON_SHIFT 1 1928#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01 1929#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0 1930 1931/* Bit definitions for INT1_LINE_STATE */ 1932#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80 1933#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7 1934#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40 1935#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6 1936#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20 1937#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5 1938#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10 1939#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4 1940#define PALMAS_INT1_LINE_STATE_RPWRON 0x08 1941#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3 1942#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 1943#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2 1944#define PALMAS_INT1_LINE_STATE_PWRON 0x02 1945#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1 1946#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01 1947#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0 1948 1949/* Bit definitions for INT2_STATUS */ 1950#define PALMAS_INT2_STATUS_VAC_ACOK 0x80 1951#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7 1952#define PALMAS_INT2_STATUS_SHORT 0x40 1953#define PALMAS_INT2_STATUS_SHORT_SHIFT 6 1954#define PALMAS_INT2_STATUS_FBI_BB 0x20 1955#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5 1956#define PALMAS_INT2_STATUS_RESET_IN 0x10 1957#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4 1958#define PALMAS_INT2_STATUS_BATREMOVAL 0x08 1959#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3 1960#define PALMAS_INT2_STATUS_WDT 0x04 1961#define PALMAS_INT2_STATUS_WDT_SHIFT 2 1962#define PALMAS_INT2_STATUS_RTC_TIMER 0x02 1963#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1 1964#define PALMAS_INT2_STATUS_RTC_ALARM 0x01 1965#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0 1966 1967/* Bit definitions for INT2_MASK */ 1968#define PALMAS_INT2_MASK_VAC_ACOK 0x80 1969#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7 1970#define PALMAS_INT2_MASK_SHORT 0x40 1971#define PALMAS_INT2_MASK_SHORT_SHIFT 6 1972#define PALMAS_INT2_MASK_FBI_BB 0x20 1973#define PALMAS_INT2_MASK_FBI_BB_SHIFT 5 1974#define PALMAS_INT2_MASK_RESET_IN 0x10 1975#define PALMAS_INT2_MASK_RESET_IN_SHIFT 4 1976#define PALMAS_INT2_MASK_BATREMOVAL 0x08 1977#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3 1978#define PALMAS_INT2_MASK_WDT 0x04 1979#define PALMAS_INT2_MASK_WDT_SHIFT 2 1980#define PALMAS_INT2_MASK_RTC_TIMER 0x02 1981#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1 1982#define PALMAS_INT2_MASK_RTC_ALARM 0x01 1983#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0 1984 1985/* Bit definitions for INT2_LINE_STATE */ 1986#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80 1987#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7 1988#define PALMAS_INT2_LINE_STATE_SHORT 0x40 1989#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6 1990#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20 1991#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5 1992#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10 1993#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4 1994#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08 1995#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3 1996#define PALMAS_INT2_LINE_STATE_WDT 0x04 1997#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2 1998#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02 1999#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1 2000#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01 2001#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0 2002 2003/* Bit definitions for INT3_STATUS */ 2004#define PALMAS_INT3_STATUS_VBUS 0x80 2005#define PALMAS_INT3_STATUS_VBUS_SHIFT 7 2006#define PALMAS_INT3_STATUS_VBUS_OTG 0x40 2007#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6 2008#define PALMAS_INT3_STATUS_ID 0x20 2009#define PALMAS_INT3_STATUS_ID_SHIFT 5 2010#define PALMAS_INT3_STATUS_ID_OTG 0x10 2011#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4 2012#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08 2013#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3 2014#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04 2015#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2 2016#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02 2017#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1 2018#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01 2019#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0 2020 2021/* Bit definitions for INT3_MASK */ 2022#define PALMAS_INT3_MASK_VBUS 0x80 2023#define PALMAS_INT3_MASK_VBUS_SHIFT 7 2024#define PALMAS_INT3_MASK_VBUS_OTG 0x40 2025#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6 2026#define PALMAS_INT3_MASK_ID 0x20 2027#define PALMAS_INT3_MASK_ID_SHIFT 5 2028#define PALMAS_INT3_MASK_ID_OTG 0x10 2029#define PALMAS_INT3_MASK_ID_OTG_SHIFT 4 2030#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08 2031#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3 2032#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04 2033#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2 2034#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02 2035#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1 2036#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01 2037#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0 2038 2039/* Bit definitions for INT3_LINE_STATE */ 2040#define PALMAS_INT3_LINE_STATE_VBUS 0x80 2041#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7 2042#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40 2043#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6 2044#define PALMAS_INT3_LINE_STATE_ID 0x20 2045#define PALMAS_INT3_LINE_STATE_ID_SHIFT 5 2046#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10 2047#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4 2048#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08 2049#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3 2050#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04 2051#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2 2052#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02 2053#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1 2054#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01 2055#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0 2056 2057/* Bit definitions for INT4_STATUS */ 2058#define PALMAS_INT4_STATUS_GPIO_7 0x80 2059#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7 2060#define PALMAS_INT4_STATUS_GPIO_6 0x40 2061#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6 2062#define PALMAS_INT4_STATUS_GPIO_5 0x20 2063#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5 2064#define PALMAS_INT4_STATUS_GPIO_4 0x10 2065#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4 2066#define PALMAS_INT4_STATUS_GPIO_3 0x08 2067#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3 2068#define PALMAS_INT4_STATUS_GPIO_2 0x04 2069#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2 2070#define PALMAS_INT4_STATUS_GPIO_1 0x02 2071#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1 2072#define PALMAS_INT4_STATUS_GPIO_0 0x01 2073#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0 2074 2075/* Bit definitions for INT4_MASK */ 2076#define PALMAS_INT4_MASK_GPIO_7 0x80 2077#define PALMAS_INT4_MASK_GPIO_7_SHIFT 7 2078#define PALMAS_INT4_MASK_GPIO_6 0x40 2079#define PALMAS_INT4_MASK_GPIO_6_SHIFT 6 2080#define PALMAS_INT4_MASK_GPIO_5 0x20 2081#define PALMAS_INT4_MASK_GPIO_5_SHIFT 5 2082#define PALMAS_INT4_MASK_GPIO_4 0x10 2083#define PALMAS_INT4_MASK_GPIO_4_SHIFT 4 2084#define PALMAS_INT4_MASK_GPIO_3 0x08 2085#define PALMAS_INT4_MASK_GPIO_3_SHIFT 3 2086#define PALMAS_INT4_MASK_GPIO_2 0x04 2087#define PALMAS_INT4_MASK_GPIO_2_SHIFT 2 2088#define PALMAS_INT4_MASK_GPIO_1 0x02 2089#define PALMAS_INT4_MASK_GPIO_1_SHIFT 1 2090#define PALMAS_INT4_MASK_GPIO_0 0x01 2091#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0 2092 2093/* Bit definitions for INT4_LINE_STATE */ 2094#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80 2095#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7 2096#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40 2097#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6 2098#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20 2099#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5 2100#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10 2101#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4 2102#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08 2103#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3 2104#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04 2105#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2 2106#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02 2107#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1 2108#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01 2109#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0 2110 2111/* Bit definitions for INT4_EDGE_DETECT1 */ 2112#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 2113#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7 2114#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 2115#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6 2116#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 2117#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5 2118#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 2119#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4 2120#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 2121#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3 2122#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 2123#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2 2124#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 2125#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1 2126#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 2127#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0 2128 2129/* Bit definitions for INT4_EDGE_DETECT2 */ 2130#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80 2131#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7 2132#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40 2133#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6 2134#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 2135#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5 2136#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 2137#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4 2138#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 2139#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3 2140#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 2141#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2 2142#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 2143#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1 2144#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 2145#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0 2146 2147/* Bit definitions for INT_CTRL */ 2148#define PALMAS_INT_CTRL_INT_PENDING 0x04 2149#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2 2150#define PALMAS_INT_CTRL_INT_CLEAR 0x01 2151#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0 2152 2153/* Registers for function USB_OTG */ 2154#define PALMAS_USB_WAKEUP 0x3 2155#define PALMAS_USB_VBUS_CTRL_SET 0x4 2156#define PALMAS_USB_VBUS_CTRL_CLR 0x5 2157#define PALMAS_USB_ID_CTRL_SET 0x6 2158#define PALMAS_USB_ID_CTRL_CLEAR 0x7 2159#define PALMAS_USB_VBUS_INT_SRC 0x8 2160#define PALMAS_USB_VBUS_INT_LATCH_SET 0x9 2161#define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA 2162#define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB 2163#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC 2164#define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD 2165#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE 2166#define PALMAS_USB_ID_INT_SRC 0xF 2167#define PALMAS_USB_ID_INT_LATCH_SET 0x10 2168#define PALMAS_USB_ID_INT_LATCH_CLR 0x11 2169#define PALMAS_USB_ID_INT_EN_LO_SET 0x12 2170#define PALMAS_USB_ID_INT_EN_LO_CLR 0x13 2171#define PALMAS_USB_ID_INT_EN_HI_SET 0x14 2172#define PALMAS_USB_ID_INT_EN_HI_CLR 0x15 2173#define PALMAS_USB_OTG_ADP_CTRL 0x16 2174#define PALMAS_USB_OTG_ADP_HIGH 0x17 2175#define PALMAS_USB_OTG_ADP_LOW 0x18 2176#define PALMAS_USB_OTG_ADP_RISE 0x19 2177#define PALMAS_USB_OTG_REVISION 0x1A 2178 2179/* Bit definitions for USB_WAKEUP */ 2180#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01 2181#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0 2182 2183/* Bit definitions for USB_VBUS_CTRL_SET */ 2184#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80 2185#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7 2186#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20 2187#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5 2188#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10 2189#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4 2190#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08 2191#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3 2192#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04 2193#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2 2194 2195/* Bit definitions for USB_VBUS_CTRL_CLR */ 2196#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80 2197#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7 2198#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20 2199#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5 2200#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10 2201#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4 2202#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08 2203#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3 2204#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04 2205#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2 2206 2207/* Bit definitions for USB_ID_CTRL_SET */ 2208#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80 2209#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7 2210#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40 2211#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6 2212#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20 2213#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5 2214#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10 2215#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4 2216#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08 2217#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3 2218#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04 2219#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2 2220 2221/* Bit definitions for USB_ID_CTRL_CLEAR */ 2222#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80 2223#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7 2224#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40 2225#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6 2226#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20 2227#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5 2228#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10 2229#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4 2230#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08 2231#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3 2232#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04 2233#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2 2234 2235/* Bit definitions for USB_VBUS_INT_SRC */ 2236#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80 2237#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7 2238#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40 2239#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6 2240#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20 2241#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5 2242#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08 2243#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3 2244#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04 2245#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2 2246#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02 2247#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1 2248#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01 2249#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0 2250 2251/* Bit definitions for USB_VBUS_INT_LATCH_SET */ 2252#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80 2253#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7 2254#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40 2255#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6 2256#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20 2257#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5 2258#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10 2259#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4 2260#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08 2261#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3 2262#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04 2263#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2 2264#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02 2265#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1 2266#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01 2267#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0 2268 2269/* Bit definitions for USB_VBUS_INT_LATCH_CLR */ 2270#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80 2271#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7 2272#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40 2273#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6 2274#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20 2275#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5 2276#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10 2277#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4 2278#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08 2279#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3 2280#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04 2281#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2 2282#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02 2283#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1 2284#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01 2285#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0 2286 2287/* Bit definitions for USB_VBUS_INT_EN_LO_SET */ 2288#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80 2289#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7 2290#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40 2291#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6 2292#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20 2293#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5 2294#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08 2295#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3 2296#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04 2297#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2 2298#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02 2299#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1 2300#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01 2301#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0 2302 2303/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */ 2304#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80 2305#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7 2306#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40 2307#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6 2308#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20 2309#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5 2310#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08 2311#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3 2312#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04 2313#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2 2314#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02 2315#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1 2316#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01 2317#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0 2318 2319/* Bit definitions for USB_VBUS_INT_EN_HI_SET */ 2320#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80 2321#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7 2322#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40 2323#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6 2324#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20 2325#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5 2326#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10 2327#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4 2328#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08 2329#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3 2330#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04 2331#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2 2332#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02 2333#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1 2334#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01 2335#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0 2336 2337/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */ 2338#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80 2339#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7 2340#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40 2341#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6 2342#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20 2343#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5 2344#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10 2345#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4 2346#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08 2347#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3 2348#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04 2349#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2 2350#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02 2351#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1 2352#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01 2353#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0 2354 2355/* Bit definitions for USB_ID_INT_SRC */ 2356#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10 2357#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4 2358#define PALMAS_USB_ID_INT_SRC_ID_A 0x08 2359#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3 2360#define PALMAS_USB_ID_INT_SRC_ID_B 0x04 2361#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2 2362#define PALMAS_USB_ID_INT_SRC_ID_C 0x02 2363#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1 2364#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01 2365#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0 2366 2367/* Bit definitions for USB_ID_INT_LATCH_SET */ 2368#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10 2369#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4 2370#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08 2371#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3 2372#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04 2373#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2 2374#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02 2375#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1 2376#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01 2377#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0 2378 2379/* Bit definitions for USB_ID_INT_LATCH_CLR */ 2380#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10 2381#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4 2382#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08 2383#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3 2384#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04 2385#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2 2386#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02 2387#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1 2388#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01 2389#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0 2390 2391/* Bit definitions for USB_ID_INT_EN_LO_SET */ 2392#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10 2393#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4 2394#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08 2395#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3 2396#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04 2397#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2 2398#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02 2399#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1 2400#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01 2401#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0 2402 2403/* Bit definitions for USB_ID_INT_EN_LO_CLR */ 2404#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10 2405#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4 2406#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08 2407#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3 2408#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04 2409#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2 2410#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02 2411#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1 2412#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01 2413#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0 2414 2415/* Bit definitions for USB_ID_INT_EN_HI_SET */ 2416#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10 2417#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4 2418#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08 2419#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3 2420#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04 2421#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2 2422#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02 2423#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1 2424#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01 2425#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0 2426 2427/* Bit definitions for USB_ID_INT_EN_HI_CLR */ 2428#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10 2429#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4 2430#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08 2431#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3 2432#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04 2433#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2 2434#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02 2435#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1 2436#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01 2437#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0 2438 2439/* Bit definitions for USB_OTG_ADP_CTRL */ 2440#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04 2441#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2 2442#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03 2443#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0 2444 2445/* Bit definitions for USB_OTG_ADP_HIGH */ 2446#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff 2447#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0 2448 2449/* Bit definitions for USB_OTG_ADP_LOW */ 2450#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff 2451#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0 2452 2453/* Bit definitions for USB_OTG_ADP_RISE */ 2454#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff 2455#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0 2456 2457/* Bit definitions for USB_OTG_REVISION */ 2458#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01 2459#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0 2460 2461/* Registers for function VIBRATOR */ 2462#define PALMAS_VIBRA_CTRL 0x0 2463 2464/* Bit definitions for VIBRA_CTRL */ 2465#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06 2466#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1 2467#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01 2468#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0 2469 2470/* Registers for function GPIO */ 2471#define PALMAS_GPIO_DATA_IN 0x0 2472#define PALMAS_GPIO_DATA_DIR 0x1 2473#define PALMAS_GPIO_DATA_OUT 0x2 2474#define PALMAS_GPIO_DEBOUNCE_EN 0x3 2475#define PALMAS_GPIO_CLEAR_DATA_OUT 0x4 2476#define PALMAS_GPIO_SET_DATA_OUT 0x5 2477#define PALMAS_PU_PD_GPIO_CTRL1 0x6 2478#define PALMAS_PU_PD_GPIO_CTRL2 0x7 2479#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8 2480 2481/* Bit definitions for GPIO_DATA_IN */ 2482#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 2483#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7 2484#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40 2485#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6 2486#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20 2487#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5 2488#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10 2489#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4 2490#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08 2491#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3 2492#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04 2493#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2 2494#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02 2495#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1 2496#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01 2497#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0 2498 2499/* Bit definitions for GPIO_DATA_DIR */ 2500#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80 2501#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7 2502#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40 2503#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6 2504#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20 2505#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5 2506#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10 2507#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4 2508#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08 2509#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3 2510#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04 2511#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2 2512#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02 2513#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1 2514#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01 2515#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0 2516 2517/* Bit definitions for GPIO_DATA_OUT */ 2518#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80 2519#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7 2520#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40 2521#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6 2522#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20 2523#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5 2524#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10 2525#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4 2526#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08 2527#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3 2528#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04 2529#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2 2530#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02 2531#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1 2532#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01 2533#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0 2534 2535/* Bit definitions for GPIO_DEBOUNCE_EN */ 2536#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80 2537#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7 2538#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40 2539#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6 2540#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20 2541#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5 2542#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10 2543#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4 2544#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08 2545#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3 2546#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04 2547#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2 2548#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02 2549#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1 2550#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01 2551#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0 2552 2553/* Bit definitions for GPIO_CLEAR_DATA_OUT */ 2554#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80 2555#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7 2556#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40 2557#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6 2558#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20 2559#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5 2560#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10 2561#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4 2562#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08 2563#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3 2564#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04 2565#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2 2566#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02 2567#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1 2568#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01 2569#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0 2570 2571/* Bit definitions for GPIO_SET_DATA_OUT */ 2572#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80 2573#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7 2574#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40 2575#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6 2576#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20 2577#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5 2578#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10 2579#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4 2580#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08 2581#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3 2582#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04 2583#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2 2584#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02 2585#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1 2586#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01 2587#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0 2588 2589/* Bit definitions for PU_PD_GPIO_CTRL1 */ 2590#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40 2591#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6 2592#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20 2593#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5 2594#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10 2595#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4 2596#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08 2597#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3 2598#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04 2599#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2 2600#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01 2601#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0 2602 2603/* Bit definitions for PU_PD_GPIO_CTRL2 */ 2604#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40 2605#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6 2606#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20 2607#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5 2608#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10 2609#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4 2610#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08 2611#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3 2612#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04 2613#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2 2614#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02 2615#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1 2616#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01 2617#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0 2618 2619/* Bit definitions for OD_OUTPUT_GPIO_CTRL */ 2620#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20 2621#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5 2622#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04 2623#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2 2624#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02 2625#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1 2626 2627/* Registers for function GPADC */ 2628#define PALMAS_GPADC_CTRL1 0x0 2629#define PALMAS_GPADC_CTRL2 0x1 2630#define PALMAS_GPADC_RT_CTRL 0x2 2631#define PALMAS_GPADC_AUTO_CTRL 0x3 2632#define PALMAS_GPADC_STATUS 0x4 2633#define PALMAS_GPADC_RT_SELECT 0x5 2634#define PALMAS_GPADC_RT_CONV0_LSB 0x6 2635#define PALMAS_GPADC_RT_CONV0_MSB 0x7 2636#define PALMAS_GPADC_AUTO_SELECT 0x8 2637#define PALMAS_GPADC_AUTO_CONV0_LSB 0x9 2638#define PALMAS_GPADC_AUTO_CONV0_MSB 0xA 2639#define PALMAS_GPADC_AUTO_CONV1_LSB 0xB 2640#define PALMAS_GPADC_AUTO_CONV1_MSB 0xC 2641#define PALMAS_GPADC_SW_SELECT 0xD 2642#define PALMAS_GPADC_SW_CONV0_LSB 0xE 2643#define PALMAS_GPADC_SW_CONV0_MSB 0xF 2644#define PALMAS_GPADC_THRES_CONV0_LSB 0x10 2645#define PALMAS_GPADC_THRES_CONV0_MSB 0x11 2646#define PALMAS_GPADC_THRES_CONV1_LSB 0x12 2647#define PALMAS_GPADC_THRES_CONV1_MSB 0x13 2648#define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14 2649#define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15 2650 2651/* Bit definitions for GPADC_CTRL1 */ 2652#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0 2653#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6 2654#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30 2655#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4 2656#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c 2657#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2 2658#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02 2659#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1 2660#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01 2661#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0 2662 2663/* Bit definitions for GPADC_CTRL2 */ 2664#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06 2665#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1 2666 2667/* Bit definitions for GPADC_RT_CTRL */ 2668#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02 2669#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1 2670#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01 2671#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0 2672 2673/* Bit definitions for GPADC_AUTO_CTRL */ 2674#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80 2675#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7 2676#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40 2677#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6 2678#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20 2679#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5 2680#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10 2681#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4 2682#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f 2683#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0 2684 2685/* Bit definitions for GPADC_STATUS */ 2686#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10 2687#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4 2688 2689/* Bit definitions for GPADC_RT_SELECT */ 2690#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80 2691#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7 2692#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f 2693#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0 2694 2695/* Bit definitions for GPADC_RT_CONV0_LSB */ 2696#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff 2697#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0 2698 2699/* Bit definitions for GPADC_RT_CONV0_MSB */ 2700#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f 2701#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0 2702 2703/* Bit definitions for GPADC_AUTO_SELECT */ 2704#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0 2705#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4 2706#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f 2707#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0 2708 2709/* Bit definitions for GPADC_AUTO_CONV0_LSB */ 2710#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff 2711#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0 2712 2713/* Bit definitions for GPADC_AUTO_CONV0_MSB */ 2714#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f 2715#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0 2716 2717/* Bit definitions for GPADC_AUTO_CONV1_LSB */ 2718#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff 2719#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0 2720 2721/* Bit definitions for GPADC_AUTO_CONV1_MSB */ 2722#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f 2723#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0 2724 2725/* Bit definitions for GPADC_SW_SELECT */ 2726#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80 2727#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7 2728#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10 2729#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4 2730#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f 2731#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0 2732 2733/* Bit definitions for GPADC_SW_CONV0_LSB */ 2734#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff 2735#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0 2736 2737/* Bit definitions for GPADC_SW_CONV0_MSB */ 2738#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f 2739#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0 2740 2741/* Bit definitions for GPADC_THRES_CONV0_LSB */ 2742#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff 2743#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0 2744 2745/* Bit definitions for GPADC_THRES_CONV0_MSB */ 2746#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80 2747#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7 2748#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f 2749#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0 2750 2751/* Bit definitions for GPADC_THRES_CONV1_LSB */ 2752#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff 2753#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0 2754 2755/* Bit definitions for GPADC_THRES_CONV1_MSB */ 2756#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80 2757#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7 2758#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f 2759#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0 2760 2761/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */ 2762#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20 2763#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5 2764#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10 2765#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4 2766#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f 2767#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0 2768 2769/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */ 2770#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80 2771#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7 2772#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f 2773#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0 2774 2775/* Registers for function GPADC */ 2776#define PALMAS_GPADC_TRIM1 0x0 2777#define PALMAS_GPADC_TRIM2 0x1 2778#define PALMAS_GPADC_TRIM3 0x2 2779#define PALMAS_GPADC_TRIM4 0x3 2780#define PALMAS_GPADC_TRIM5 0x4 2781#define PALMAS_GPADC_TRIM6 0x5 2782#define PALMAS_GPADC_TRIM7 0x6 2783#define PALMAS_GPADC_TRIM8 0x7 2784#define PALMAS_GPADC_TRIM9 0x8 2785#define PALMAS_GPADC_TRIM10 0x9 2786#define PALMAS_GPADC_TRIM11 0xA 2787#define PALMAS_GPADC_TRIM12 0xB 2788#define PALMAS_GPADC_TRIM13 0xC 2789#define PALMAS_GPADC_TRIM14 0xD 2790#define PALMAS_GPADC_TRIM15 0xE 2791#define PALMAS_GPADC_TRIM16 0xF 2792 2793static inline int palmas_read(struct palmas *palmas, unsigned int base, 2794 unsigned int reg, unsigned int *val) 2795{ 2796 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2797 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2798 2799 return regmap_read(palmas->regmap[slave_id], addr, val); 2800} 2801 2802static inline int palmas_write(struct palmas *palmas, unsigned int base, 2803 unsigned int reg, unsigned int value) 2804{ 2805 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2806 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2807 2808 return regmap_write(palmas->regmap[slave_id], addr, value); 2809} 2810 2811static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base, 2812 unsigned int reg, const void *val, size_t val_count) 2813{ 2814 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2815 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2816 2817 return regmap_bulk_write(palmas->regmap[slave_id], addr, 2818 val, val_count); 2819} 2820 2821static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base, 2822 unsigned int reg, void *val, size_t val_count) 2823{ 2824 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2825 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2826 2827 return regmap_bulk_read(palmas->regmap[slave_id], addr, 2828 val, val_count); 2829} 2830 2831static inline int palmas_update_bits(struct palmas *palmas, unsigned int base, 2832 unsigned int reg, unsigned int mask, unsigned int val) 2833{ 2834 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2835 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2836 2837 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val); 2838} 2839 2840static inline int palmas_irq_get_virq(struct palmas *palmas, int irq) 2841{ 2842 return regmap_irq_get_virq(palmas->irq_data, irq); 2843} 2844 2845#endif /* __LINUX_MFD_PALMAS_H */