tjh.dev / kernel
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kernel / drivers / net / ethernet / broadcom / tg3.h
at v3.9 3372 lines 125 kB view raw
1/* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $ 2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver. 3 * 4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) 5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com) 6 * Copyright (C) 2004 Sun Microsystems Inc. 7 * Copyright (C) 2007-2013 Broadcom Corporation. 8 */ 9 10#ifndef _T3_H 11#define _T3_H 12 13#define TG3_64BIT_REG_HIGH 0x00UL 14#define TG3_64BIT_REG_LOW 0x04UL 15 16/* Descriptor block info. */ 17#define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */ 18#define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */ 19#define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */ 20#define BDINFO_FLAGS_DISABLED 0x00000002 21#define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000 22#define BDINFO_FLAGS_MAXLEN_SHIFT 16 23#define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */ 24#define TG3_BDINFO_SIZE 0x10UL 25 26#define TG3_RX_STD_MAX_SIZE_5700 512 27#define TG3_RX_STD_MAX_SIZE_5717 2048 28#define TG3_RX_JMB_MAX_SIZE_5700 256 29#define TG3_RX_JMB_MAX_SIZE_5717 1024 30#define TG3_RX_RET_MAX_SIZE_5700 1024 31#define TG3_RX_RET_MAX_SIZE_5705 512 32#define TG3_RX_RET_MAX_SIZE_5717 4096 33 34#define TG3_RSS_INDIR_TBL_SIZE 128 35 36/* First 256 bytes are a mirror of PCI config space. */ 37#define TG3PCI_VENDOR 0x00000000 38#define TG3PCI_VENDOR_BROADCOM 0x14e4 39#define TG3PCI_DEVICE 0x00000002 40#define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */ 41#define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */ 42#define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */ 43#define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */ 44#define TG3PCI_DEVICE_TIGON3_5761S 0x1688 45#define TG3PCI_DEVICE_TIGON3_5761SE 0x1689 46#define TG3PCI_DEVICE_TIGON3_57780 0x1692 47#define TG3PCI_DEVICE_TIGON3_5787M 0x1693 48#define TG3PCI_DEVICE_TIGON3_57760 0x1690 49#define TG3PCI_DEVICE_TIGON3_57790 0x1694 50#define TG3PCI_DEVICE_TIGON3_57788 0x1691 51#define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */ 52#define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */ 53#define TG3PCI_DEVICE_TIGON3_5717 0x1655 54#define TG3PCI_DEVICE_TIGON3_5717_C 0x1665 55#define TG3PCI_DEVICE_TIGON3_5718 0x1656 56#define TG3PCI_DEVICE_TIGON3_57781 0x16b1 57#define TG3PCI_DEVICE_TIGON3_57785 0x16b5 58#define TG3PCI_DEVICE_TIGON3_57761 0x16b0 59#define TG3PCI_DEVICE_TIGON3_57765 0x16b4 60#define TG3PCI_DEVICE_TIGON3_57791 0x16b2 61#define TG3PCI_DEVICE_TIGON3_57795 0x16b6 62#define TG3PCI_DEVICE_TIGON3_5719 0x1657 63#define TG3PCI_DEVICE_TIGON3_5720 0x165f 64#define TG3PCI_DEVICE_TIGON3_57762 0x1682 65#define TG3PCI_DEVICE_TIGON3_57766 0x1686 66#define TG3PCI_DEVICE_TIGON3_57786 0x16b3 67#define TG3PCI_DEVICE_TIGON3_57782 0x16b7 68#define TG3PCI_DEVICE_TIGON3_5762 0x1687 69#define TG3PCI_DEVICE_TIGON3_5725 0x1643 70#define TG3PCI_DEVICE_TIGON3_5727 0x16f3 71/* 0x04 --> 0x2c unused */ 72#define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM 73#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644 74#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001 75#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002 76#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003 77#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005 78#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006 79#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007 80#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008 81#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008 82#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009 83#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009 84#define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM 85#define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000 86#define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006 87#define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004 88#define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007 89#define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008 90#define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL 91#define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1 92#define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106 93#define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109 94#define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a 95#define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ 96#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c 97#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a 98#define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d 99#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085 100#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099 101#define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM 102#define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281 103#define TG3PCI_SUBDEVICE_ID_ACER_57780_A 0x0601 104#define TG3PCI_SUBDEVICE_ID_ACER_57780_B 0x0612 105#define TG3PCI_SUBDEVICE_ID_LENOVO_5787M 0x3056 106 107/* 0x30 --> 0x64 unused */ 108#define TG3PCI_MSI_DATA 0x00000064 109/* 0x66 --> 0x68 unused */ 110#define TG3PCI_MISC_HOST_CTRL 0x00000068 111#define MISC_HOST_CTRL_CLEAR_INT 0x00000001 112#define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002 113#define MISC_HOST_CTRL_BYTE_SWAP 0x00000004 114#define MISC_HOST_CTRL_WORD_SWAP 0x00000008 115#define MISC_HOST_CTRL_PCISTATE_RW 0x00000010 116#define MISC_HOST_CTRL_CLKREG_RW 0x00000020 117#define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040 118#define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080 119#define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100 120#define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200 121#define MISC_HOST_CTRL_CHIPREV 0xffff0000 122#define MISC_HOST_CTRL_CHIPREV_SHIFT 16 123 124#define CHIPREV_ID_5700_A0 0x7000 125#define CHIPREV_ID_5700_A1 0x7001 126#define CHIPREV_ID_5700_B0 0x7100 127#define CHIPREV_ID_5700_B1 0x7101 128#define CHIPREV_ID_5700_B3 0x7102 129#define CHIPREV_ID_5700_ALTIMA 0x7104 130#define CHIPREV_ID_5700_C0 0x7200 131#define CHIPREV_ID_5701_A0 0x0000 132#define CHIPREV_ID_5701_B0 0x0100 133#define CHIPREV_ID_5701_B2 0x0102 134#define CHIPREV_ID_5701_B5 0x0105 135#define CHIPREV_ID_5703_A0 0x1000 136#define CHIPREV_ID_5703_A1 0x1001 137#define CHIPREV_ID_5703_A2 0x1002 138#define CHIPREV_ID_5703_A3 0x1003 139#define CHIPREV_ID_5704_A0 0x2000 140#define CHIPREV_ID_5704_A1 0x2001 141#define CHIPREV_ID_5704_A2 0x2002 142#define CHIPREV_ID_5704_A3 0x2003 143#define CHIPREV_ID_5705_A0 0x3000 144#define CHIPREV_ID_5705_A1 0x3001 145#define CHIPREV_ID_5705_A2 0x3002 146#define CHIPREV_ID_5705_A3 0x3003 147#define CHIPREV_ID_5750_A0 0x4000 148#define CHIPREV_ID_5750_A1 0x4001 149#define CHIPREV_ID_5750_A3 0x4003 150#define CHIPREV_ID_5750_C2 0x4202 151#define CHIPREV_ID_5752_A0_HW 0x5000 152#define CHIPREV_ID_5752_A0 0x6000 153#define CHIPREV_ID_5752_A1 0x6001 154#define CHIPREV_ID_5714_A2 0x9002 155#define CHIPREV_ID_5906_A1 0xc001 156#define CHIPREV_ID_57780_A0 0x57780000 157#define CHIPREV_ID_57780_A1 0x57780001 158#define CHIPREV_ID_5717_A0 0x05717000 159#define CHIPREV_ID_5717_C0 0x05717200 160#define CHIPREV_ID_57765_A0 0x57785000 161#define CHIPREV_ID_5719_A0 0x05719000 162#define CHIPREV_ID_5720_A0 0x05720000 163#define CHIPREV_ID_5762_A0 0x05762000 164 165#define ASIC_REV_5700 0x07 166#define ASIC_REV_5701 0x00 167#define ASIC_REV_5703 0x01 168#define ASIC_REV_5704 0x02 169#define ASIC_REV_5705 0x03 170#define ASIC_REV_5750 0x04 171#define ASIC_REV_5752 0x06 172#define ASIC_REV_5780 0x08 173#define ASIC_REV_5714 0x09 174#define ASIC_REV_5755 0x0a 175#define ASIC_REV_5787 0x0b 176#define ASIC_REV_5906 0x0c 177#define ASIC_REV_USE_PROD_ID_REG 0x0f 178#define ASIC_REV_5784 0x5784 179#define ASIC_REV_5761 0x5761 180#define ASIC_REV_5785 0x5785 181#define ASIC_REV_57780 0x57780 182#define ASIC_REV_5717 0x5717 183#define ASIC_REV_57765 0x57785 184#define ASIC_REV_5719 0x5719 185#define ASIC_REV_5720 0x5720 186#define ASIC_REV_57766 0x57766 187#define ASIC_REV_5762 0x5762 188#define CHIPREV_5700_AX 0x70 189#define CHIPREV_5700_BX 0x71 190#define CHIPREV_5700_CX 0x72 191#define CHIPREV_5701_AX 0x00 192#define CHIPREV_5703_AX 0x10 193#define CHIPREV_5704_AX 0x20 194#define CHIPREV_5704_BX 0x21 195#define CHIPREV_5750_AX 0x40 196#define CHIPREV_5750_BX 0x41 197#define CHIPREV_5784_AX 0x57840 198#define CHIPREV_5761_AX 0x57610 199#define CHIPREV_57765_AX 0x577650 200#define METAL_REV_A0 0x00 201#define METAL_REV_A1 0x01 202#define METAL_REV_B0 0x00 203#define METAL_REV_B1 0x01 204#define METAL_REV_B2 0x02 205#define TG3PCI_DMA_RW_CTRL 0x0000006c 206#define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001 207#define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080 208#define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380 209#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 210#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 211#define DMA_RWCTRL_READ_BNDRY_16 0x00000100 212#define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100 213#define DMA_RWCTRL_READ_BNDRY_32 0x00000200 214#define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200 215#define DMA_RWCTRL_READ_BNDRY_64 0x00000300 216#define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300 217#define DMA_RWCTRL_READ_BNDRY_128 0x00000400 218#define DMA_RWCTRL_READ_BNDRY_256 0x00000500 219#define DMA_RWCTRL_READ_BNDRY_512 0x00000600 220#define DMA_RWCTRL_READ_BNDRY_1024 0x00000700 221#define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800 222#define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000 223#define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800 224#define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800 225#define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000 226#define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000 227#define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800 228#define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800 229#define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000 230#define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800 231#define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000 232#define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800 233#define DMA_RWCTRL_ONE_DMA 0x00004000 234#define DMA_RWCTRL_READ_WATER 0x00070000 235#define DMA_RWCTRL_READ_WATER_SHIFT 16 236#define DMA_RWCTRL_WRITE_WATER 0x00380000 237#define DMA_RWCTRL_WRITE_WATER_SHIFT 19 238#define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000 239#define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000 240#define DMA_RWCTRL_PCI_READ_CMD 0x0f000000 241#define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24 242#define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000 243#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28 244#define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000 245#define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000 246#define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000 247#define TG3PCI_PCISTATE 0x00000070 248#define PCISTATE_FORCE_RESET 0x00000001 249#define PCISTATE_INT_NOT_ACTIVE 0x00000002 250#define PCISTATE_CONV_PCI_MODE 0x00000004 251#define PCISTATE_BUS_SPEED_HIGH 0x00000008 252#define PCISTATE_BUS_32BIT 0x00000010 253#define PCISTATE_ROM_ENABLE 0x00000020 254#define PCISTATE_ROM_RETRY_ENABLE 0x00000040 255#define PCISTATE_FLAT_VIEW 0x00000100 256#define PCISTATE_RETRY_SAME_DMA 0x00002000 257#define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 258#define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 259#define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 260#define TG3PCI_CLOCK_CTRL 0x00000074 261#define CLOCK_CTRL_CORECLK_DISABLE 0x00000200 262#define CLOCK_CTRL_RXCLK_DISABLE 0x00000400 263#define CLOCK_CTRL_TXCLK_DISABLE 0x00000800 264#define CLOCK_CTRL_ALTCLK 0x00001000 265#define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000 266#define CLOCK_CTRL_44MHZ_CORE 0x00040000 267#define CLOCK_CTRL_625_CORE 0x00100000 268#define CLOCK_CTRL_FORCE_CLKRUN 0x00200000 269#define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000 270#define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000 271#define TG3PCI_REG_BASE_ADDR 0x00000078 272#define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c 273#define TG3PCI_REG_DATA 0x00000080 274#define TG3PCI_MEM_WIN_DATA 0x00000084 275#define TG3PCI_MISC_LOCAL_CTRL 0x00000090 276/* 0x94 --> 0x98 unused */ 277#define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */ 278#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */ 279/* 0xa8 --> 0xb8 unused */ 280#define TG3PCI_DUAL_MAC_CTRL 0x000000b8 281#define DUAL_MAC_CTRL_CH_MASK 0x00000003 282#define DUAL_MAC_CTRL_ID 0x00000004 283#define TG3PCI_PRODID_ASICREV 0x000000bc 284#define PROD_ID_ASIC_REV_MASK 0x0fffffff 285/* 0xc0 --> 0xf4 unused */ 286 287#define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4 288#define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc 289/* 0xf8 --> 0x200 unused */ 290 291#define TG3_CORR_ERR_STAT 0x00000110 292#define TG3_CORR_ERR_STAT_CLEAR 0xffffffff 293/* 0x114 --> 0x200 unused */ 294 295/* Mailbox registers */ 296#define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ 297#define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */ 298#define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */ 299#define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */ 300#define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */ 301#define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */ 302#define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */ 303#define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */ 304#define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */ 305#define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */ 306#define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */ 307#define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */ 308#define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */ 309#define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */ 310#define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \ 311 TG3_64BIT_REG_LOW) 312#define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */ 313#define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \ 314 TG3_64BIT_REG_LOW) 315#define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */ 316#define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */ 317#define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */ 318#define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */ 319#define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */ 320#define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */ 321#define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */ 322#define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */ 323#define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */ 324#define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */ 325#define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */ 326#define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */ 327#define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */ 328#define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */ 329#define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */ 330#define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */ 331#define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */ 332#define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */ 333#define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */ 334#define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */ 335#define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */ 336#define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */ 337#define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */ 338#define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */ 339#define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */ 340#define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */ 341#define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */ 342#define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */ 343#define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */ 344#define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */ 345#define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */ 346#define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */ 347#define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */ 348#define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */ 349#define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */ 350#define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */ 351#define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */ 352#define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */ 353#define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */ 354#define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */ 355#define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */ 356#define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */ 357#define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */ 358#define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */ 359#define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */ 360#define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */ 361#define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */ 362#define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */ 363#define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */ 364 365/* MAC control registers */ 366#define MAC_MODE 0x00000400 367#define MAC_MODE_RESET 0x00000001 368#define MAC_MODE_HALF_DUPLEX 0x00000002 369#define MAC_MODE_PORT_MODE_MASK 0x0000000c 370#define MAC_MODE_PORT_MODE_TBI 0x0000000c 371#define MAC_MODE_PORT_MODE_GMII 0x00000008 372#define MAC_MODE_PORT_MODE_MII 0x00000004 373#define MAC_MODE_PORT_MODE_NONE 0x00000000 374#define MAC_MODE_PORT_INT_LPBACK 0x00000010 375#define MAC_MODE_TAGGED_MAC_CTRL 0x00000080 376#define MAC_MODE_TX_BURSTING 0x00000100 377#define MAC_MODE_MAX_DEFER 0x00000200 378#define MAC_MODE_LINK_POLARITY 0x00000400 379#define MAC_MODE_RXSTAT_ENABLE 0x00000800 380#define MAC_MODE_RXSTAT_CLEAR 0x00001000 381#define MAC_MODE_RXSTAT_FLUSH 0x00002000 382#define MAC_MODE_TXSTAT_ENABLE 0x00004000 383#define MAC_MODE_TXSTAT_CLEAR 0x00008000 384#define MAC_MODE_TXSTAT_FLUSH 0x00010000 385#define MAC_MODE_SEND_CONFIGS 0x00020000 386#define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000 387#define MAC_MODE_ACPI_ENABLE 0x00080000 388#define MAC_MODE_MIP_ENABLE 0x00100000 389#define MAC_MODE_TDE_ENABLE 0x00200000 390#define MAC_MODE_RDE_ENABLE 0x00400000 391#define MAC_MODE_FHDE_ENABLE 0x00800000 392#define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000 393#define MAC_MODE_APE_RX_EN 0x08000000 394#define MAC_MODE_APE_TX_EN 0x10000000 395#define MAC_STATUS 0x00000404 396#define MAC_STATUS_PCS_SYNCED 0x00000001 397#define MAC_STATUS_SIGNAL_DET 0x00000002 398#define MAC_STATUS_RCVD_CFG 0x00000004 399#define MAC_STATUS_CFG_CHANGED 0x00000008 400#define MAC_STATUS_SYNC_CHANGED 0x00000010 401#define MAC_STATUS_PORT_DEC_ERR 0x00000400 402#define MAC_STATUS_LNKSTATE_CHANGED 0x00001000 403#define MAC_STATUS_MI_COMPLETION 0x00400000 404#define MAC_STATUS_MI_INTERRUPT 0x00800000 405#define MAC_STATUS_AP_ERROR 0x01000000 406#define MAC_STATUS_ODI_ERROR 0x02000000 407#define MAC_STATUS_RXSTAT_OVERRUN 0x04000000 408#define MAC_STATUS_TXSTAT_OVERRUN 0x08000000 409#define MAC_EVENT 0x00000408 410#define MAC_EVENT_PORT_DECODE_ERR 0x00000400 411#define MAC_EVENT_LNKSTATE_CHANGED 0x00001000 412#define MAC_EVENT_MI_COMPLETION 0x00400000 413#define MAC_EVENT_MI_INTERRUPT 0x00800000 414#define MAC_EVENT_AP_ERROR 0x01000000 415#define MAC_EVENT_ODI_ERROR 0x02000000 416#define MAC_EVENT_RXSTAT_OVERRUN 0x04000000 417#define MAC_EVENT_TXSTAT_OVERRUN 0x08000000 418#define MAC_LED_CTRL 0x0000040c 419#define LED_CTRL_LNKLED_OVERRIDE 0x00000001 420#define LED_CTRL_1000MBPS_ON 0x00000002 421#define LED_CTRL_100MBPS_ON 0x00000004 422#define LED_CTRL_10MBPS_ON 0x00000008 423#define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010 424#define LED_CTRL_TRAFFIC_BLINK 0x00000020 425#define LED_CTRL_TRAFFIC_LED 0x00000040 426#define LED_CTRL_1000MBPS_STATUS 0x00000080 427#define LED_CTRL_100MBPS_STATUS 0x00000100 428#define LED_CTRL_10MBPS_STATUS 0x00000200 429#define LED_CTRL_TRAFFIC_STATUS 0x00000400 430#define LED_CTRL_MODE_MAC 0x00000000 431#define LED_CTRL_MODE_PHY_1 0x00000800 432#define LED_CTRL_MODE_PHY_2 0x00001000 433#define LED_CTRL_MODE_SHASTA_MAC 0x00002000 434#define LED_CTRL_MODE_SHARED 0x00004000 435#define LED_CTRL_MODE_COMBO 0x00008000 436#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 437#define LED_CTRL_BLINK_RATE_SHIFT 19 438#define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000 439#define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000 440#define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */ 441#define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */ 442#define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */ 443#define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */ 444#define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */ 445#define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */ 446#define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */ 447#define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */ 448#define MAC_ACPI_MBUF_PTR 0x00000430 449#define MAC_ACPI_LEN_OFFSET 0x00000434 450#define ACPI_LENOFF_LEN_MASK 0x0000ffff 451#define ACPI_LENOFF_LEN_SHIFT 0 452#define ACPI_LENOFF_OFF_MASK 0x0fff0000 453#define ACPI_LENOFF_OFF_SHIFT 16 454#define MAC_TX_BACKOFF_SEED 0x00000438 455#define TX_BACKOFF_SEED_MASK 0x000003ff 456#define MAC_RX_MTU_SIZE 0x0000043c 457#define RX_MTU_SIZE_MASK 0x0000ffff 458#define MAC_PCS_TEST 0x00000440 459#define PCS_TEST_PATTERN_MASK 0x000fffff 460#define PCS_TEST_PATTERN_SHIFT 0 461#define PCS_TEST_ENABLE 0x00100000 462#define MAC_TX_AUTO_NEG 0x00000444 463#define TX_AUTO_NEG_MASK 0x0000ffff 464#define TX_AUTO_NEG_SHIFT 0 465#define MAC_RX_AUTO_NEG 0x00000448 466#define RX_AUTO_NEG_MASK 0x0000ffff 467#define RX_AUTO_NEG_SHIFT 0 468#define MAC_MI_COM 0x0000044c 469#define MI_COM_CMD_MASK 0x0c000000 470#define MI_COM_CMD_WRITE 0x04000000 471#define MI_COM_CMD_READ 0x08000000 472#define MI_COM_READ_FAILED 0x10000000 473#define MI_COM_START 0x20000000 474#define MI_COM_BUSY 0x20000000 475#define MI_COM_PHY_ADDR_MASK 0x03e00000 476#define MI_COM_PHY_ADDR_SHIFT 21 477#define MI_COM_REG_ADDR_MASK 0x001f0000 478#define MI_COM_REG_ADDR_SHIFT 16 479#define MI_COM_DATA_MASK 0x0000ffff 480#define MAC_MI_STAT 0x00000450 481#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001 482#define MAC_MI_STAT_10MBPS_MODE 0x00000002 483#define MAC_MI_MODE 0x00000454 484#define MAC_MI_MODE_CLK_10MHZ 0x00000001 485#define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002 486#define MAC_MI_MODE_AUTO_POLL 0x00000010 487#define MAC_MI_MODE_500KHZ_CONST 0x00008000 488#define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */ 489#define MAC_AUTO_POLL_STATUS 0x00000458 490#define MAC_AUTO_POLL_ERROR 0x00000001 491#define MAC_TX_MODE 0x0000045c 492#define TX_MODE_RESET 0x00000001 493#define TX_MODE_ENABLE 0x00000002 494#define TX_MODE_FLOW_CTRL_ENABLE 0x00000010 495#define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020 496#define TX_MODE_LONG_PAUSE_ENABLE 0x00000040 497#define TX_MODE_MBUF_LOCKUP_FIX 0x00000100 498#define TX_MODE_JMB_FRM_LEN 0x00400000 499#define TX_MODE_CNT_DN_MODE 0x00800000 500#define MAC_TX_STATUS 0x00000460 501#define TX_STATUS_XOFFED 0x00000001 502#define TX_STATUS_SENT_XOFF 0x00000002 503#define TX_STATUS_SENT_XON 0x00000004 504#define TX_STATUS_LINK_UP 0x00000008 505#define TX_STATUS_ODI_UNDERRUN 0x00000010 506#define TX_STATUS_ODI_OVERRUN 0x00000020 507#define MAC_TX_LENGTHS 0x00000464 508#define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff 509#define TX_LENGTHS_SLOT_TIME_SHIFT 0 510#define TX_LENGTHS_IPG_MASK 0x00000f00 511#define TX_LENGTHS_IPG_SHIFT 8 512#define TX_LENGTHS_IPG_CRS_MASK 0x00003000 513#define TX_LENGTHS_IPG_CRS_SHIFT 12 514#define TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000 515#define TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000 516#define MAC_RX_MODE 0x00000468 517#define RX_MODE_RESET 0x00000001 518#define RX_MODE_ENABLE 0x00000002 519#define RX_MODE_FLOW_CTRL_ENABLE 0x00000004 520#define RX_MODE_KEEP_MAC_CTRL 0x00000008 521#define RX_MODE_KEEP_PAUSE 0x00000010 522#define RX_MODE_ACCEPT_OVERSIZED 0x00000020 523#define RX_MODE_ACCEPT_RUNTS 0x00000040 524#define RX_MODE_LEN_CHECK 0x00000080 525#define RX_MODE_PROMISC 0x00000100 526#define RX_MODE_NO_CRC_CHECK 0x00000200 527#define RX_MODE_KEEP_VLAN_TAG 0x00000400 528#define RX_MODE_RSS_IPV4_HASH_EN 0x00010000 529#define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000 530#define RX_MODE_RSS_IPV6_HASH_EN 0x00040000 531#define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000 532#define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000 533#define RX_MODE_RSS_ENABLE 0x00800000 534#define RX_MODE_IPV6_CSUM_ENABLE 0x01000000 535#define MAC_RX_STATUS 0x0000046c 536#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001 537#define RX_STATUS_XOFF_RCVD 0x00000002 538#define RX_STATUS_XON_RCVD 0x00000004 539#define MAC_HASH_REG_0 0x00000470 540#define MAC_HASH_REG_1 0x00000474 541#define MAC_HASH_REG_2 0x00000478 542#define MAC_HASH_REG_3 0x0000047c 543#define MAC_RCV_RULE_0 0x00000480 544#define MAC_RCV_VALUE_0 0x00000484 545#define MAC_RCV_RULE_1 0x00000488 546#define MAC_RCV_VALUE_1 0x0000048c 547#define MAC_RCV_RULE_2 0x00000490 548#define MAC_RCV_VALUE_2 0x00000494 549#define MAC_RCV_RULE_3 0x00000498 550#define MAC_RCV_VALUE_3 0x0000049c 551#define MAC_RCV_RULE_4 0x000004a0 552#define MAC_RCV_VALUE_4 0x000004a4 553#define MAC_RCV_RULE_5 0x000004a8 554#define MAC_RCV_VALUE_5 0x000004ac 555#define MAC_RCV_RULE_6 0x000004b0 556#define MAC_RCV_VALUE_6 0x000004b4 557#define MAC_RCV_RULE_7 0x000004b8 558#define MAC_RCV_VALUE_7 0x000004bc 559#define MAC_RCV_RULE_8 0x000004c0 560#define MAC_RCV_VALUE_8 0x000004c4 561#define MAC_RCV_RULE_9 0x000004c8 562#define MAC_RCV_VALUE_9 0x000004cc 563#define MAC_RCV_RULE_10 0x000004d0 564#define MAC_RCV_VALUE_10 0x000004d4 565#define MAC_RCV_RULE_11 0x000004d8 566#define MAC_RCV_VALUE_11 0x000004dc 567#define MAC_RCV_RULE_12 0x000004e0 568#define MAC_RCV_VALUE_12 0x000004e4 569#define MAC_RCV_RULE_13 0x000004e8 570#define MAC_RCV_VALUE_13 0x000004ec 571#define MAC_RCV_RULE_14 0x000004f0 572#define MAC_RCV_VALUE_14 0x000004f4 573#define MAC_RCV_RULE_15 0x000004f8 574#define MAC_RCV_VALUE_15 0x000004fc 575#define RCV_RULE_DISABLE_MASK 0x7fffffff 576#define MAC_RCV_RULE_CFG 0x00000500 577#define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008 578#define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504 579/* 0x508 --> 0x520 unused */ 580#define MAC_HASHREGU_0 0x00000520 581#define MAC_HASHREGU_1 0x00000524 582#define MAC_HASHREGU_2 0x00000528 583#define MAC_HASHREGU_3 0x0000052c 584#define MAC_EXTADDR_0_HIGH 0x00000530 585#define MAC_EXTADDR_0_LOW 0x00000534 586#define MAC_EXTADDR_1_HIGH 0x00000538 587#define MAC_EXTADDR_1_LOW 0x0000053c 588#define MAC_EXTADDR_2_HIGH 0x00000540 589#define MAC_EXTADDR_2_LOW 0x00000544 590#define MAC_EXTADDR_3_HIGH 0x00000548 591#define MAC_EXTADDR_3_LOW 0x0000054c 592#define MAC_EXTADDR_4_HIGH 0x00000550 593#define MAC_EXTADDR_4_LOW 0x00000554 594#define MAC_EXTADDR_5_HIGH 0x00000558 595#define MAC_EXTADDR_5_LOW 0x0000055c 596#define MAC_EXTADDR_6_HIGH 0x00000560 597#define MAC_EXTADDR_6_LOW 0x00000564 598#define MAC_EXTADDR_7_HIGH 0x00000568 599#define MAC_EXTADDR_7_LOW 0x0000056c 600#define MAC_EXTADDR_8_HIGH 0x00000570 601#define MAC_EXTADDR_8_LOW 0x00000574 602#define MAC_EXTADDR_9_HIGH 0x00000578 603#define MAC_EXTADDR_9_LOW 0x0000057c 604#define MAC_EXTADDR_10_HIGH 0x00000580 605#define MAC_EXTADDR_10_LOW 0x00000584 606#define MAC_EXTADDR_11_HIGH 0x00000588 607#define MAC_EXTADDR_11_LOW 0x0000058c 608#define MAC_SERDES_CFG 0x00000590 609#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000 610#define MAC_SERDES_STAT 0x00000594 611/* 0x598 --> 0x5a0 unused */ 612#define MAC_PHYCFG1 0x000005a0 613#define MAC_PHYCFG1_RGMII_INT 0x00000001 614#define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0 615#define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000 616#define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000 617#define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000 618#define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000 619#define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000 620#define MAC_PHYCFG1_TXC_DRV 0x20000000 621#define MAC_PHYCFG2 0x000005a4 622#define MAC_PHYCFG2_INBAND_ENABLE 0x00000001 623#define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0 624#define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0 625#define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100 626#define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000 627#define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0 628#define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00 629#define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600 630#define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400 631#define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800 632#define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000 633#define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000 634#define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000 635#define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000 636#define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000 637#define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000 638#define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000 639#define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000 640#define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000 641#define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000 642#define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000 643#define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000 644#define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000 645#define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000 646#define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000 647#define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000 648#define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000 649#define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000 650#define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000 651#define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000 652#define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000 653#define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000 654#define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000 655#define MAC_PHYCFG2_ACT_MASK_50610 0x01000000 656#define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000 657#define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000 658#define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000 659#define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000 660#define MAC_PHYCFG2_ACT_COMP_50610 0x00000000 661#define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000 662#define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000 663#define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000 664#define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000 665#define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000 666#define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000 667#define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000 668#define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000 669#define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000 670#define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000 671#define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000 672#define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000 673#define MAC_PHYCFG2_50610_LED_MODES \ 674 (MAC_PHYCFG2_EMODE_MASK_50610 | \ 675 MAC_PHYCFG2_EMODE_COMP_50610 | \ 676 MAC_PHYCFG2_FMODE_MASK_50610 | \ 677 MAC_PHYCFG2_FMODE_COMP_50610 | \ 678 MAC_PHYCFG2_GMODE_MASK_50610 | \ 679 MAC_PHYCFG2_GMODE_COMP_50610 | \ 680 MAC_PHYCFG2_ACT_MASK_50610 | \ 681 MAC_PHYCFG2_ACT_COMP_50610 | \ 682 MAC_PHYCFG2_QUAL_MASK_50610 | \ 683 MAC_PHYCFG2_QUAL_COMP_50610) 684#define MAC_PHYCFG2_AC131_LED_MODES \ 685 (MAC_PHYCFG2_EMODE_MASK_AC131 | \ 686 MAC_PHYCFG2_EMODE_COMP_AC131 | \ 687 MAC_PHYCFG2_FMODE_MASK_AC131 | \ 688 MAC_PHYCFG2_FMODE_COMP_AC131 | \ 689 MAC_PHYCFG2_GMODE_MASK_AC131 | \ 690 MAC_PHYCFG2_GMODE_COMP_AC131 | \ 691 MAC_PHYCFG2_ACT_MASK_AC131 | \ 692 MAC_PHYCFG2_ACT_COMP_AC131 | \ 693 MAC_PHYCFG2_QUAL_MASK_AC131 | \ 694 MAC_PHYCFG2_QUAL_COMP_AC131) 695#define MAC_PHYCFG2_RTL8211C_LED_MODES \ 696 (MAC_PHYCFG2_EMODE_MASK_RT8211 | \ 697 MAC_PHYCFG2_EMODE_COMP_RT8211 | \ 698 MAC_PHYCFG2_FMODE_MASK_RT8211 | \ 699 MAC_PHYCFG2_FMODE_COMP_RT8211 | \ 700 MAC_PHYCFG2_GMODE_MASK_RT8211 | \ 701 MAC_PHYCFG2_GMODE_COMP_RT8211 | \ 702 MAC_PHYCFG2_ACT_MASK_RT8211 | \ 703 MAC_PHYCFG2_ACT_COMP_RT8211 | \ 704 MAC_PHYCFG2_QUAL_MASK_RT8211 | \ 705 MAC_PHYCFG2_QUAL_COMP_RT8211) 706#define MAC_PHYCFG2_RTL8201E_LED_MODES \ 707 (MAC_PHYCFG2_EMODE_MASK_RT8201 | \ 708 MAC_PHYCFG2_EMODE_COMP_RT8201 | \ 709 MAC_PHYCFG2_FMODE_MASK_RT8201 | \ 710 MAC_PHYCFG2_FMODE_COMP_RT8201 | \ 711 MAC_PHYCFG2_GMODE_MASK_RT8201 | \ 712 MAC_PHYCFG2_GMODE_COMP_RT8201 | \ 713 MAC_PHYCFG2_ACT_MASK_RT8201 | \ 714 MAC_PHYCFG2_ACT_COMP_RT8201 | \ 715 MAC_PHYCFG2_QUAL_MASK_RT8201 | \ 716 MAC_PHYCFG2_QUAL_COMP_RT8201) 717#define MAC_EXT_RGMII_MODE 0x000005a8 718#define MAC_RGMII_MODE_TX_ENABLE 0x00000001 719#define MAC_RGMII_MODE_TX_LOWPWR 0x00000002 720#define MAC_RGMII_MODE_TX_RESET 0x00000004 721#define MAC_RGMII_MODE_RX_INT_B 0x00000100 722#define MAC_RGMII_MODE_RX_QUALITY 0x00000200 723#define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400 724#define MAC_RGMII_MODE_RX_ENG_DET 0x00000800 725/* 0x5ac --> 0x5b0 unused */ 726#define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */ 727#define SERDES_RX_SIG_DETECT 0x00000400 728#define SG_DIG_CTRL 0x000005b0 729#define SG_DIG_USING_HW_AUTONEG 0x80000000 730#define SG_DIG_SOFT_RESET 0x40000000 731#define SG_DIG_DISABLE_LINKRDY 0x20000000 732#define SG_DIG_CRC16_CLEAR_N 0x01000000 733#define SG_DIG_EN10B 0x00800000 734#define SG_DIG_CLEAR_STATUS 0x00400000 735#define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000 736#define SG_DIG_LOCAL_LINK_STATUS 0x00100000 737#define SG_DIG_SPEED_STATUS_MASK 0x000c0000 738#define SG_DIG_SPEED_STATUS_SHIFT 18 739#define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000 740#define SG_DIG_RESTART_AUTONEG 0x00010000 741#define SG_DIG_FIBER_MODE 0x00008000 742#define SG_DIG_REMOTE_FAULT_MASK 0x00006000 743#define SG_DIG_PAUSE_MASK 0x00001800 744#define SG_DIG_PAUSE_CAP 0x00000800 745#define SG_DIG_ASYM_PAUSE 0x00001000 746#define SG_DIG_GBIC_ENABLE 0x00000400 747#define SG_DIG_CHECK_END_ENABLE 0x00000200 748#define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100 749#define SG_DIG_CLOCK_PHASE_SELECT 0x00000080 750#define SG_DIG_GMII_INPUT_SELECT 0x00000040 751#define SG_DIG_MRADV_CRC16_SELECT 0x00000020 752#define SG_DIG_COMMA_DETECT_ENABLE 0x00000010 753#define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008 754#define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004 755#define SG_DIG_REMOTE_LOOPBACK 0x00000002 756#define SG_DIG_LOOPBACK 0x00000001 757#define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \ 758 SG_DIG_LOCAL_DUPLEX_STATUS | \ 759 SG_DIG_LOCAL_LINK_STATUS | \ 760 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \ 761 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE) 762#define SG_DIG_STATUS 0x000005b4 763#define SG_DIG_CRC16_BUS_MASK 0xffff0000 764#define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */ 765#define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */ 766#define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */ 767#define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */ 768#define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */ 769#define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */ 770#define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0 771#define SG_DIG_IS_SERDES 0x00000100 772#define SG_DIG_COMMA_DETECTOR 0x00000008 773#define SG_DIG_MAC_ACK_STATUS 0x00000004 774#define SG_DIG_AUTONEG_COMPLETE 0x00000002 775#define SG_DIG_AUTONEG_ERROR 0x00000001 776#define TG3_TX_TSTAMP_LSB 0x000005c0 777#define TG3_TX_TSTAMP_MSB 0x000005c4 778#define TG3_TSTAMP_MASK 0x7fffffffffffffffLL 779/* 0x5c8 --> 0x600 unused */ 780#define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */ 781#define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */ 782/* 0x624 --> 0x670 unused */ 783 784#define MAC_RSS_INDIR_TBL_0 0x00000630 785 786#define MAC_RSS_HASH_KEY_0 0x00000670 787#define MAC_RSS_HASH_KEY_1 0x00000674 788#define MAC_RSS_HASH_KEY_2 0x00000678 789#define MAC_RSS_HASH_KEY_3 0x0000067c 790#define MAC_RSS_HASH_KEY_4 0x00000680 791#define MAC_RSS_HASH_KEY_5 0x00000684 792#define MAC_RSS_HASH_KEY_6 0x00000688 793#define MAC_RSS_HASH_KEY_7 0x0000068c 794#define MAC_RSS_HASH_KEY_8 0x00000690 795#define MAC_RSS_HASH_KEY_9 0x00000694 796/* 0x698 --> 0x6b0 unused */ 797 798#define TG3_RX_TSTAMP_LSB 0x000006b0 799#define TG3_RX_TSTAMP_MSB 0x000006b4 800/* 0x6b8 --> 0x6c8 unused */ 801 802#define TG3_RX_PTP_CTL 0x000006c8 803#define TG3_RX_PTP_CTL_SYNC_EVNT 0x00000001 804#define TG3_RX_PTP_CTL_DELAY_REQ 0x00000002 805#define TG3_RX_PTP_CTL_PDLAY_REQ 0x00000004 806#define TG3_RX_PTP_CTL_PDLAY_RES 0x00000008 807#define TG3_RX_PTP_CTL_ALL_V1_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \ 808 TG3_RX_PTP_CTL_DELAY_REQ) 809#define TG3_RX_PTP_CTL_ALL_V2_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \ 810 TG3_RX_PTP_CTL_DELAY_REQ | \ 811 TG3_RX_PTP_CTL_PDLAY_REQ | \ 812 TG3_RX_PTP_CTL_PDLAY_RES) 813#define TG3_RX_PTP_CTL_FOLLOW_UP 0x00000100 814#define TG3_RX_PTP_CTL_DELAY_RES 0x00000200 815#define TG3_RX_PTP_CTL_PDRES_FLW_UP 0x00000400 816#define TG3_RX_PTP_CTL_ANNOUNCE 0x00000800 817#define TG3_RX_PTP_CTL_SIGNALING 0x00001000 818#define TG3_RX_PTP_CTL_MANAGEMENT 0x00002000 819#define TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN 0x00800000 820#define TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN 0x01000000 821#define TG3_RX_PTP_CTL_RX_PTP_V2_EN (TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | \ 822 TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN) 823#define TG3_RX_PTP_CTL_RX_PTP_V1_EN 0x02000000 824#define TG3_RX_PTP_CTL_HWTS_INTERLOCK 0x04000000 825/* 0x6cc --> 0x800 unused */ 826 827#define MAC_TX_STATS_OCTETS 0x00000800 828#define MAC_TX_STATS_RESV1 0x00000804 829#define MAC_TX_STATS_COLLISIONS 0x00000808 830#define MAC_TX_STATS_XON_SENT 0x0000080c 831#define MAC_TX_STATS_XOFF_SENT 0x00000810 832#define MAC_TX_STATS_RESV2 0x00000814 833#define MAC_TX_STATS_MAC_ERRORS 0x00000818 834#define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c 835#define MAC_TX_STATS_MULT_COLLISIONS 0x00000820 836#define MAC_TX_STATS_DEFERRED 0x00000824 837#define MAC_TX_STATS_RESV3 0x00000828 838#define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c 839#define MAC_TX_STATS_LATE_COL 0x00000830 840#define MAC_TX_STATS_RESV4_1 0x00000834 841#define MAC_TX_STATS_RESV4_2 0x00000838 842#define MAC_TX_STATS_RESV4_3 0x0000083c 843#define MAC_TX_STATS_RESV4_4 0x00000840 844#define MAC_TX_STATS_RESV4_5 0x00000844 845#define MAC_TX_STATS_RESV4_6 0x00000848 846#define MAC_TX_STATS_RESV4_7 0x0000084c 847#define MAC_TX_STATS_RESV4_8 0x00000850 848#define MAC_TX_STATS_RESV4_9 0x00000854 849#define MAC_TX_STATS_RESV4_10 0x00000858 850#define MAC_TX_STATS_RESV4_11 0x0000085c 851#define MAC_TX_STATS_RESV4_12 0x00000860 852#define MAC_TX_STATS_RESV4_13 0x00000864 853#define MAC_TX_STATS_RESV4_14 0x00000868 854#define MAC_TX_STATS_UCAST 0x0000086c 855#define MAC_TX_STATS_MCAST 0x00000870 856#define MAC_TX_STATS_BCAST 0x00000874 857#define MAC_TX_STATS_RESV5_1 0x00000878 858#define MAC_TX_STATS_RESV5_2 0x0000087c 859#define MAC_RX_STATS_OCTETS 0x00000880 860#define MAC_RX_STATS_RESV1 0x00000884 861#define MAC_RX_STATS_FRAGMENTS 0x00000888 862#define MAC_RX_STATS_UCAST 0x0000088c 863#define MAC_RX_STATS_MCAST 0x00000890 864#define MAC_RX_STATS_BCAST 0x00000894 865#define MAC_RX_STATS_FCS_ERRORS 0x00000898 866#define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c 867#define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0 868#define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4 869#define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8 870#define MAC_RX_STATS_XOFF_ENTERED 0x000008ac 871#define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0 872#define MAC_RX_STATS_JABBERS 0x000008b4 873#define MAC_RX_STATS_UNDERSIZE 0x000008b8 874/* 0x8bc --> 0xc00 unused */ 875 876/* Send data initiator control registers */ 877#define SNDDATAI_MODE 0x00000c00 878#define SNDDATAI_MODE_RESET 0x00000001 879#define SNDDATAI_MODE_ENABLE 0x00000002 880#define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004 881#define SNDDATAI_STATUS 0x00000c04 882#define SNDDATAI_STATUS_STAT_OFLOW 0x00000004 883#define SNDDATAI_STATSCTRL 0x00000c08 884#define SNDDATAI_SCTRL_ENABLE 0x00000001 885#define SNDDATAI_SCTRL_FASTUPD 0x00000002 886#define SNDDATAI_SCTRL_CLEAR 0x00000004 887#define SNDDATAI_SCTRL_FLUSH 0x00000008 888#define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010 889#define SNDDATAI_STATSENAB 0x00000c0c 890#define SNDDATAI_STATSINCMASK 0x00000c10 891#define ISO_PKT_TX 0x00000c20 892/* 0xc24 --> 0xc80 unused */ 893#define SNDDATAI_COS_CNT_0 0x00000c80 894#define SNDDATAI_COS_CNT_1 0x00000c84 895#define SNDDATAI_COS_CNT_2 0x00000c88 896#define SNDDATAI_COS_CNT_3 0x00000c8c 897#define SNDDATAI_COS_CNT_4 0x00000c90 898#define SNDDATAI_COS_CNT_5 0x00000c94 899#define SNDDATAI_COS_CNT_6 0x00000c98 900#define SNDDATAI_COS_CNT_7 0x00000c9c 901#define SNDDATAI_COS_CNT_8 0x00000ca0 902#define SNDDATAI_COS_CNT_9 0x00000ca4 903#define SNDDATAI_COS_CNT_10 0x00000ca8 904#define SNDDATAI_COS_CNT_11 0x00000cac 905#define SNDDATAI_COS_CNT_12 0x00000cb0 906#define SNDDATAI_COS_CNT_13 0x00000cb4 907#define SNDDATAI_COS_CNT_14 0x00000cb8 908#define SNDDATAI_COS_CNT_15 0x00000cbc 909#define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0 910#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4 911#define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8 912#define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc 913#define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0 914#define SNDDATAI_INTERRUPTS_CNT 0x00000cd4 915#define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8 916#define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc 917/* 0xce0 --> 0x1000 unused */ 918 919/* Send data completion control registers */ 920#define SNDDATAC_MODE 0x00001000 921#define SNDDATAC_MODE_RESET 0x00000001 922#define SNDDATAC_MODE_ENABLE 0x00000002 923#define SNDDATAC_MODE_CDELAY 0x00000010 924/* 0x1004 --> 0x1400 unused */ 925 926/* Send BD ring selector */ 927#define SNDBDS_MODE 0x00001400 928#define SNDBDS_MODE_RESET 0x00000001 929#define SNDBDS_MODE_ENABLE 0x00000002 930#define SNDBDS_MODE_ATTN_ENABLE 0x00000004 931#define SNDBDS_STATUS 0x00001404 932#define SNDBDS_STATUS_ERROR_ATTN 0x00000004 933#define SNDBDS_HWDIAG 0x00001408 934/* 0x140c --> 0x1440 */ 935#define SNDBDS_SEL_CON_IDX_0 0x00001440 936#define SNDBDS_SEL_CON_IDX_1 0x00001444 937#define SNDBDS_SEL_CON_IDX_2 0x00001448 938#define SNDBDS_SEL_CON_IDX_3 0x0000144c 939#define SNDBDS_SEL_CON_IDX_4 0x00001450 940#define SNDBDS_SEL_CON_IDX_5 0x00001454 941#define SNDBDS_SEL_CON_IDX_6 0x00001458 942#define SNDBDS_SEL_CON_IDX_7 0x0000145c 943#define SNDBDS_SEL_CON_IDX_8 0x00001460 944#define SNDBDS_SEL_CON_IDX_9 0x00001464 945#define SNDBDS_SEL_CON_IDX_10 0x00001468 946#define SNDBDS_SEL_CON_IDX_11 0x0000146c 947#define SNDBDS_SEL_CON_IDX_12 0x00001470 948#define SNDBDS_SEL_CON_IDX_13 0x00001474 949#define SNDBDS_SEL_CON_IDX_14 0x00001478 950#define SNDBDS_SEL_CON_IDX_15 0x0000147c 951/* 0x1480 --> 0x1800 unused */ 952 953/* Send BD initiator control registers */ 954#define SNDBDI_MODE 0x00001800 955#define SNDBDI_MODE_RESET 0x00000001 956#define SNDBDI_MODE_ENABLE 0x00000002 957#define SNDBDI_MODE_ATTN_ENABLE 0x00000004 958#define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020 959#define SNDBDI_STATUS 0x00001804 960#define SNDBDI_STATUS_ERROR_ATTN 0x00000004 961#define SNDBDI_IN_PROD_IDX_0 0x00001808 962#define SNDBDI_IN_PROD_IDX_1 0x0000180c 963#define SNDBDI_IN_PROD_IDX_2 0x00001810 964#define SNDBDI_IN_PROD_IDX_3 0x00001814 965#define SNDBDI_IN_PROD_IDX_4 0x00001818 966#define SNDBDI_IN_PROD_IDX_5 0x0000181c 967#define SNDBDI_IN_PROD_IDX_6 0x00001820 968#define SNDBDI_IN_PROD_IDX_7 0x00001824 969#define SNDBDI_IN_PROD_IDX_8 0x00001828 970#define SNDBDI_IN_PROD_IDX_9 0x0000182c 971#define SNDBDI_IN_PROD_IDX_10 0x00001830 972#define SNDBDI_IN_PROD_IDX_11 0x00001834 973#define SNDBDI_IN_PROD_IDX_12 0x00001838 974#define SNDBDI_IN_PROD_IDX_13 0x0000183c 975#define SNDBDI_IN_PROD_IDX_14 0x00001840 976#define SNDBDI_IN_PROD_IDX_15 0x00001844 977/* 0x1848 --> 0x1c00 unused */ 978 979/* Send BD completion control registers */ 980#define SNDBDC_MODE 0x00001c00 981#define SNDBDC_MODE_RESET 0x00000001 982#define SNDBDC_MODE_ENABLE 0x00000002 983#define SNDBDC_MODE_ATTN_ENABLE 0x00000004 984/* 0x1c04 --> 0x2000 unused */ 985 986/* Receive list placement control registers */ 987#define RCVLPC_MODE 0x00002000 988#define RCVLPC_MODE_RESET 0x00000001 989#define RCVLPC_MODE_ENABLE 0x00000002 990#define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004 991#define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008 992#define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010 993#define RCVLPC_STATUS 0x00002004 994#define RCVLPC_STATUS_CLASS0 0x00000004 995#define RCVLPC_STATUS_MAPOOR 0x00000008 996#define RCVLPC_STATUS_STAT_OFLOW 0x00000010 997#define RCVLPC_LOCK 0x00002008 998#define RCVLPC_LOCK_REQ_MASK 0x0000ffff 999#define RCVLPC_LOCK_REQ_SHIFT 0 1000#define RCVLPC_LOCK_GRANT_MASK 0xffff0000 1001#define RCVLPC_LOCK_GRANT_SHIFT 16 1002#define RCVLPC_NON_EMPTY_BITS 0x0000200c 1003#define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff 1004#define RCVLPC_CONFIG 0x00002010 1005#define RCVLPC_STATSCTRL 0x00002014 1006#define RCVLPC_STATSCTRL_ENABLE 0x00000001 1007#define RCVLPC_STATSCTRL_FASTUPD 0x00000002 1008#define RCVLPC_STATS_ENABLE 0x00002018 1009#define RCVLPC_STATSENAB_ASF_FIX 0x00000002 1010#define RCVLPC_STATSENAB_DACK_FIX 0x00040000 1011#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 1012#define RCVLPC_STATS_INCMASK 0x0000201c 1013/* 0x2020 --> 0x2100 unused */ 1014#define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */ 1015#define SELLST_TAIL 0x00000004 1016#define SELLST_CONT 0x00000008 1017#define SELLST_UNUSED 0x0000000c 1018#define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */ 1019#define RCVLPC_DROP_FILTER_CNT 0x00002240 1020#define RCVLPC_DMA_WQ_FULL_CNT 0x00002244 1021#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248 1022#define RCVLPC_NO_RCV_BD_CNT 0x0000224c 1023#define RCVLPC_IN_DISCARDS_CNT 0x00002250 1024#define RCVLPC_IN_ERRORS_CNT 0x00002254 1025#define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258 1026/* 0x225c --> 0x2400 unused */ 1027 1028/* Receive Data and Receive BD Initiator Control */ 1029#define RCVDBDI_MODE 0x00002400 1030#define RCVDBDI_MODE_RESET 0x00000001 1031#define RCVDBDI_MODE_ENABLE 0x00000002 1032#define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004 1033#define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008 1034#define RCVDBDI_MODE_INV_RING_SZ 0x00000010 1035#define RCVDBDI_MODE_LRG_RING_SZ 0x00010000 1036#define RCVDBDI_STATUS 0x00002404 1037#define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004 1038#define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008 1039#define RCVDBDI_STATUS_INV_RING_SZ 0x00000010 1040#define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408 1041/* 0x240c --> 0x2440 unused */ 1042#define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */ 1043#define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */ 1044#define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */ 1045#define RCVDBDI_JUMBO_CON_IDX 0x00002470 1046#define RCVDBDI_STD_CON_IDX 0x00002474 1047#define RCVDBDI_MINI_CON_IDX 0x00002478 1048/* 0x247c --> 0x2480 unused */ 1049#define RCVDBDI_BD_PROD_IDX_0 0x00002480 1050#define RCVDBDI_BD_PROD_IDX_1 0x00002484 1051#define RCVDBDI_BD_PROD_IDX_2 0x00002488 1052#define RCVDBDI_BD_PROD_IDX_3 0x0000248c 1053#define RCVDBDI_BD_PROD_IDX_4 0x00002490 1054#define RCVDBDI_BD_PROD_IDX_5 0x00002494 1055#define RCVDBDI_BD_PROD_IDX_6 0x00002498 1056#define RCVDBDI_BD_PROD_IDX_7 0x0000249c 1057#define RCVDBDI_BD_PROD_IDX_8 0x000024a0 1058#define RCVDBDI_BD_PROD_IDX_9 0x000024a4 1059#define RCVDBDI_BD_PROD_IDX_10 0x000024a8 1060#define RCVDBDI_BD_PROD_IDX_11 0x000024ac 1061#define RCVDBDI_BD_PROD_IDX_12 0x000024b0 1062#define RCVDBDI_BD_PROD_IDX_13 0x000024b4 1063#define RCVDBDI_BD_PROD_IDX_14 0x000024b8 1064#define RCVDBDI_BD_PROD_IDX_15 0x000024bc 1065#define RCVDBDI_HWDIAG 0x000024c0 1066/* 0x24c4 --> 0x2800 unused */ 1067 1068/* Receive Data Completion Control */ 1069#define RCVDCC_MODE 0x00002800 1070#define RCVDCC_MODE_RESET 0x00000001 1071#define RCVDCC_MODE_ENABLE 0x00000002 1072#define RCVDCC_MODE_ATTN_ENABLE 0x00000004 1073/* 0x2804 --> 0x2c00 unused */ 1074 1075/* Receive BD Initiator Control Registers */ 1076#define RCVBDI_MODE 0x00002c00 1077#define RCVBDI_MODE_RESET 0x00000001 1078#define RCVBDI_MODE_ENABLE 0x00000002 1079#define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004 1080#define RCVBDI_STATUS 0x00002c04 1081#define RCVBDI_STATUS_RCB_ATTN 0x00000004 1082#define RCVBDI_JUMBO_PROD_IDX 0x00002c08 1083#define RCVBDI_STD_PROD_IDX 0x00002c0c 1084#define RCVBDI_MINI_PROD_IDX 0x00002c10 1085#define RCVBDI_MINI_THRESH 0x00002c14 1086#define RCVBDI_STD_THRESH 0x00002c18 1087#define RCVBDI_JUMBO_THRESH 0x00002c1c 1088/* 0x2c20 --> 0x2d00 unused */ 1089 1090#define STD_REPLENISH_LWM 0x00002d00 1091#define JMB_REPLENISH_LWM 0x00002d04 1092/* 0x2d08 --> 0x3000 unused */ 1093 1094/* Receive BD Completion Control Registers */ 1095#define RCVCC_MODE 0x00003000 1096#define RCVCC_MODE_RESET 0x00000001 1097#define RCVCC_MODE_ENABLE 0x00000002 1098#define RCVCC_MODE_ATTN_ENABLE 0x00000004 1099#define RCVCC_STATUS 0x00003004 1100#define RCVCC_STATUS_ERROR_ATTN 0x00000004 1101#define RCVCC_JUMP_PROD_IDX 0x00003008 1102#define RCVCC_STD_PROD_IDX 0x0000300c 1103#define RCVCC_MINI_PROD_IDX 0x00003010 1104/* 0x3014 --> 0x3400 unused */ 1105 1106/* Receive list selector control registers */ 1107#define RCVLSC_MODE 0x00003400 1108#define RCVLSC_MODE_RESET 0x00000001 1109#define RCVLSC_MODE_ENABLE 0x00000002 1110#define RCVLSC_MODE_ATTN_ENABLE 0x00000004 1111#define RCVLSC_STATUS 0x00003404 1112#define RCVLSC_STATUS_ERROR_ATTN 0x00000004 1113/* 0x3408 --> 0x3600 unused */ 1114 1115#define TG3_CPMU_DRV_STATUS 0x0000344c 1116 1117/* CPMU registers */ 1118#define TG3_CPMU_CTRL 0x00003600 1119#define CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1120#define CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1121#define CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1122#define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1123#define TG3_CPMU_LSPD_10MB_CLK 0x00003604 1124#define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000 1125#define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1126/* 0x3608 --> 0x360c unused */ 1127 1128#define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c 1129#define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1130#define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1131#define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000 1132#define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610 1133#define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000 1134#define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1135/* 0x3614 --> 0x361c unused */ 1136 1137#define TG3_CPMU_HST_ACC 0x0000361c 1138#define CPMU_HST_ACC_MACCLK_MASK 0x001f0000 1139#define CPMU_HST_ACC_MACCLK_6_25 0x00130000 1140/* 0x3620 --> 0x3630 unused */ 1141 1142#define TG3_CPMU_CLCK_ORIDE 0x00003624 1143#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1144 1145#define TG3_CPMU_STATUS 0x0000362c 1146#define TG3_CPMU_STATUS_FMSK_5717 0x20000000 1147#define TG3_CPMU_STATUS_FMSK_5719 0xc0000000 1148#define TG3_CPMU_STATUS_FSHFT_5719 30 1149 1150#define TG3_CPMU_CLCK_STAT 0x00003630 1151#define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000 1152#define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1153#define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1154#define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1155/* 0x3634 --> 0x365c unused */ 1156 1157#define TG3_CPMU_MUTEX_REQ 0x0000365c 1158#define CPMU_MUTEX_REQ_DRIVER 0x00001000 1159#define TG3_CPMU_MUTEX_GNT 0x00003660 1160#define CPMU_MUTEX_GNT_DRIVER 0x00001000 1161#define TG3_CPMU_PHY_STRAP 0x00003664 1162#define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1163#define TG3_CPMU_PADRNG_CTL 0x00003668 1164#define TG3_CPMU_PADRNG_CTL_RDIV2 0x00040000 1165/* 0x3664 --> 0x36b0 unused */ 1166 1167#define TG3_CPMU_EEE_MODE 0x000036b0 1168#define TG3_CPMU_EEEMD_APE_TX_DET_EN 0x00000004 1169#define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008 1170#define TG3_CPMU_EEEMD_SND_IDX_DET_EN 0x00000040 1171#define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080 1172#define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100 1173#define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200 1174#define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000 1175#define TG3_CPMU_EEE_DBTMR1 0x000036b4 1176#define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000 1177#define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000007ff 1178#define TG3_CPMU_EEE_DBTMR2 0x000036b8 1179#define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000 1180#define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000007ff 1181#define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc 1182#define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000 1183#define TG3_CPMU_EEE_LNKIDL_UART_IDL 0x00000004 1184#define TG3_CPMU_EEE_LNKIDL_APE_TX_MT 0x00000002 1185/* 0x36c0 --> 0x36d0 unused */ 1186 1187#define TG3_CPMU_EEE_CTRL 0x000036d0 1188#define TG3_CPMU_EEE_CTRL_EXIT_16_5_US 0x0000019d 1189#define TG3_CPMU_EEE_CTRL_EXIT_36_US 0x00000384 1190#define TG3_CPMU_EEE_CTRL_EXIT_20_1_US 0x000001f8 1191/* 0x36d4 --> 0x3800 unused */ 1192 1193/* Mbuf cluster free registers */ 1194#define MBFREE_MODE 0x00003800 1195#define MBFREE_MODE_RESET 0x00000001 1196#define MBFREE_MODE_ENABLE 0x00000002 1197#define MBFREE_STATUS 0x00003804 1198/* 0x3808 --> 0x3c00 unused */ 1199 1200/* Host coalescing control registers */ 1201#define HOSTCC_MODE 0x00003c00 1202#define HOSTCC_MODE_RESET 0x00000001 1203#define HOSTCC_MODE_ENABLE 0x00000002 1204#define HOSTCC_MODE_ATTN 0x00000004 1205#define HOSTCC_MODE_NOW 0x00000008 1206#define HOSTCC_MODE_FULL_STATUS 0x00000000 1207#define HOSTCC_MODE_64BYTE 0x00000080 1208#define HOSTCC_MODE_32BYTE 0x00000100 1209#define HOSTCC_MODE_CLRTICK_RXBD 0x00000200 1210#define HOSTCC_MODE_CLRTICK_TXBD 0x00000400 1211#define HOSTCC_MODE_NOINT_ON_NOW 0x00000800 1212#define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000 1213#define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000 1214#define HOSTCC_STATUS 0x00003c04 1215#define HOSTCC_STATUS_ERROR_ATTN 0x00000004 1216#define HOSTCC_RXCOL_TICKS 0x00003c08 1217#define LOW_RXCOL_TICKS 0x00000032 1218#define LOW_RXCOL_TICKS_CLRTCKS 0x00000014 1219#define DEFAULT_RXCOL_TICKS 0x00000048 1220#define HIGH_RXCOL_TICKS 0x00000096 1221#define MAX_RXCOL_TICKS 0x000003ff 1222#define HOSTCC_TXCOL_TICKS 0x00003c0c 1223#define LOW_TXCOL_TICKS 0x00000096 1224#define LOW_TXCOL_TICKS_CLRTCKS 0x00000048 1225#define DEFAULT_TXCOL_TICKS 0x0000012c 1226#define HIGH_TXCOL_TICKS 0x00000145 1227#define MAX_TXCOL_TICKS 0x000003ff 1228#define HOSTCC_RXMAX_FRAMES 0x00003c10 1229#define LOW_RXMAX_FRAMES 0x00000005 1230#define DEFAULT_RXMAX_FRAMES 0x00000008 1231#define HIGH_RXMAX_FRAMES 0x00000012 1232#define MAX_RXMAX_FRAMES 0x000000ff 1233#define HOSTCC_TXMAX_FRAMES 0x00003c14 1234#define LOW_TXMAX_FRAMES 0x00000035 1235#define DEFAULT_TXMAX_FRAMES 0x0000004b 1236#define HIGH_TXMAX_FRAMES 0x00000052 1237#define MAX_TXMAX_FRAMES 0x000000ff 1238#define HOSTCC_RXCOAL_TICK_INT 0x00003c18 1239#define DEFAULT_RXCOAL_TICK_INT 0x00000019 1240#define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014 1241#define MAX_RXCOAL_TICK_INT 0x000003ff 1242#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c 1243#define DEFAULT_TXCOAL_TICK_INT 0x00000019 1244#define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014 1245#define MAX_TXCOAL_TICK_INT 0x000003ff 1246#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 1247#define DEFAULT_RXCOAL_MAXF_INT 0x00000005 1248#define MAX_RXCOAL_MAXF_INT 0x000000ff 1249#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 1250#define DEFAULT_TXCOAL_MAXF_INT 0x00000005 1251#define MAX_TXCOAL_MAXF_INT 0x000000ff 1252#define HOSTCC_STAT_COAL_TICKS 0x00003c28 1253#define DEFAULT_STAT_COAL_TICKS 0x000f4240 1254#define MAX_STAT_COAL_TICKS 0xd693d400 1255#define MIN_STAT_COAL_TICKS 0x00000064 1256/* 0x3c2c --> 0x3c30 unused */ 1257#define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */ 1258#define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ 1259#define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40 1260#define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44 1261#define HOSTCC_FLOW_ATTN 0x00003c48 1262#define HOSTCC_FLOW_ATTN_MBUF_LWM 0x00000040 1263/* 0x3c4c --> 0x3c50 unused */ 1264#define HOSTCC_JUMBO_CON_IDX 0x00003c50 1265#define HOSTCC_STD_CON_IDX 0x00003c54 1266#define HOSTCC_MINI_CON_IDX 0x00003c58 1267/* 0x3c5c --> 0x3c80 unused */ 1268#define HOSTCC_RET_PROD_IDX_0 0x00003c80 1269#define HOSTCC_RET_PROD_IDX_1 0x00003c84 1270#define HOSTCC_RET_PROD_IDX_2 0x00003c88 1271#define HOSTCC_RET_PROD_IDX_3 0x00003c8c 1272#define HOSTCC_RET_PROD_IDX_4 0x00003c90 1273#define HOSTCC_RET_PROD_IDX_5 0x00003c94 1274#define HOSTCC_RET_PROD_IDX_6 0x00003c98 1275#define HOSTCC_RET_PROD_IDX_7 0x00003c9c 1276#define HOSTCC_RET_PROD_IDX_8 0x00003ca0 1277#define HOSTCC_RET_PROD_IDX_9 0x00003ca4 1278#define HOSTCC_RET_PROD_IDX_10 0x00003ca8 1279#define HOSTCC_RET_PROD_IDX_11 0x00003cac 1280#define HOSTCC_RET_PROD_IDX_12 0x00003cb0 1281#define HOSTCC_RET_PROD_IDX_13 0x00003cb4 1282#define HOSTCC_RET_PROD_IDX_14 0x00003cb8 1283#define HOSTCC_RET_PROD_IDX_15 0x00003cbc 1284#define HOSTCC_SND_CON_IDX_0 0x00003cc0 1285#define HOSTCC_SND_CON_IDX_1 0x00003cc4 1286#define HOSTCC_SND_CON_IDX_2 0x00003cc8 1287#define HOSTCC_SND_CON_IDX_3 0x00003ccc 1288#define HOSTCC_SND_CON_IDX_4 0x00003cd0 1289#define HOSTCC_SND_CON_IDX_5 0x00003cd4 1290#define HOSTCC_SND_CON_IDX_6 0x00003cd8 1291#define HOSTCC_SND_CON_IDX_7 0x00003cdc 1292#define HOSTCC_SND_CON_IDX_8 0x00003ce0 1293#define HOSTCC_SND_CON_IDX_9 0x00003ce4 1294#define HOSTCC_SND_CON_IDX_10 0x00003ce8 1295#define HOSTCC_SND_CON_IDX_11 0x00003cec 1296#define HOSTCC_SND_CON_IDX_12 0x00003cf0 1297#define HOSTCC_SND_CON_IDX_13 0x00003cf4 1298#define HOSTCC_SND_CON_IDX_14 0x00003cf8 1299#define HOSTCC_SND_CON_IDX_15 0x00003cfc 1300#define HOSTCC_STATBLCK_RING1 0x00003d00 1301/* 0x3d00 --> 0x3d80 unused */ 1302 1303#define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80 1304#define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84 1305#define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88 1306#define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c 1307#define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90 1308#define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94 1309/* 0x3d98 --> 0x4000 unused */ 1310 1311/* Memory arbiter control registers */ 1312#define MEMARB_MODE 0x00004000 1313#define MEMARB_MODE_RESET 0x00000001 1314#define MEMARB_MODE_ENABLE 0x00000002 1315#define MEMARB_STATUS 0x00004004 1316#define MEMARB_TRAP_ADDR_LOW 0x00004008 1317#define MEMARB_TRAP_ADDR_HIGH 0x0000400c 1318/* 0x4010 --> 0x4400 unused */ 1319 1320/* Buffer manager control registers */ 1321#define BUFMGR_MODE 0x00004400 1322#define BUFMGR_MODE_RESET 0x00000001 1323#define BUFMGR_MODE_ENABLE 0x00000002 1324#define BUFMGR_MODE_ATTN_ENABLE 0x00000004 1325#define BUFMGR_MODE_BM_TEST 0x00000008 1326#define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010 1327#define BUFMGR_MODE_NO_TX_UNDERRUN 0x80000000 1328#define BUFMGR_STATUS 0x00004404 1329#define BUFMGR_STATUS_ERROR 0x00000004 1330#define BUFMGR_STATUS_MBLOW 0x00000010 1331#define BUFMGR_MB_POOL_ADDR 0x00004408 1332#define BUFMGR_MB_POOL_SIZE 0x0000440c 1333#define BUFMGR_MB_RDMA_LOW_WATER 0x00004410 1334#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050 1335#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000 1336#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130 1337#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000 1338#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414 1339#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020 1340#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 1341#define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004 1342#define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a 1343#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098 1344#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b 1345#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e 1346#define BUFMGR_MB_HIGH_WATER 0x00004418 1347#define DEFAULT_MB_HIGH_WATER 0x00000060 1348#define DEFAULT_MB_HIGH_WATER_5705 0x00000060 1349#define DEFAULT_MB_HIGH_WATER_5906 0x00000010 1350#define DEFAULT_MB_HIGH_WATER_57765 0x000000a0 1351#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c 1352#define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096 1353#define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea 1354#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c 1355#define BUFMGR_MB_ALLOC_BIT 0x10000000 1356#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420 1357#define BUFMGR_TX_MB_ALLOC_REQ 0x00004424 1358#define BUFMGR_TX_MB_ALLOC_RESP 0x00004428 1359#define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c 1360#define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430 1361#define BUFMGR_DMA_LOW_WATER 0x00004434 1362#define DEFAULT_DMA_LOW_WATER 0x00000005 1363#define BUFMGR_DMA_HIGH_WATER 0x00004438 1364#define DEFAULT_DMA_HIGH_WATER 0x0000000a 1365#define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c 1366#define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440 1367#define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444 1368#define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448 1369#define BUFMGR_HWDIAG_0 0x0000444c 1370#define BUFMGR_HWDIAG_1 0x00004450 1371#define BUFMGR_HWDIAG_2 0x00004454 1372/* 0x4458 --> 0x4800 unused */ 1373 1374/* Read DMA control registers */ 1375#define RDMAC_MODE 0x00004800 1376#define RDMAC_MODE_RESET 0x00000001 1377#define RDMAC_MODE_ENABLE 0x00000002 1378#define RDMAC_MODE_TGTABORT_ENAB 0x00000004 1379#define RDMAC_MODE_MSTABORT_ENAB 0x00000008 1380#define RDMAC_MODE_PARITYERR_ENAB 0x00000010 1381#define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1382#define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1383#define RDMAC_MODE_FIFOURUN_ENAB 0x00000080 1384#define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1385#define RDMAC_MODE_LNGREAD_ENAB 0x00000200 1386#define RDMAC_MODE_SPLIT_ENABLE 0x00000800 1387#define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800 1388#define RDMAC_MODE_SPLIT_RESET 0x00001000 1389#define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000 1390#define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000 1391#define RDMAC_MODE_FIFO_SIZE_128 0x00020000 1392#define RDMAC_MODE_FIFO_LONG_BURST 0x00030000 1393#define RDMAC_MODE_JMB_2K_MMRR 0x00800000 1394#define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000 1395#define RDMAC_MODE_IPV4_LSO_EN 0x08000000 1396#define RDMAC_MODE_IPV6_LSO_EN 0x10000000 1397#define RDMAC_MODE_H2BNC_VLAN_DET 0x20000000 1398#define RDMAC_STATUS 0x00004804 1399#define RDMAC_STATUS_TGTABORT 0x00000004 1400#define RDMAC_STATUS_MSTABORT 0x00000008 1401#define RDMAC_STATUS_PARITYERR 0x00000010 1402#define RDMAC_STATUS_ADDROFLOW 0x00000020 1403#define RDMAC_STATUS_FIFOOFLOW 0x00000040 1404#define RDMAC_STATUS_FIFOURUN 0x00000080 1405#define RDMAC_STATUS_FIFOOREAD 0x00000100 1406#define RDMAC_STATUS_LNGREAD 0x00000200 1407/* 0x4808 --> 0x4890 unused */ 1408 1409#define TG3_RDMA_RSRVCTRL_REG2 0x00004890 1410#define TG3_LSO_RD_DMA_CRPTEN_CTRL2 0x000048a0 1411 1412#define TG3_RDMA_RSRVCTRL_REG 0x00004900 1413#define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1414#define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00 1415#define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0 1416#define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000 1417#define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000 1418#define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1419#define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000 1420/* 0x4904 --> 0x4910 unused */ 1421 1422#define TG3_LSO_RD_DMA_CRPTEN_CTRL 0x00004910 1423#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1424#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K 0x000c0000 1425#define TG3_LSO_RD_DMA_TX_LENGTH_WA 0x02000000 1426/* 0x4914 --> 0x4be0 unused */ 1427 1428#define TG3_NUM_RDMA_CHANNELS 4 1429#define TG3_RDMA_LENGTH 0x00004be0 1430 1431/* Write DMA control registers */ 1432#define WDMAC_MODE 0x00004c00 1433#define WDMAC_MODE_RESET 0x00000001 1434#define WDMAC_MODE_ENABLE 0x00000002 1435#define WDMAC_MODE_TGTABORT_ENAB 0x00000004 1436#define WDMAC_MODE_MSTABORT_ENAB 0x00000008 1437#define WDMAC_MODE_PARITYERR_ENAB 0x00000010 1438#define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1439#define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1440#define WDMAC_MODE_FIFOURUN_ENAB 0x00000080 1441#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1442#define WDMAC_MODE_LNGREAD_ENAB 0x00000200 1443#define WDMAC_MODE_RX_ACCEL 0x00000400 1444#define WDMAC_MODE_STATUS_TAG_FIX 0x20000000 1445#define WDMAC_MODE_BURST_ALL_DATA 0xc0000000 1446#define WDMAC_STATUS 0x00004c04 1447#define WDMAC_STATUS_TGTABORT 0x00000004 1448#define WDMAC_STATUS_MSTABORT 0x00000008 1449#define WDMAC_STATUS_PARITYERR 0x00000010 1450#define WDMAC_STATUS_ADDROFLOW 0x00000020 1451#define WDMAC_STATUS_FIFOOFLOW 0x00000040 1452#define WDMAC_STATUS_FIFOURUN 0x00000080 1453#define WDMAC_STATUS_FIFOOREAD 0x00000100 1454#define WDMAC_STATUS_LNGREAD 0x00000200 1455/* 0x4c08 --> 0x5000 unused */ 1456 1457/* Per-cpu register offsets (arm9) */ 1458#define CPU_MODE 0x00000000 1459#define CPU_MODE_RESET 0x00000001 1460#define CPU_MODE_HALT 0x00000400 1461#define CPU_STATE 0x00000004 1462#define CPU_EVTMASK 0x00000008 1463/* 0xc --> 0x1c reserved */ 1464#define CPU_PC 0x0000001c 1465#define CPU_INSN 0x00000020 1466#define CPU_SPAD_UFLOW 0x00000024 1467#define CPU_WDOG_CLEAR 0x00000028 1468#define CPU_WDOG_VECTOR 0x0000002c 1469#define CPU_WDOG_PC 0x00000030 1470#define CPU_HW_BP 0x00000034 1471/* 0x38 --> 0x44 unused */ 1472#define CPU_WDOG_SAVED_STATE 0x00000044 1473#define CPU_LAST_BRANCH_ADDR 0x00000048 1474#define CPU_SPAD_UFLOW_SET 0x0000004c 1475/* 0x50 --> 0x200 unused */ 1476#define CPU_R0 0x00000200 1477#define CPU_R1 0x00000204 1478#define CPU_R2 0x00000208 1479#define CPU_R3 0x0000020c 1480#define CPU_R4 0x00000210 1481#define CPU_R5 0x00000214 1482#define CPU_R6 0x00000218 1483#define CPU_R7 0x0000021c 1484#define CPU_R8 0x00000220 1485#define CPU_R9 0x00000224 1486#define CPU_R10 0x00000228 1487#define CPU_R11 0x0000022c 1488#define CPU_R12 0x00000230 1489#define CPU_R13 0x00000234 1490#define CPU_R14 0x00000238 1491#define CPU_R15 0x0000023c 1492#define CPU_R16 0x00000240 1493#define CPU_R17 0x00000244 1494#define CPU_R18 0x00000248 1495#define CPU_R19 0x0000024c 1496#define CPU_R20 0x00000250 1497#define CPU_R21 0x00000254 1498#define CPU_R22 0x00000258 1499#define CPU_R23 0x0000025c 1500#define CPU_R24 0x00000260 1501#define CPU_R25 0x00000264 1502#define CPU_R26 0x00000268 1503#define CPU_R27 0x0000026c 1504#define CPU_R28 0x00000270 1505#define CPU_R29 0x00000274 1506#define CPU_R30 0x00000278 1507#define CPU_R31 0x0000027c 1508/* 0x280 --> 0x400 unused */ 1509 1510#define RX_CPU_BASE 0x00005000 1511#define RX_CPU_MODE 0x00005000 1512#define RX_CPU_STATE 0x00005004 1513#define RX_CPU_PGMCTR 0x0000501c 1514#define RX_CPU_HWBKPT 0x00005034 1515#define TX_CPU_BASE 0x00005400 1516#define TX_CPU_MODE 0x00005400 1517#define TX_CPU_STATE 0x00005404 1518#define TX_CPU_PGMCTR 0x0000541c 1519 1520#define VCPU_STATUS 0x00005100 1521#define VCPU_STATUS_INIT_DONE 0x04000000 1522#define VCPU_STATUS_DRV_RESET 0x08000000 1523 1524#define VCPU_CFGSHDW 0x00005104 1525#define VCPU_CFGSHDW_WOL_ENABLE 0x00000001 1526#define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004 1527#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000 1528 1529/* Mailboxes */ 1530#define GRCMBOX_BASE 0x00005600 1531#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ 1532#define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */ 1533#define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */ 1534#define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */ 1535#define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */ 1536#define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */ 1537#define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */ 1538#define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */ 1539#define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */ 1540#define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */ 1541#define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */ 1542#define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */ 1543#define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */ 1544#define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */ 1545#define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */ 1546#define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */ 1547#define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */ 1548#define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */ 1549#define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */ 1550#define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */ 1551#define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */ 1552#define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */ 1553#define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */ 1554#define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */ 1555#define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */ 1556#define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */ 1557#define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */ 1558#define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */ 1559#define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */ 1560#define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */ 1561#define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */ 1562#define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */ 1563#define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */ 1564#define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */ 1565#define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */ 1566#define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */ 1567#define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */ 1568#define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */ 1569#define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */ 1570#define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */ 1571#define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */ 1572#define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */ 1573#define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */ 1574#define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */ 1575#define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */ 1576#define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */ 1577#define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */ 1578#define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */ 1579#define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */ 1580#define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */ 1581#define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */ 1582#define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */ 1583#define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */ 1584#define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */ 1585#define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */ 1586#define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */ 1587#define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */ 1588#define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */ 1589#define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */ 1590#define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */ 1591#define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */ 1592#define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */ 1593#define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */ 1594#define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */ 1595#define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00 1596#define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04 1597#define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08 1598#define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c 1599/* 0x5a10 --> 0x5c00 */ 1600 1601/* Flow Through queues */ 1602#define FTQ_RESET 0x00005c00 1603/* 0x5c04 --> 0x5c10 unused */ 1604#define FTQ_DMA_NORM_READ_CTL 0x00005c10 1605#define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14 1606#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18 1607#define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c 1608#define FTQ_DMA_HIGH_READ_CTL 0x00005c20 1609#define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24 1610#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28 1611#define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c 1612#define FTQ_DMA_COMP_DISC_CTL 0x00005c30 1613#define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34 1614#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38 1615#define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c 1616#define FTQ_SEND_BD_COMP_CTL 0x00005c40 1617#define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44 1618#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48 1619#define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c 1620#define FTQ_SEND_DATA_INIT_CTL 0x00005c50 1621#define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54 1622#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58 1623#define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c 1624#define FTQ_DMA_NORM_WRITE_CTL 0x00005c60 1625#define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64 1626#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68 1627#define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c 1628#define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70 1629#define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74 1630#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78 1631#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c 1632#define FTQ_SWTYPE1_CTL 0x00005c80 1633#define FTQ_SWTYPE1_FULL_CNT 0x00005c84 1634#define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88 1635#define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c 1636#define FTQ_SEND_DATA_COMP_CTL 0x00005c90 1637#define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94 1638#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98 1639#define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c 1640#define FTQ_HOST_COAL_CTL 0x00005ca0 1641#define FTQ_HOST_COAL_FULL_CNT 0x00005ca4 1642#define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8 1643#define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac 1644#define FTQ_MAC_TX_CTL 0x00005cb0 1645#define FTQ_MAC_TX_FULL_CNT 0x00005cb4 1646#define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8 1647#define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc 1648#define FTQ_MB_FREE_CTL 0x00005cc0 1649#define FTQ_MB_FREE_FULL_CNT 0x00005cc4 1650#define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8 1651#define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc 1652#define FTQ_RCVBD_COMP_CTL 0x00005cd0 1653#define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4 1654#define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8 1655#define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc 1656#define FTQ_RCVLST_PLMT_CTL 0x00005ce0 1657#define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4 1658#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8 1659#define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec 1660#define FTQ_RCVDATA_INI_CTL 0x00005cf0 1661#define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4 1662#define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8 1663#define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc 1664#define FTQ_RCVDATA_COMP_CTL 0x00005d00 1665#define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04 1666#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08 1667#define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c 1668#define FTQ_SWTYPE2_CTL 0x00005d10 1669#define FTQ_SWTYPE2_FULL_CNT 0x00005d14 1670#define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18 1671#define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c 1672/* 0x5d20 --> 0x6000 unused */ 1673 1674/* Message signaled interrupt registers */ 1675#define MSGINT_MODE 0x00006000 1676#define MSGINT_MODE_RESET 0x00000001 1677#define MSGINT_MODE_ENABLE 0x00000002 1678#define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020 1679#define MSGINT_MODE_MULTIVEC_EN 0x00000080 1680#define MSGINT_STATUS 0x00006004 1681#define MSGINT_STATUS_MSI_REQ 0x00000001 1682#define MSGINT_FIFO 0x00006008 1683/* 0x600c --> 0x6400 unused */ 1684 1685/* DMA completion registers */ 1686#define DMAC_MODE 0x00006400 1687#define DMAC_MODE_RESET 0x00000001 1688#define DMAC_MODE_ENABLE 0x00000002 1689/* 0x6404 --> 0x6800 unused */ 1690 1691/* GRC registers */ 1692#define GRC_MODE 0x00006800 1693#define GRC_MODE_UPD_ON_COAL 0x00000001 1694#define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002 1695#define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004 1696#define GRC_MODE_BSWAP_DATA 0x00000010 1697#define GRC_MODE_WSWAP_DATA 0x00000020 1698#define GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040 1699#define GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080 1700#define GRC_MODE_SPLITHDR 0x00000100 1701#define GRC_MODE_NOFRM_CRACKING 0x00000200 1702#define GRC_MODE_INCL_CRC 0x00000400 1703#define GRC_MODE_ALLOW_BAD_FRMS 0x00000800 1704#define GRC_MODE_NOIRQ_ON_SENDS 0x00002000 1705#define GRC_MODE_NOIRQ_ON_RCV 0x00004000 1706#define GRC_MODE_FORCE_PCI32BIT 0x00008000 1707#define GRC_MODE_B2HRX_ENABLE 0x00008000 1708#define GRC_MODE_HOST_STACKUP 0x00010000 1709#define GRC_MODE_HOST_SENDBDS 0x00020000 1710#define GRC_MODE_HTX2B_ENABLE 0x00040000 1711#define GRC_MODE_TIME_SYNC_ENABLE 0x00080000 1712#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000 1713#define GRC_MODE_NVRAM_WR_ENABLE 0x00200000 1714#define GRC_MODE_PCIE_TL_SEL 0x00000000 1715#define GRC_MODE_PCIE_PL_SEL 0x00400000 1716#define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000 1717#define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000 1718#define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000 1719#define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000 1720#define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000 1721#define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000 1722#define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000 1723#define GRC_MODE_PCIE_DL_SEL 0x20000000 1724#define GRC_MODE_MCAST_FRM_ENABLE 0x40000000 1725#define GRC_MODE_PCIE_HI_1K_EN 0x80000000 1726#define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \ 1727 GRC_MODE_PCIE_PL_SEL | \ 1728 GRC_MODE_PCIE_DL_SEL | \ 1729 GRC_MODE_PCIE_HI_1K_EN) 1730#define GRC_MISC_CFG 0x00006804 1731#define GRC_MISC_CFG_CORECLK_RESET 0x00000001 1732#define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe 1733#define GRC_MISC_CFG_PRESCALAR_SHIFT 1 1734#define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000 1735#define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000 1736#define GRC_MISC_CFG_BOARD_ID_5701 0x00000000 1737#define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000 1738#define GRC_MISC_CFG_BOARD_ID_5703 0x00000000 1739#define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000 1740#define GRC_MISC_CFG_BOARD_ID_5704 0x00000000 1741#define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000 1742#define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000 1743#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000 1744#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000 1745#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 1746#define GRC_MISC_CFG_EPHY_IDDQ 0x00200000 1747#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 1748#define GRC_LOCAL_CTRL 0x00006808 1749#define GRC_LCLCTRL_INT_ACTIVE 0x00000001 1750#define GRC_LCLCTRL_CLEARINT 0x00000002 1751#define GRC_LCLCTRL_SETINT 0x00000004 1752#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008 1753#define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */ 1754#define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */ 1755#define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */ 1756#define GRC_LCLCTRL_GPIO_INPUT3 0x00000020 1757#define GRC_LCLCTRL_GPIO_OE3 0x00000040 1758#define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080 1759#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100 1760#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200 1761#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400 1762#define GRC_LCLCTRL_GPIO_OE0 0x00000800 1763#define GRC_LCLCTRL_GPIO_OE1 0x00001000 1764#define GRC_LCLCTRL_GPIO_OE2 0x00002000 1765#define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000 1766#define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000 1767#define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000 1768#define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000 1769#define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000 1770#define GRC_LCLCTRL_MEMSZ_256K 0x00000000 1771#define GRC_LCLCTRL_MEMSZ_512K 0x00040000 1772#define GRC_LCLCTRL_MEMSZ_1M 0x00080000 1773#define GRC_LCLCTRL_MEMSZ_2M 0x000c0000 1774#define GRC_LCLCTRL_MEMSZ_4M 0x00100000 1775#define GRC_LCLCTRL_MEMSZ_8M 0x00140000 1776#define GRC_LCLCTRL_MEMSZ_16M 0x00180000 1777#define GRC_LCLCTRL_BANK_SELECT 0x00200000 1778#define GRC_LCLCTRL_SSRAM_TYPE 0x00400000 1779#define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000 1780#define GRC_TIMER 0x0000680c 1781#define GRC_RX_CPU_EVENT 0x00006810 1782#define GRC_RX_CPU_DRIVER_EVENT 0x00004000 1783#define GRC_RX_TIMER_REF 0x00006814 1784#define GRC_RX_CPU_SEM 0x00006818 1785#define GRC_REMOTE_RX_CPU_ATTN 0x0000681c 1786#define GRC_TX_CPU_EVENT 0x00006820 1787#define GRC_TX_TIMER_REF 0x00006824 1788#define GRC_TX_CPU_SEM 0x00006828 1789#define GRC_REMOTE_TX_CPU_ATTN 0x0000682c 1790#define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */ 1791#define GRC_EEPROM_ADDR 0x00006838 1792#define EEPROM_ADDR_WRITE 0x00000000 1793#define EEPROM_ADDR_READ 0x80000000 1794#define EEPROM_ADDR_COMPLETE 0x40000000 1795#define EEPROM_ADDR_FSM_RESET 0x20000000 1796#define EEPROM_ADDR_DEVID_MASK 0x1c000000 1797#define EEPROM_ADDR_DEVID_SHIFT 26 1798#define EEPROM_ADDR_START 0x02000000 1799#define EEPROM_ADDR_CLKPERD_SHIFT 16 1800#define EEPROM_ADDR_ADDR_MASK 0x0000ffff 1801#define EEPROM_ADDR_ADDR_SHIFT 0 1802#define EEPROM_DEFAULT_CLOCK_PERIOD 0x60 1803#define EEPROM_CHIP_SIZE (64 * 1024) 1804#define GRC_EEPROM_DATA 0x0000683c 1805#define GRC_EEPROM_CTRL 0x00006840 1806#define GRC_MDI_CTRL 0x00006844 1807#define GRC_SEEPROM_DELAY 0x00006848 1808/* 0x684c --> 0x6890 unused */ 1809#define GRC_VCPU_EXT_CTRL 0x00006890 1810#define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1811#define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1812#define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */ 1813 1814#define TG3_EAV_REF_CLCK_LSB 0x00006900 1815#define TG3_EAV_REF_CLCK_MSB 0x00006904 1816#define TG3_EAV_REF_CLCK_CTL 0x00006908 1817#define TG3_EAV_REF_CLCK_CTL_STOP 0x00000002 1818#define TG3_EAV_REF_CLCK_CTL_RESUME 0x00000004 1819#define TG3_EAV_REF_CLK_CORRECT_CTL 0x00006928 1820#define TG3_EAV_REF_CLK_CORRECT_EN (1 << 31) 1821#define TG3_EAV_REF_CLK_CORRECT_NEG (1 << 30) 1822 1823#define TG3_EAV_REF_CLK_CORRECT_MASK 0xffffff 1824/* 0x690c --> 0x7000 unused */ 1825 1826/* NVRAM Control registers */ 1827#define NVRAM_CMD 0x00007000 1828#define NVRAM_CMD_RESET 0x00000001 1829#define NVRAM_CMD_DONE 0x00000008 1830#define NVRAM_CMD_GO 0x00000010 1831#define NVRAM_CMD_WR 0x00000020 1832#define NVRAM_CMD_RD 0x00000000 1833#define NVRAM_CMD_ERASE 0x00000040 1834#define NVRAM_CMD_FIRST 0x00000080 1835#define NVRAM_CMD_LAST 0x00000100 1836#define NVRAM_CMD_WREN 0x00010000 1837#define NVRAM_CMD_WRDI 0x00020000 1838#define NVRAM_STAT 0x00007004 1839#define NVRAM_WRDATA 0x00007008 1840#define NVRAM_ADDR 0x0000700c 1841#define NVRAM_ADDR_MSK 0x00ffffff 1842#define NVRAM_RDDATA 0x00007010 1843#define NVRAM_CFG1 0x00007014 1844#define NVRAM_CFG1_FLASHIF_ENAB 0x00000001 1845#define NVRAM_CFG1_BUFFERED_MODE 0x00000002 1846#define NVRAM_CFG1_PASS_THRU 0x00000004 1847#define NVRAM_CFG1_STATUS_BITS 0x00000070 1848#define NVRAM_CFG1_BIT_BANG 0x00000008 1849#define NVRAM_CFG1_FLASH_SIZE 0x02000000 1850#define NVRAM_CFG1_COMPAT_BYPASS 0x80000000 1851#define NVRAM_CFG1_VENDOR_MASK 0x03000003 1852#define FLASH_VENDOR_ATMEL_EEPROM 0x02000000 1853#define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 1854#define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003 1855#define FLASH_VENDOR_ST 0x03000001 1856#define FLASH_VENDOR_SAIFUN 0x01000003 1857#define FLASH_VENDOR_SST_SMALL 0x00000001 1858#define FLASH_VENDOR_SST_LARGE 0x02000001 1859#define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003 1860#define NVRAM_CFG1_5762VENDOR_MASK 0x03e00003 1861#define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000 1862#define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000 1863#define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 1864#define FLASH_5752VENDOR_ST_M45PE10 0x02400000 1865#define FLASH_5752VENDOR_ST_M45PE20 0x02400002 1866#define FLASH_5752VENDOR_ST_M45PE40 0x02400001 1867#define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001 1868#define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002 1869#define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000 1870#define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003 1871#define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003 1872#define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003 1873#define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002 1874#define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003 1875#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002 1876#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000 1877#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000 1878#define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003 1879#define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000 1880#define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002 1881#define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001 1882#define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003 1883#define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000 1884#define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002 1885#define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001 1886#define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001 1887#define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000 1888#define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002 1889#define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003 1890#define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001 1891#define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000 1892#define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002 1893#define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003 1894#define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000 1895#define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000 1896#define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002 1897#define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002 1898#define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001 1899#define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001 1900#define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001 1901#define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003 1902#define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001 1903#define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003 1904#define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000 1905#define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002 1906#define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001 1907#define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003 1908#define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000 1909#define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002 1910#define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001 1911#define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003 1912#define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000 1913#define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002 1914#define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001 1915#define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003 1916#define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000 1917#define FLASH_5717VENDOR_ST_25USPT 0x03400002 1918#define FLASH_5717VENDOR_ST_45USPT 0x03400001 1919#define FLASH_5720_EEPROM_HD 0x00000001 1920#define FLASH_5720_EEPROM_LD 0x00000003 1921#define FLASH_5762_EEPROM_HD 0x02000001 1922#define FLASH_5762_EEPROM_LD 0x02000003 1923#define FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000 1924#define FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002 1925#define FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001 1926#define FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003 1927#define FLASH_5720VENDOR_M_ST_M25PE10 0x02000000 1928#define FLASH_5720VENDOR_M_ST_M25PE20 0x02000002 1929#define FLASH_5720VENDOR_M_ST_M25PE40 0x02000001 1930#define FLASH_5720VENDOR_M_ST_M25PE80 0x02000003 1931#define FLASH_5720VENDOR_M_ST_M45PE10 0x03000000 1932#define FLASH_5720VENDOR_M_ST_M45PE20 0x03000002 1933#define FLASH_5720VENDOR_M_ST_M45PE40 0x03000001 1934#define FLASH_5720VENDOR_M_ST_M45PE80 0x03000003 1935#define FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000 1936#define FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002 1937#define FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001 1938#define FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000 1939#define FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002 1940#define FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001 1941#define FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003 1942#define FLASH_5720VENDOR_A_ST_M25PE10 0x02800000 1943#define FLASH_5720VENDOR_A_ST_M25PE20 0x02800002 1944#define FLASH_5720VENDOR_A_ST_M25PE40 0x02800001 1945#define FLASH_5720VENDOR_A_ST_M25PE80 0x02800003 1946#define FLASH_5720VENDOR_A_ST_M45PE10 0x02c00000 1947#define FLASH_5720VENDOR_A_ST_M45PE20 0x02c00002 1948#define FLASH_5720VENDOR_A_ST_M45PE40 0x02c00001 1949#define FLASH_5720VENDOR_A_ST_M45PE80 0x02c00003 1950#define FLASH_5720VENDOR_ATMEL_45USPT 0x03c00000 1951#define FLASH_5720VENDOR_ST_25USPT 0x03c00002 1952#define FLASH_5720VENDOR_ST_45USPT 0x03c00001 1953#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 1954#define FLASH_5752PAGE_SIZE_256 0x00000000 1955#define FLASH_5752PAGE_SIZE_512 0x10000000 1956#define FLASH_5752PAGE_SIZE_1K 0x20000000 1957#define FLASH_5752PAGE_SIZE_2K 0x30000000 1958#define FLASH_5752PAGE_SIZE_4K 0x40000000 1959#define FLASH_5752PAGE_SIZE_264 0x50000000 1960#define FLASH_5752PAGE_SIZE_528 0x60000000 1961#define NVRAM_CFG2 0x00007018 1962#define NVRAM_CFG3 0x0000701c 1963#define NVRAM_SWARB 0x00007020 1964#define SWARB_REQ_SET0 0x00000001 1965#define SWARB_REQ_SET1 0x00000002 1966#define SWARB_REQ_SET2 0x00000004 1967#define SWARB_REQ_SET3 0x00000008 1968#define SWARB_REQ_CLR0 0x00000010 1969#define SWARB_REQ_CLR1 0x00000020 1970#define SWARB_REQ_CLR2 0x00000040 1971#define SWARB_REQ_CLR3 0x00000080 1972#define SWARB_GNT0 0x00000100 1973#define SWARB_GNT1 0x00000200 1974#define SWARB_GNT2 0x00000400 1975#define SWARB_GNT3 0x00000800 1976#define SWARB_REQ0 0x00001000 1977#define SWARB_REQ1 0x00002000 1978#define SWARB_REQ2 0x00004000 1979#define SWARB_REQ3 0x00008000 1980#define NVRAM_ACCESS 0x00007024 1981#define ACCESS_ENABLE 0x00000001 1982#define ACCESS_WR_ENABLE 0x00000002 1983#define NVRAM_WRITE1 0x00007028 1984/* 0x702c unused */ 1985 1986#define NVRAM_ADDR_LOCKOUT 0x00007030 1987/* 0x7034 --> 0x7500 unused */ 1988 1989#define OTP_MODE 0x00007500 1990#define OTP_MODE_OTP_THRU_GRC 0x00000001 1991#define OTP_CTRL 0x00007504 1992#define OTP_CTRL_OTP_PROG_ENABLE 0x00200000 1993#define OTP_CTRL_OTP_CMD_READ 0x00000000 1994#define OTP_CTRL_OTP_CMD_INIT 0x00000008 1995#define OTP_CTRL_OTP_CMD_START 0x00000001 1996#define OTP_STATUS 0x00007508 1997#define OTP_STATUS_CMD_DONE 0x00000001 1998#define OTP_ADDRESS 0x0000750c 1999#define OTP_ADDRESS_MAGIC1 0x000000a0 2000#define OTP_ADDRESS_MAGIC2 0x00000080 2001/* 0x7510 unused */ 2002 2003#define OTP_READ_DATA 0x00007514 2004/* 0x7518 --> 0x7c04 unused */ 2005 2006#define PCIE_TRANSACTION_CFG 0x00007c04 2007#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 2008#define PCIE_TRANS_CFG_LOM 0x00000020 2009/* 0x7c08 --> 0x7d28 unused */ 2010 2011#define PCIE_PWR_MGMT_THRESH 0x00007d28 2012#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 2013#define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 2014#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 2015/* 0x7d2c --> 0x7d54 unused */ 2016 2017#define TG3_PCIE_LNKCTL 0x00007d54 2018#define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008 2019#define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080 2020/* 0x7d58 --> 0x7e70 unused */ 2021 2022#define TG3_PCIE_PHY_TSTCTL 0x00007e2c 2023#define TG3_PCIE_PHY_TSTCTL_PCIE10 0x00000040 2024#define TG3_PCIE_PHY_TSTCTL_PSCRAM 0x00000020 2025 2026#define TG3_PCIE_EIDLE_DELAY 0x00007e70 2027#define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f 2028#define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c 2029/* 0x7e74 --> 0x8000 unused */ 2030 2031 2032/* Alternate PCIE definitions */ 2033#define TG3_PCIE_TLDLPL_PORT 0x00007c00 2034#define TG3_PCIE_DL_LO_FTSMAX 0x0000000c 2035#define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff 2036#define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c 2037#define TG3_PCIE_PL_LO_PHYCTL1 0x00000004 2038#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000 2039#define TG3_PCIE_PL_LO_PHYCTL5 0x00000014 2040#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000 2041 2042#define TG3_REG_BLK_SIZE 0x00008000 2043 2044/* OTP bit definitions */ 2045#define TG3_OTP_AGCTGT_MASK 0x000000e0 2046#define TG3_OTP_AGCTGT_SHIFT 1 2047#define TG3_OTP_HPFFLTR_MASK 0x00000300 2048#define TG3_OTP_HPFFLTR_SHIFT 1 2049#define TG3_OTP_HPFOVER_MASK 0x00000400 2050#define TG3_OTP_HPFOVER_SHIFT 1 2051#define TG3_OTP_LPFDIS_MASK 0x00000800 2052#define TG3_OTP_LPFDIS_SHIFT 11 2053#define TG3_OTP_VDAC_MASK 0xff000000 2054#define TG3_OTP_VDAC_SHIFT 24 2055#define TG3_OTP_10BTAMP_MASK 0x0000f000 2056#define TG3_OTP_10BTAMP_SHIFT 8 2057#define TG3_OTP_ROFF_MASK 0x00e00000 2058#define TG3_OTP_ROFF_SHIFT 11 2059#define TG3_OTP_RCOFF_MASK 0x001c0000 2060#define TG3_OTP_RCOFF_SHIFT 16 2061 2062#define TG3_OTP_DEFAULT 0x286c1640 2063 2064 2065/* Hardware Legacy NVRAM layout */ 2066#define TG3_NVM_VPD_OFF 0x100 2067#define TG3_NVM_VPD_LEN 256 2068 2069/* Hardware Selfboot NVRAM layout */ 2070#define TG3_NVM_HWSB_CFG1 0x00000004 2071#define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000 2072#define TG3_NVM_HWSB_CFG1_MAJSFT 27 2073#define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000 2074#define TG3_NVM_HWSB_CFG1_MINSFT 22 2075 2076#define TG3_EEPROM_MAGIC 0x669955aa 2077#define TG3_EEPROM_MAGIC_FW 0xa5000000 2078#define TG3_EEPROM_MAGIC_FW_MSK 0xff000000 2079#define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000 2080#define TG3_EEPROM_SB_FORMAT_1 0x00200000 2081#define TG3_EEPROM_SB_REVISION_MASK 0x001f0000 2082#define TG3_EEPROM_SB_REVISION_0 0x00000000 2083#define TG3_EEPROM_SB_REVISION_2 0x00020000 2084#define TG3_EEPROM_SB_REVISION_3 0x00030000 2085#define TG3_EEPROM_SB_REVISION_4 0x00040000 2086#define TG3_EEPROM_SB_REVISION_5 0x00050000 2087#define TG3_EEPROM_SB_REVISION_6 0x00060000 2088#define TG3_EEPROM_MAGIC_HW 0xabcd 2089#define TG3_EEPROM_MAGIC_HW_MSK 0xffff 2090 2091#define TG3_NVM_DIR_START 0x18 2092#define TG3_NVM_DIR_END 0x78 2093#define TG3_NVM_DIRENT_SIZE 0xc 2094#define TG3_NVM_DIRTYPE_SHIFT 24 2095#define TG3_NVM_DIRTYPE_LENMSK 0x003fffff 2096#define TG3_NVM_DIRTYPE_ASFINI 1 2097#define TG3_NVM_DIRTYPE_EXTVPD 20 2098#define TG3_NVM_PTREV_BCVER 0x94 2099#define TG3_NVM_BCVER_MAJMSK 0x0000ff00 2100#define TG3_NVM_BCVER_MAJSFT 8 2101#define TG3_NVM_BCVER_MINMSK 0x000000ff 2102 2103#define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10 2104#define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14 2105#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 2106#define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18 2107#define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c 2108#define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20 2109#define TG3_EEPROM_SB_F1R6_EDH_OFF 0x4c 2110#define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700 2111#define TG3_EEPROM_SB_EDH_MAJ_SHFT 8 2112#define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff 2113#define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800 2114#define TG3_EEPROM_SB_EDH_BLD_SHFT 11 2115 2116 2117/* 32K Window into NIC internal memory */ 2118#define NIC_SRAM_WIN_BASE 0x00008000 2119 2120/* Offsets into first 32k of NIC internal memory. */ 2121#define NIC_SRAM_PAGE_ZERO 0x00000000 2122#define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */ 2123#define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */ 2124#define NIC_SRAM_STATS_BLK 0x00000300 2125#define NIC_SRAM_STATUS_BLK 0x00000b00 2126 2127#define NIC_SRAM_FIRMWARE_MBOX 0x00000b50 2128#define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654 2129#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */ 2130 2131#define NIC_SRAM_DATA_SIG 0x00000b54 2132#define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */ 2133 2134#define NIC_SRAM_DATA_CFG 0x00000b58 2135#define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c 2136#define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000 2137#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004 2138#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008 2139#define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030 2140#define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000 2141#define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010 2142#define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020 2143#define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040 2144#define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080 2145#define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100 2146#define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000 2147#define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000 2148#define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000 2149#define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000 2150 2151#define NIC_SRAM_DATA_VER 0x00000b5c 2152#define NIC_SRAM_DATA_VER_SHIFT 16 2153 2154#define NIC_SRAM_DATA_PHY_ID 0x00000b74 2155#define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000 2156#define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff 2157 2158#define NIC_SRAM_FW_CMD_MBOX 0x00000b78 2159#define FWCMD_NICDRV_ALIVE 0x00000001 2160#define FWCMD_NICDRV_PAUSE_FW 0x00000002 2161#define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003 2162#define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004 2163#define FWCMD_NICDRV_FIX_DMAR 0x00000005 2164#define FWCMD_NICDRV_FIX_DMAW 0x00000006 2165#define FWCMD_NICDRV_LINK_UPDATE 0x0000000c 2166#define FWCMD_NICDRV_ALIVE2 0x0000000d 2167#define FWCMD_NICDRV_ALIVE3 0x0000000e 2168#define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c 2169#define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80 2170#define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00 2171#define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04 2172#define DRV_STATE_START 0x00000001 2173#define DRV_STATE_START_DONE 0x80000001 2174#define DRV_STATE_UNLOAD 0x00000002 2175#define DRV_STATE_UNLOAD_DONE 0x80000002 2176#define DRV_STATE_WOL 0x00000003 2177#define DRV_STATE_SUSPEND 0x00000004 2178 2179#define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08 2180 2181#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14 2182#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18 2183 2184#define NIC_SRAM_WOL_MBOX 0x00000d30 2185#define WOL_SIGNATURE 0x474c0000 2186#define WOL_DRV_STATE_SHUTDOWN 0x00000001 2187#define WOL_DRV_WOL 0x00000002 2188#define WOL_SET_MAGIC_PKT 0x00000004 2189 2190#define NIC_SRAM_DATA_CFG_2 0x00000d38 2191 2192#define NIC_SRAM_DATA_CFG_2_APD_EN 0x00000400 2193#define SHASTA_EXT_LED_MODE_MASK 0x00018000 2194#define SHASTA_EXT_LED_LEGACY 0x00000000 2195#define SHASTA_EXT_LED_SHARED 0x00008000 2196#define SHASTA_EXT_LED_MAC 0x00010000 2197#define SHASTA_EXT_LED_COMBO 0x00018000 2198 2199#define NIC_SRAM_DATA_CFG_3 0x00000d3c 2200#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 2201 2202#define NIC_SRAM_DATA_CFG_4 0x00000d60 2203#define NIC_SRAM_GMII_MODE 0x00000002 2204#define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004 2205#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008 2206#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010 2207 2208#define NIC_SRAM_CPMU_STATUS 0x00000e00 2209#define NIC_SRAM_CPMUSTAT_SIG 0x0000362c 2210#define NIC_SRAM_CPMUSTAT_SIG_MSK 0x0000ffff 2211 2212#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 2213 2214#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 2215#define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000 2216#define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */ 2217#define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */ 2218#define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */ 2219#define NIC_SRAM_MBUF_POOL_BASE 0x00008000 2220#define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000 2221#define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000 2222#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 2223#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 2224 2225#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128 2226#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64 2227#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32 2228 2229#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700 64 2230#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717 16 2231 2232 2233/* Currently this is fixed. */ 2234#define TG3_PHY_MII_ADDR 0x01 2235 2236 2237/*** Tigon3 specific PHY MII registers. ***/ 2238#define MII_TG3_MMD_CTRL 0x0d /* MMD Access Control register */ 2239#define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000 2240#define MII_TG3_MMD_ADDRESS 0x0e /* MMD Address Data register */ 2241 2242#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */ 2243#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001 2244#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002 2245#define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008 2246#define MII_TG3_EXT_CTRL_TBI 0x8000 2247 2248#define MII_TG3_EXT_STAT 0x11 /* Extended status register */ 2249#define MII_TG3_EXT_STAT_MDIX 0x2000 2250#define MII_TG3_EXT_STAT_LPASS 0x0100 2251 2252#define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */ 2253#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ 2254#define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */ 2255#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ 2256 2257#define MII_TG3_DSP_TAP1 0x0001 2258#define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007 2259#define MII_TG3_DSP_TAP26 0x001a 2260#define MII_TG3_DSP_TAP26_ALNOKO 0x0001 2261#define MII_TG3_DSP_TAP26_RMRXSTO 0x0002 2262#define MII_TG3_DSP_TAP26_OPCSINPT 0x0004 2263#define MII_TG3_DSP_AADJ1CH0 0x001f 2264#define MII_TG3_DSP_CH34TP2 0x4022 2265#define MII_TG3_DSP_CH34TP2_HIBW01 0x01ff 2266#define MII_TG3_DSP_AADJ1CH3 0x601f 2267#define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002 2268#define MII_TG3_DSP_EXP1_INT_STAT 0x0f01 2269#define MII_TG3_DSP_EXP8 0x0f08 2270#define MII_TG3_DSP_EXP8_REJ2MHz 0x0001 2271#define MII_TG3_DSP_EXP8_AEDW 0x0200 2272#define MII_TG3_DSP_EXP75 0x0f75 2273#define MII_TG3_DSP_EXP96 0x0f96 2274#define MII_TG3_DSP_EXP97 0x0f97 2275 2276#define MII_TG3_AUX_CTRL 0x18 /* auxiliary control register */ 2277 2278#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000 2279#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400 2280#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800 2281#define MII_TG3_AUXCTL_ACTL_EXTPKTLEN 0x4000 2282#define MII_TG3_AUXCTL_ACTL_EXTLOOPBK 0x8000 2283 2284#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002 2285#define MII_TG3_AUXCTL_PCTL_WOL_EN 0x0008 2286#define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010 2287#define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020 2288#define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040 2289#define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180 2290 2291#define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004 2292 2293#define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 2294#define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010 2295#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200 2296#define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12 2297#define MII_TG3_AUXCTL_MISC_WREN 0x8000 2298 2299 2300#define MII_TG3_AUX_STAT 0x19 /* auxiliary status register */ 2301#define MII_TG3_AUX_STAT_LPASS 0x0004 2302#define MII_TG3_AUX_STAT_SPDMASK 0x0700 2303#define MII_TG3_AUX_STAT_10HALF 0x0100 2304#define MII_TG3_AUX_STAT_10FULL 0x0200 2305#define MII_TG3_AUX_STAT_100HALF 0x0300 2306#define MII_TG3_AUX_STAT_100_4 0x0400 2307#define MII_TG3_AUX_STAT_100FULL 0x0500 2308#define MII_TG3_AUX_STAT_1000HALF 0x0600 2309#define MII_TG3_AUX_STAT_1000FULL 0x0700 2310#define MII_TG3_AUX_STAT_100 0x0008 2311#define MII_TG3_AUX_STAT_FULL 0x0001 2312 2313#define MII_TG3_ISTAT 0x1a /* IRQ status register */ 2314#define MII_TG3_IMASK 0x1b /* IRQ mask register */ 2315 2316/* ISTAT/IMASK event bits */ 2317#define MII_TG3_INT_LINKCHG 0x0002 2318#define MII_TG3_INT_SPEEDCHG 0x0004 2319#define MII_TG3_INT_DUPLEXCHG 0x0008 2320#define MII_TG3_INT_ANEG_PAGE_RX 0x0400 2321 2322#define MII_TG3_MISC_SHDW 0x1c 2323#define MII_TG3_MISC_SHDW_WREN 0x8000 2324 2325#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001 2326#define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020 2327#define MII_TG3_MISC_SHDW_APD_SEL 0x2800 2328 2329#define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001 2330#define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002 2331#define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004 2332#define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008 2333#define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010 2334#define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400 2335 2336#define MII_TG3_TEST1 0x1e 2337#define MII_TG3_TEST1_TRIM_EN 0x0010 2338#define MII_TG3_TEST1_CRC_EN 0x8000 2339 2340/* Clause 45 expansion registers */ 2341#define TG3_CL45_D7_EEERES_STAT 0x803e 2342#define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002 2343#define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004 2344 2345 2346/* Fast Ethernet Tranceiver definitions */ 2347#define MII_TG3_FET_PTEST 0x17 2348#define MII_TG3_FET_PTEST_TRIM_SEL 0x0010 2349#define MII_TG3_FET_PTEST_TRIM_2 0x0002 2350#define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000 2351#define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800 2352 2353#define MII_TG3_FET_GEN_STAT 0x1c 2354#define MII_TG3_FET_GEN_STAT_MDIXSTAT 0x2000 2355 2356#define MII_TG3_FET_TEST 0x1f 2357#define MII_TG3_FET_SHADOW_EN 0x0080 2358 2359#define MII_TG3_FET_SHDW_MISCCTRL 0x10 2360#define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000 2361 2362#define MII_TG3_FET_SHDW_AUXMODE4 0x1a 2363#define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008 2364 2365#define MII_TG3_FET_SHDW_AUXSTAT2 0x1b 2366#define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 2367 2368 2369/* APE registers. Accessible through BAR1 */ 2370#define TG3_APE_GPIO_MSG 0x0008 2371#define TG3_APE_GPIO_MSG_SHIFT 4 2372#define TG3_APE_EVENT 0x000c 2373#define APE_EVENT_1 0x00000001 2374#define TG3_APE_LOCK_REQ 0x002c 2375#define APE_LOCK_REQ_DRIVER 0x00001000 2376#define TG3_APE_LOCK_GRANT 0x004c 2377#define APE_LOCK_GRANT_DRIVER 0x00001000 2378#define TG3_APE_OTP_CTRL 0x00e8 2379#define APE_OTP_CTRL_PROG_EN 0x200000 2380#define APE_OTP_CTRL_CMD_RD 0x000000 2381#define APE_OTP_CTRL_START 0x000001 2382#define TG3_APE_OTP_STATUS 0x00ec 2383#define APE_OTP_STATUS_CMD_DONE 0x000001 2384#define TG3_APE_OTP_ADDR 0x00f0 2385#define APE_OTP_ADDR_CPU_ENABLE 0x80000000 2386#define TG3_APE_OTP_RD_DATA 0x00f8 2387 2388#define OTP_ADDRESS_MAGIC0 0x00000050 2389#define TG3_OTP_MAGIC0_VALID(val) \ 2390 ((((val) & 0xf0000000) == 0xa0000000) ||\ 2391 (((val) & 0x0f000000) == 0x0a000000)) 2392 2393/* APE shared memory. Accessible through BAR1 */ 2394#define TG3_APE_SHMEM_BASE 0x4000 2395#define TG3_APE_SEG_SIG 0x4000 2396#define APE_SEG_SIG_MAGIC 0x41504521 2397#define TG3_APE_FW_STATUS 0x400c 2398#define APE_FW_STATUS_READY 0x00000100 2399#define TG3_APE_FW_FEATURES 0x4010 2400#define TG3_APE_FW_FEATURE_NCSI 0x00000002 2401#define TG3_APE_FW_VERSION 0x4018 2402#define APE_FW_VERSION_MAJMSK 0xff000000 2403#define APE_FW_VERSION_MAJSFT 24 2404#define APE_FW_VERSION_MINMSK 0x00ff0000 2405#define APE_FW_VERSION_MINSFT 16 2406#define APE_FW_VERSION_REVMSK 0x0000ff00 2407#define APE_FW_VERSION_REVSFT 8 2408#define APE_FW_VERSION_BLDMSK 0x000000ff 2409#define TG3_APE_SEG_MSG_BUF_OFF 0x401c 2410#define TG3_APE_SEG_MSG_BUF_LEN 0x4020 2411#define TG3_APE_HOST_SEG_SIG 0x4200 2412#define APE_HOST_SEG_SIG_MAGIC 0x484f5354 2413#define TG3_APE_HOST_SEG_LEN 0x4204 2414#define APE_HOST_SEG_LEN_MAGIC 0x00000020 2415#define TG3_APE_HOST_INIT_COUNT 0x4208 2416#define TG3_APE_HOST_DRIVER_ID 0x420c 2417#define APE_HOST_DRIVER_ID_LINUX 0xf0000000 2418#define APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2419 (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8) 2420#define TG3_APE_HOST_BEHAVIOR 0x4210 2421#define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2422#define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214 2423#define APE_HOST_HEARTBEAT_INT_DISABLE 0 2424#define APE_HOST_HEARTBEAT_INT_5SEC 5000 2425#define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218 2426#define TG3_APE_HOST_DRVR_STATE 0x421c 2427#define TG3_APE_HOST_DRVR_STATE_START 0x00000001 2428#define TG3_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2429#define TG3_APE_HOST_DRVR_STATE_WOL 0x00000003 2430#define TG3_APE_HOST_WOL_SPEED 0x4224 2431#define TG3_APE_HOST_WOL_SPEED_AUTO 0x00008000 2432 2433#define TG3_APE_EVENT_STATUS 0x4300 2434 2435#define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2436#define APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2437#define APE_EVENT_STATUS_SCRTCHPD_READ 0x00001600 2438#define APE_EVENT_STATUS_SCRTCHPD_WRITE 0x00001700 2439#define APE_EVENT_STATUS_STATE_START 0x00010000 2440#define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2441#define APE_EVENT_STATUS_STATE_WOL 0x00030000 2442#define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2443#define APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2444 2445#define TG3_APE_PER_LOCK_REQ 0x8400 2446#define APE_LOCK_PER_REQ_DRIVER 0x00001000 2447#define TG3_APE_PER_LOCK_GRANT 0x8420 2448#define APE_PER_LOCK_GRANT_DRIVER 0x00001000 2449 2450/* APE convenience enumerations. */ 2451#define TG3_APE_LOCK_PHY0 0 2452#define TG3_APE_LOCK_GRC 1 2453#define TG3_APE_LOCK_PHY1 2 2454#define TG3_APE_LOCK_PHY2 3 2455#define TG3_APE_LOCK_MEM 4 2456#define TG3_APE_LOCK_PHY3 5 2457#define TG3_APE_LOCK_GPIO 7 2458 2459#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 2460 2461 2462/* There are two ways to manage the TX descriptors on the tigon3. 2463 * Either the descriptors are in host DMA'able memory, or they 2464 * exist only in the cards on-chip SRAM. All 16 send bds are under 2465 * the same mode, they may not be configured individually. 2466 * 2467 * This driver always uses host memory TX descriptors. 2468 * 2469 * To use host memory TX descriptors: 2470 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register. 2471 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear. 2472 * 2) Allocate DMA'able memory. 2473 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 2474 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory 2475 * obtained in step 2 2476 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC. 2477 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number 2478 * of TX descriptors. Leave flags field clear. 2479 * 4) Access TX descriptors via host memory. The chip 2480 * will refetch into local SRAM as needed when producer 2481 * index mailboxes are updated. 2482 * 2483 * To use on-chip TX descriptors: 2484 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register. 2485 * Make sure GRC_MODE_HOST_SENDBDS is clear. 2486 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 2487 * a) Set TG3_BDINFO_HOST_ADDR to zero. 2488 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC 2489 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care. 2490 * 3) Access TX descriptors directly in on-chip SRAM 2491 * using normal {read,write}l(). (and not using 2492 * pointer dereferencing of ioremap()'d memory like 2493 * the broken Broadcom driver does) 2494 * 2495 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of 2496 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices. 2497 */ 2498struct tg3_tx_buffer_desc { 2499 u32 addr_hi; 2500 u32 addr_lo; 2501 2502 u32 len_flags; 2503#define TXD_FLAG_TCPUDP_CSUM 0x0001 2504#define TXD_FLAG_IP_CSUM 0x0002 2505#define TXD_FLAG_END 0x0004 2506#define TXD_FLAG_IP_FRAG 0x0008 2507#define TXD_FLAG_JMB_PKT 0x0008 2508#define TXD_FLAG_IP_FRAG_END 0x0010 2509#define TXD_FLAG_HWTSTAMP 0x0020 2510#define TXD_FLAG_VLAN 0x0040 2511#define TXD_FLAG_COAL_NOW 0x0080 2512#define TXD_FLAG_CPU_PRE_DMA 0x0100 2513#define TXD_FLAG_CPU_POST_DMA 0x0200 2514#define TXD_FLAG_ADD_SRC_ADDR 0x1000 2515#define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000 2516#define TXD_FLAG_NO_CRC 0x8000 2517#define TXD_LEN_SHIFT 16 2518 2519 u32 vlan_tag; 2520#define TXD_VLAN_TAG_SHIFT 0 2521#define TXD_MSS_SHIFT 16 2522}; 2523 2524#define TXD_ADDR 0x00UL /* 64-bit */ 2525#define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */ 2526#define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */ 2527#define TXD_SIZE 0x10UL 2528 2529struct tg3_rx_buffer_desc { 2530 u32 addr_hi; 2531 u32 addr_lo; 2532 2533 u32 idx_len; 2534#define RXD_IDX_MASK 0xffff0000 2535#define RXD_IDX_SHIFT 16 2536#define RXD_LEN_MASK 0x0000ffff 2537#define RXD_LEN_SHIFT 0 2538 2539 u32 type_flags; 2540#define RXD_TYPE_SHIFT 16 2541#define RXD_FLAGS_SHIFT 0 2542 2543#define RXD_FLAG_END 0x0004 2544#define RXD_FLAG_MINI 0x0800 2545#define RXD_FLAG_JUMBO 0x0020 2546#define RXD_FLAG_VLAN 0x0040 2547#define RXD_FLAG_ERROR 0x0400 2548#define RXD_FLAG_IP_CSUM 0x1000 2549#define RXD_FLAG_TCPUDP_CSUM 0x2000 2550#define RXD_FLAG_IS_TCP 0x4000 2551#define RXD_FLAG_PTPSTAT_MASK 0x0210 2552#define RXD_FLAG_PTPSTAT_PTPV1 0x0010 2553#define RXD_FLAG_PTPSTAT_PTPV2 0x0200 2554 2555 u32 ip_tcp_csum; 2556#define RXD_IPCSUM_MASK 0xffff0000 2557#define RXD_IPCSUM_SHIFT 16 2558#define RXD_TCPCSUM_MASK 0x0000ffff 2559#define RXD_TCPCSUM_SHIFT 0 2560 2561 u32 err_vlan; 2562 2563#define RXD_VLAN_MASK 0x0000ffff 2564 2565#define RXD_ERR_BAD_CRC 0x00010000 2566#define RXD_ERR_COLLISION 0x00020000 2567#define RXD_ERR_LINK_LOST 0x00040000 2568#define RXD_ERR_PHY_DECODE 0x00080000 2569#define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000 2570#define RXD_ERR_MAC_ABRT 0x00200000 2571#define RXD_ERR_TOO_SMALL 0x00400000 2572#define RXD_ERR_NO_RESOURCES 0x00800000 2573#define RXD_ERR_HUGE_FRAME 0x01000000 2574#define RXD_ERR_MASK 0xffff0000 2575 2576 u32 reserved; 2577 u32 opaque; 2578#define RXD_OPAQUE_INDEX_MASK 0x0000ffff 2579#define RXD_OPAQUE_INDEX_SHIFT 0 2580#define RXD_OPAQUE_RING_STD 0x00010000 2581#define RXD_OPAQUE_RING_JUMBO 0x00020000 2582#define RXD_OPAQUE_RING_MINI 0x00040000 2583#define RXD_OPAQUE_RING_MASK 0x00070000 2584}; 2585 2586struct tg3_ext_rx_buffer_desc { 2587 struct { 2588 u32 addr_hi; 2589 u32 addr_lo; 2590 } addrlist[3]; 2591 u32 len2_len1; 2592 u32 resv_len3; 2593 struct tg3_rx_buffer_desc std; 2594}; 2595 2596/* We only use this when testing out the DMA engine 2597 * at probe time. This is the internal format of buffer 2598 * descriptors used by the chip at NIC_SRAM_DMA_DESCS. 2599 */ 2600struct tg3_internal_buffer_desc { 2601 u32 addr_hi; 2602 u32 addr_lo; 2603 u32 nic_mbuf; 2604 /* XXX FIX THIS */ 2605#ifdef __BIG_ENDIAN 2606 u16 cqid_sqid; 2607 u16 len; 2608#else 2609 u16 len; 2610 u16 cqid_sqid; 2611#endif 2612 u32 flags; 2613 u32 __cookie1; 2614 u32 __cookie2; 2615 u32 __cookie3; 2616}; 2617 2618#define TG3_HW_STATUS_SIZE 0x50 2619struct tg3_hw_status { 2620 u32 status; 2621#define SD_STATUS_UPDATED 0x00000001 2622#define SD_STATUS_LINK_CHG 0x00000002 2623#define SD_STATUS_ERROR 0x00000004 2624 2625 u32 status_tag; 2626 2627#ifdef __BIG_ENDIAN 2628 u16 rx_consumer; 2629 u16 rx_jumbo_consumer; 2630#else 2631 u16 rx_jumbo_consumer; 2632 u16 rx_consumer; 2633#endif 2634 2635#ifdef __BIG_ENDIAN 2636 u16 reserved; 2637 u16 rx_mini_consumer; 2638#else 2639 u16 rx_mini_consumer; 2640 u16 reserved; 2641#endif 2642 struct { 2643#ifdef __BIG_ENDIAN 2644 u16 tx_consumer; 2645 u16 rx_producer; 2646#else 2647 u16 rx_producer; 2648 u16 tx_consumer; 2649#endif 2650 } idx[16]; 2651}; 2652 2653typedef struct { 2654 u32 high, low; 2655} tg3_stat64_t; 2656 2657struct tg3_hw_stats { 2658 u8 __reserved0[0x400-0x300]; 2659 2660 /* Statistics maintained by Receive MAC. */ 2661 tg3_stat64_t rx_octets; 2662 u64 __reserved1; 2663 tg3_stat64_t rx_fragments; 2664 tg3_stat64_t rx_ucast_packets; 2665 tg3_stat64_t rx_mcast_packets; 2666 tg3_stat64_t rx_bcast_packets; 2667 tg3_stat64_t rx_fcs_errors; 2668 tg3_stat64_t rx_align_errors; 2669 tg3_stat64_t rx_xon_pause_rcvd; 2670 tg3_stat64_t rx_xoff_pause_rcvd; 2671 tg3_stat64_t rx_mac_ctrl_rcvd; 2672 tg3_stat64_t rx_xoff_entered; 2673 tg3_stat64_t rx_frame_too_long_errors; 2674 tg3_stat64_t rx_jabbers; 2675 tg3_stat64_t rx_undersize_packets; 2676 tg3_stat64_t rx_in_length_errors; 2677 tg3_stat64_t rx_out_length_errors; 2678 tg3_stat64_t rx_64_or_less_octet_packets; 2679 tg3_stat64_t rx_65_to_127_octet_packets; 2680 tg3_stat64_t rx_128_to_255_octet_packets; 2681 tg3_stat64_t rx_256_to_511_octet_packets; 2682 tg3_stat64_t rx_512_to_1023_octet_packets; 2683 tg3_stat64_t rx_1024_to_1522_octet_packets; 2684 tg3_stat64_t rx_1523_to_2047_octet_packets; 2685 tg3_stat64_t rx_2048_to_4095_octet_packets; 2686 tg3_stat64_t rx_4096_to_8191_octet_packets; 2687 tg3_stat64_t rx_8192_to_9022_octet_packets; 2688 2689 u64 __unused0[37]; 2690 2691 /* Statistics maintained by Transmit MAC. */ 2692 tg3_stat64_t tx_octets; 2693 u64 __reserved2; 2694 tg3_stat64_t tx_collisions; 2695 tg3_stat64_t tx_xon_sent; 2696 tg3_stat64_t tx_xoff_sent; 2697 tg3_stat64_t tx_flow_control; 2698 tg3_stat64_t tx_mac_errors; 2699 tg3_stat64_t tx_single_collisions; 2700 tg3_stat64_t tx_mult_collisions; 2701 tg3_stat64_t tx_deferred; 2702 u64 __reserved3; 2703 tg3_stat64_t tx_excessive_collisions; 2704 tg3_stat64_t tx_late_collisions; 2705 tg3_stat64_t tx_collide_2times; 2706 tg3_stat64_t tx_collide_3times; 2707 tg3_stat64_t tx_collide_4times; 2708 tg3_stat64_t tx_collide_5times; 2709 tg3_stat64_t tx_collide_6times; 2710 tg3_stat64_t tx_collide_7times; 2711 tg3_stat64_t tx_collide_8times; 2712 tg3_stat64_t tx_collide_9times; 2713 tg3_stat64_t tx_collide_10times; 2714 tg3_stat64_t tx_collide_11times; 2715 tg3_stat64_t tx_collide_12times; 2716 tg3_stat64_t tx_collide_13times; 2717 tg3_stat64_t tx_collide_14times; 2718 tg3_stat64_t tx_collide_15times; 2719 tg3_stat64_t tx_ucast_packets; 2720 tg3_stat64_t tx_mcast_packets; 2721 tg3_stat64_t tx_bcast_packets; 2722 tg3_stat64_t tx_carrier_sense_errors; 2723 tg3_stat64_t tx_discards; 2724 tg3_stat64_t tx_errors; 2725 2726 u64 __unused1[31]; 2727 2728 /* Statistics maintained by Receive List Placement. */ 2729 tg3_stat64_t COS_rx_packets[16]; 2730 tg3_stat64_t COS_rx_filter_dropped; 2731 tg3_stat64_t dma_writeq_full; 2732 tg3_stat64_t dma_write_prioq_full; 2733 tg3_stat64_t rxbds_empty; 2734 tg3_stat64_t rx_discards; 2735 tg3_stat64_t rx_errors; 2736 tg3_stat64_t rx_threshold_hit; 2737 2738 u64 __unused2[9]; 2739 2740 /* Statistics maintained by Send Data Initiator. */ 2741 tg3_stat64_t COS_out_packets[16]; 2742 tg3_stat64_t dma_readq_full; 2743 tg3_stat64_t dma_read_prioq_full; 2744 tg3_stat64_t tx_comp_queue_full; 2745 2746 /* Statistics maintained by Host Coalescing. */ 2747 tg3_stat64_t ring_set_send_prod_index; 2748 tg3_stat64_t ring_status_update; 2749 tg3_stat64_t nic_irqs; 2750 tg3_stat64_t nic_avoided_irqs; 2751 tg3_stat64_t nic_tx_threshold_hit; 2752 2753 /* NOT a part of the hardware statistics block format. 2754 * These stats are here as storage for tg3_periodic_fetch_stats(). 2755 */ 2756 tg3_stat64_t mbuf_lwm_thresh_hit; 2757 2758 u8 __reserved4[0xb00-0x9c8]; 2759}; 2760 2761#define TG3_SD_NUM_RECS 3 2762#define TG3_OCIR_LEN (sizeof(struct tg3_ocir)) 2763#define TG3_OCIR_SIG_MAGIC 0x5253434f 2764#define TG3_OCIR_FLAG_ACTIVE 0x00000001 2765 2766#define TG3_TEMP_CAUTION_OFFSET 0xc8 2767#define TG3_TEMP_MAX_OFFSET 0xcc 2768#define TG3_TEMP_SENSOR_OFFSET 0xd4 2769 2770 2771struct tg3_ocir { 2772 u32 signature; 2773 u16 version_flags; 2774 u16 refresh_int; 2775 u32 refresh_tmr; 2776 u32 update_tmr; 2777 u32 dst_base_addr; 2778 u16 src_hdr_offset; 2779 u16 src_hdr_length; 2780 u16 src_data_offset; 2781 u16 src_data_length; 2782 u16 dst_hdr_offset; 2783 u16 dst_data_offset; 2784 u16 dst_reg_upd_offset; 2785 u16 dst_sem_offset; 2786 u32 reserved1[2]; 2787 u32 port0_flags; 2788 u32 port1_flags; 2789 u32 port2_flags; 2790 u32 port3_flags; 2791 u32 reserved2[1]; 2792}; 2793 2794 2795/* 'mapping' is superfluous as the chip does not write into 2796 * the tx/rx post rings so we could just fetch it from there. 2797 * But the cache behavior is better how we are doing it now. 2798 * 2799 * This driver uses new build_skb() API : 2800 * RX ring buffer contains pointer to kmalloc() data only, 2801 * skb are built only after Hardware filled the frame. 2802 */ 2803struct ring_info { 2804 u8 *data; 2805 DEFINE_DMA_UNMAP_ADDR(mapping); 2806}; 2807 2808struct tg3_tx_ring_info { 2809 struct sk_buff *skb; 2810 DEFINE_DMA_UNMAP_ADDR(mapping); 2811 bool fragmented; 2812}; 2813 2814struct tg3_link_config { 2815 /* Describes what we're trying to get. */ 2816 u32 advertising; 2817 u16 speed; 2818 u8 duplex; 2819 u8 autoneg; 2820 u8 flowctrl; 2821 2822 /* Describes what we actually have. */ 2823 u8 active_flowctrl; 2824 2825 u8 active_duplex; 2826 u16 active_speed; 2827 u32 rmt_adv; 2828}; 2829 2830struct tg3_bufmgr_config { 2831 u32 mbuf_read_dma_low_water; 2832 u32 mbuf_mac_rx_low_water; 2833 u32 mbuf_high_water; 2834 2835 u32 mbuf_read_dma_low_water_jumbo; 2836 u32 mbuf_mac_rx_low_water_jumbo; 2837 u32 mbuf_high_water_jumbo; 2838 2839 u32 dma_low_water; 2840 u32 dma_high_water; 2841}; 2842 2843struct tg3_ethtool_stats { 2844 /* Statistics maintained by Receive MAC. */ 2845 u64 rx_octets; 2846 u64 rx_fragments; 2847 u64 rx_ucast_packets; 2848 u64 rx_mcast_packets; 2849 u64 rx_bcast_packets; 2850 u64 rx_fcs_errors; 2851 u64 rx_align_errors; 2852 u64 rx_xon_pause_rcvd; 2853 u64 rx_xoff_pause_rcvd; 2854 u64 rx_mac_ctrl_rcvd; 2855 u64 rx_xoff_entered; 2856 u64 rx_frame_too_long_errors; 2857 u64 rx_jabbers; 2858 u64 rx_undersize_packets; 2859 u64 rx_in_length_errors; 2860 u64 rx_out_length_errors; 2861 u64 rx_64_or_less_octet_packets; 2862 u64 rx_65_to_127_octet_packets; 2863 u64 rx_128_to_255_octet_packets; 2864 u64 rx_256_to_511_octet_packets; 2865 u64 rx_512_to_1023_octet_packets; 2866 u64 rx_1024_to_1522_octet_packets; 2867 u64 rx_1523_to_2047_octet_packets; 2868 u64 rx_2048_to_4095_octet_packets; 2869 u64 rx_4096_to_8191_octet_packets; 2870 u64 rx_8192_to_9022_octet_packets; 2871 2872 /* Statistics maintained by Transmit MAC. */ 2873 u64 tx_octets; 2874 u64 tx_collisions; 2875 u64 tx_xon_sent; 2876 u64 tx_xoff_sent; 2877 u64 tx_flow_control; 2878 u64 tx_mac_errors; 2879 u64 tx_single_collisions; 2880 u64 tx_mult_collisions; 2881 u64 tx_deferred; 2882 u64 tx_excessive_collisions; 2883 u64 tx_late_collisions; 2884 u64 tx_collide_2times; 2885 u64 tx_collide_3times; 2886 u64 tx_collide_4times; 2887 u64 tx_collide_5times; 2888 u64 tx_collide_6times; 2889 u64 tx_collide_7times; 2890 u64 tx_collide_8times; 2891 u64 tx_collide_9times; 2892 u64 tx_collide_10times; 2893 u64 tx_collide_11times; 2894 u64 tx_collide_12times; 2895 u64 tx_collide_13times; 2896 u64 tx_collide_14times; 2897 u64 tx_collide_15times; 2898 u64 tx_ucast_packets; 2899 u64 tx_mcast_packets; 2900 u64 tx_bcast_packets; 2901 u64 tx_carrier_sense_errors; 2902 u64 tx_discards; 2903 u64 tx_errors; 2904 2905 /* Statistics maintained by Receive List Placement. */ 2906 u64 dma_writeq_full; 2907 u64 dma_write_prioq_full; 2908 u64 rxbds_empty; 2909 u64 rx_discards; 2910 u64 rx_errors; 2911 u64 rx_threshold_hit; 2912 2913 /* Statistics maintained by Send Data Initiator. */ 2914 u64 dma_readq_full; 2915 u64 dma_read_prioq_full; 2916 u64 tx_comp_queue_full; 2917 2918 /* Statistics maintained by Host Coalescing. */ 2919 u64 ring_set_send_prod_index; 2920 u64 ring_status_update; 2921 u64 nic_irqs; 2922 u64 nic_avoided_irqs; 2923 u64 nic_tx_threshold_hit; 2924 2925 u64 mbuf_lwm_thresh_hit; 2926}; 2927 2928struct tg3_rx_prodring_set { 2929 u32 rx_std_prod_idx; 2930 u32 rx_std_cons_idx; 2931 u32 rx_jmb_prod_idx; 2932 u32 rx_jmb_cons_idx; 2933 struct tg3_rx_buffer_desc *rx_std; 2934 struct tg3_ext_rx_buffer_desc *rx_jmb; 2935 struct ring_info *rx_std_buffers; 2936 struct ring_info *rx_jmb_buffers; 2937 dma_addr_t rx_std_mapping; 2938 dma_addr_t rx_jmb_mapping; 2939}; 2940 2941#define TG3_RSS_MAX_NUM_QS 4 2942#define TG3_IRQ_MAX_VECS_RSS (TG3_RSS_MAX_NUM_QS + 1) 2943#define TG3_IRQ_MAX_VECS TG3_IRQ_MAX_VECS_RSS 2944 2945struct tg3_napi { 2946 struct napi_struct napi ____cacheline_aligned; 2947 struct tg3 *tp; 2948 struct tg3_hw_status *hw_status; 2949 2950 u32 chk_msi_cnt; 2951 u32 last_tag; 2952 u32 last_irq_tag; 2953 u32 int_mbox; 2954 u32 coal_now; 2955 2956 u32 consmbox ____cacheline_aligned; 2957 u32 rx_rcb_ptr; 2958 u32 last_rx_cons; 2959 u16 *rx_rcb_prod_idx; 2960 struct tg3_rx_prodring_set prodring; 2961 struct tg3_rx_buffer_desc *rx_rcb; 2962 2963 u32 tx_prod ____cacheline_aligned; 2964 u32 tx_cons; 2965 u32 tx_pending; 2966 u32 last_tx_cons; 2967 u32 prodmbox; 2968 struct tg3_tx_buffer_desc *tx_ring; 2969 struct tg3_tx_ring_info *tx_buffers; 2970 2971 dma_addr_t status_mapping; 2972 dma_addr_t rx_rcb_mapping; 2973 dma_addr_t tx_desc_mapping; 2974 2975 char irq_lbl[IFNAMSIZ]; 2976 unsigned int irq_vec; 2977}; 2978 2979enum TG3_FLAGS { 2980 TG3_FLAG_TAGGED_STATUS = 0, 2981 TG3_FLAG_TXD_MBOX_HWBUG, 2982 TG3_FLAG_USE_LINKCHG_REG, 2983 TG3_FLAG_ERROR_PROCESSED, 2984 TG3_FLAG_ENABLE_ASF, 2985 TG3_FLAG_ASPM_WORKAROUND, 2986 TG3_FLAG_POLL_SERDES, 2987 TG3_FLAG_MBOX_WRITE_REORDER, 2988 TG3_FLAG_PCIX_TARGET_HWBUG, 2989 TG3_FLAG_WOL_SPEED_100MB, 2990 TG3_FLAG_WOL_ENABLE, 2991 TG3_FLAG_EEPROM_WRITE_PROT, 2992 TG3_FLAG_NVRAM, 2993 TG3_FLAG_NVRAM_BUFFERED, 2994 TG3_FLAG_SUPPORT_MSI, 2995 TG3_FLAG_SUPPORT_MSIX, 2996 TG3_FLAG_USING_MSI, 2997 TG3_FLAG_USING_MSIX, 2998 TG3_FLAG_PCIX_MODE, 2999 TG3_FLAG_PCI_HIGH_SPEED, 3000 TG3_FLAG_PCI_32BIT, 3001 TG3_FLAG_SRAM_USE_CONFIG, 3002 TG3_FLAG_TX_RECOVERY_PENDING, 3003 TG3_FLAG_WOL_CAP, 3004 TG3_FLAG_JUMBO_RING_ENABLE, 3005 TG3_FLAG_PAUSE_AUTONEG, 3006 TG3_FLAG_CPMU_PRESENT, 3007 TG3_FLAG_40BIT_DMA_BUG, 3008 TG3_FLAG_BROKEN_CHECKSUMS, 3009 TG3_FLAG_JUMBO_CAPABLE, 3010 TG3_FLAG_CHIP_RESETTING, 3011 TG3_FLAG_INIT_COMPLETE, 3012 TG3_FLAG_TSO_BUG, 3013 TG3_FLAG_MAX_RXPEND_64, 3014 TG3_FLAG_TSO_CAPABLE, 3015 TG3_FLAG_PCI_EXPRESS, /* BCM5785 + pci_is_pcie() */ 3016 TG3_FLAG_ASF_NEW_HANDSHAKE, 3017 TG3_FLAG_HW_AUTONEG, 3018 TG3_FLAG_IS_NIC, 3019 TG3_FLAG_FLASH, 3020 TG3_FLAG_HW_TSO_1, 3021 TG3_FLAG_HW_TSO_2, 3022 TG3_FLAG_HW_TSO_3, 3023 TG3_FLAG_ICH_WORKAROUND, 3024 TG3_FLAG_1SHOT_MSI, 3025 TG3_FLAG_NO_FWARE_REPORTED, 3026 TG3_FLAG_NO_NVRAM_ADDR_TRANS, 3027 TG3_FLAG_ENABLE_APE, 3028 TG3_FLAG_PROTECTED_NVRAM, 3029 TG3_FLAG_5701_DMA_BUG, 3030 TG3_FLAG_USE_PHYLIB, 3031 TG3_FLAG_MDIOBUS_INITED, 3032 TG3_FLAG_LRG_PROD_RING_CAP, 3033 TG3_FLAG_RGMII_INBAND_DISABLE, 3034 TG3_FLAG_RGMII_EXT_IBND_RX_EN, 3035 TG3_FLAG_RGMII_EXT_IBND_TX_EN, 3036 TG3_FLAG_CLKREQ_BUG, 3037 TG3_FLAG_NO_NVRAM, 3038 TG3_FLAG_ENABLE_RSS, 3039 TG3_FLAG_ENABLE_TSS, 3040 TG3_FLAG_SHORT_DMA_BUG, 3041 TG3_FLAG_USE_JUMBO_BDFLAG, 3042 TG3_FLAG_L1PLLPD_EN, 3043 TG3_FLAG_APE_HAS_NCSI, 3044 TG3_FLAG_TX_TSTAMP_EN, 3045 TG3_FLAG_4K_FIFO_LIMIT, 3046 TG3_FLAG_5719_RDMA_BUG, 3047 TG3_FLAG_RESET_TASK_PENDING, 3048 TG3_FLAG_PTP_CAPABLE, 3049 TG3_FLAG_5705_PLUS, 3050 TG3_FLAG_IS_5788, 3051 TG3_FLAG_5750_PLUS, 3052 TG3_FLAG_5780_CLASS, 3053 TG3_FLAG_5755_PLUS, 3054 TG3_FLAG_57765_PLUS, 3055 TG3_FLAG_57765_CLASS, 3056 TG3_FLAG_5717_PLUS, 3057 TG3_FLAG_IS_SSB_CORE, 3058 TG3_FLAG_FLUSH_POSTED_WRITES, 3059 TG3_FLAG_ROBOSWITCH, 3060 TG3_FLAG_ONE_DMA_AT_ONCE, 3061 TG3_FLAG_RGMII_MODE, 3062 3063 /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */ 3064 TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */ 3065}; 3066 3067struct tg3 { 3068 /* begin "general, frequently-used members" cacheline section */ 3069 3070 /* If the IRQ handler (which runs lockless) needs to be 3071 * quiesced, the following bitmask state is used. The 3072 * SYNC flag is set by non-IRQ context code to initiate 3073 * the quiescence. 3074 * 3075 * When the IRQ handler notices that SYNC is set, it 3076 * disables interrupts and returns. 3077 * 3078 * When all outstanding IRQ handlers have returned after 3079 * the SYNC flag has been set, the setter can be assured 3080 * that interrupts will no longer get run. 3081 * 3082 * In this way all SMP driver locks are never acquired 3083 * in hw IRQ context, only sw IRQ context or lower. 3084 */ 3085 unsigned int irq_sync; 3086 3087 /* SMP locking strategy: 3088 * 3089 * lock: Held during reset, PHY access, timer, and when 3090 * updating tg3_flags. 3091 * 3092 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds 3093 * netif_tx_lock when it needs to call 3094 * netif_wake_queue. 3095 * 3096 * Both of these locks are to be held with BH safety. 3097 * 3098 * Because the IRQ handler, tg3_poll, and tg3_start_xmit 3099 * are running lockless, it is necessary to completely 3100 * quiesce the chip with tg3_netif_stop and tg3_full_lock 3101 * before reconfiguring the device. 3102 * 3103 * indirect_lock: Held when accessing registers indirectly 3104 * with IRQ disabling. 3105 */ 3106 spinlock_t lock; 3107 spinlock_t indirect_lock; 3108 3109 u32 (*read32) (struct tg3 *, u32); 3110 void (*write32) (struct tg3 *, u32, u32); 3111 u32 (*read32_mbox) (struct tg3 *, u32); 3112 void (*write32_mbox) (struct tg3 *, u32, 3113 u32); 3114 void __iomem *regs; 3115 void __iomem *aperegs; 3116 struct net_device *dev; 3117 struct pci_dev *pdev; 3118 3119 u32 coal_now; 3120 u32 msg_enable; 3121 3122 struct ptp_clock_info ptp_info; 3123 struct ptp_clock *ptp_clock; 3124 s64 ptp_adjust; 3125 3126 /* begin "tx thread" cacheline section */ 3127 void (*write32_tx_mbox) (struct tg3 *, u32, 3128 u32); 3129 u32 dma_limit; 3130 u32 txq_req; 3131 u32 txq_cnt; 3132 u32 txq_max; 3133 3134 /* begin "rx thread" cacheline section */ 3135 struct tg3_napi napi[TG3_IRQ_MAX_VECS]; 3136 void (*write32_rx_mbox) (struct tg3 *, u32, 3137 u32); 3138 u32 rx_copy_thresh; 3139 u32 rx_std_ring_mask; 3140 u32 rx_jmb_ring_mask; 3141 u32 rx_ret_ring_mask; 3142 u32 rx_pending; 3143 u32 rx_jumbo_pending; 3144 u32 rx_std_max_post; 3145 u32 rx_offset; 3146 u32 rx_pkt_map_sz; 3147 u32 rxq_req; 3148 u32 rxq_cnt; 3149 u32 rxq_max; 3150 bool rx_refill; 3151 3152 3153 /* begin "everything else" cacheline(s) section */ 3154 unsigned long rx_dropped; 3155 unsigned long tx_dropped; 3156 struct rtnl_link_stats64 net_stats_prev; 3157 struct tg3_ethtool_stats estats_prev; 3158 3159 DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS); 3160 3161 union { 3162 unsigned long phy_crc_errors; 3163 unsigned long last_event_jiffies; 3164 }; 3165 3166 struct timer_list timer; 3167 u16 timer_counter; 3168 u16 timer_multiplier; 3169 u32 timer_offset; 3170 u16 asf_counter; 3171 u16 asf_multiplier; 3172 3173 /* 1 second counter for transient serdes link events */ 3174 u32 serdes_counter; 3175#define SERDES_AN_TIMEOUT_5704S 2 3176#define SERDES_PARALLEL_DET_TIMEOUT 1 3177#define SERDES_AN_TIMEOUT_5714S 1 3178 3179 struct tg3_link_config link_config; 3180 struct tg3_bufmgr_config bufmgr_config; 3181 3182 /* cache h/w values, often passed straight to h/w */ 3183 u32 rx_mode; 3184 u32 tx_mode; 3185 u32 mac_mode; 3186 u32 mi_mode; 3187 u32 misc_host_ctrl; 3188 u32 grc_mode; 3189 u32 grc_local_ctrl; 3190 u32 dma_rwctrl; 3191 u32 coalesce_mode; 3192 u32 pwrmgmt_thresh; 3193 u32 rxptpctl; 3194 3195 /* PCI block */ 3196 u32 pci_chip_rev_id; 3197 u16 pci_cmd; 3198 u8 pci_cacheline_sz; 3199 u8 pci_lat_timer; 3200 3201 int pci_fn; 3202 int pm_cap; 3203 int msi_cap; 3204 int pcix_cap; 3205 int pcie_readrq; 3206 3207 struct mii_bus *mdio_bus; 3208 int mdio_irq[PHY_MAX_ADDR]; 3209 int old_link; 3210 3211 u8 phy_addr; 3212 u8 phy_ape_lock; 3213 3214 /* PHY info */ 3215 u32 phy_id; 3216#define TG3_PHY_ID_MASK 0xfffffff0 3217#define TG3_PHY_ID_BCM5400 0x60008040 3218#define TG3_PHY_ID_BCM5401 0x60008050 3219#define TG3_PHY_ID_BCM5411 0x60008070 3220#define TG3_PHY_ID_BCM5701 0x60008110 3221#define TG3_PHY_ID_BCM5703 0x60008160 3222#define TG3_PHY_ID_BCM5704 0x60008190 3223#define TG3_PHY_ID_BCM5705 0x600081a0 3224#define TG3_PHY_ID_BCM5750 0x60008180 3225#define TG3_PHY_ID_BCM5752 0x60008100 3226#define TG3_PHY_ID_BCM5714 0x60008340 3227#define TG3_PHY_ID_BCM5780 0x60008350 3228#define TG3_PHY_ID_BCM5755 0xbc050cc0 3229#define TG3_PHY_ID_BCM5787 0xbc050ce0 3230#define TG3_PHY_ID_BCM5756 0xbc050ed0 3231#define TG3_PHY_ID_BCM5784 0xbc050fa0 3232#define TG3_PHY_ID_BCM5761 0xbc050fd0 3233#define TG3_PHY_ID_BCM5718C 0x5c0d8a00 3234#define TG3_PHY_ID_BCM5718S 0xbc050ff0 3235#define TG3_PHY_ID_BCM57765 0x5c0d8a40 3236#define TG3_PHY_ID_BCM5719C 0x5c0d8a20 3237#define TG3_PHY_ID_BCM5720C 0x5c0d8b60 3238#define TG3_PHY_ID_BCM5762 0x85803780 3239#define TG3_PHY_ID_BCM5906 0xdc00ac40 3240#define TG3_PHY_ID_BCM8002 0x60010140 3241#define TG3_PHY_ID_INVALID 0xffffffff 3242 3243#define PHY_ID_RTL8211C 0x001cc910 3244#define PHY_ID_RTL8201E 0x00008200 3245 3246#define TG3_PHY_ID_REV_MASK 0x0000000f 3247#define TG3_PHY_REV_BCM5401_B0 0x1 3248 3249 /* This macro assumes the passed PHY ID is 3250 * already masked with TG3_PHY_ID_MASK. 3251 */ 3252#define TG3_KNOWN_PHY_ID(X) \ 3253 ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \ 3254 (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \ 3255 (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \ 3256 (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \ 3257 (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \ 3258 (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \ 3259 (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \ 3260 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \ 3261 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \ 3262 (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \ 3263 (X) == TG3_PHY_ID_BCM5720C || (X) == TG3_PHY_ID_BCM5762 || \ 3264 (X) == TG3_PHY_ID_BCM8002) 3265 3266 u32 phy_flags; 3267#define TG3_PHYFLG_IS_LOW_POWER 0x00000001 3268#define TG3_PHYFLG_IS_CONNECTED 0x00000002 3269#define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004 3270#define TG3_PHYFLG_PHY_SERDES 0x00000010 3271#define TG3_PHYFLG_MII_SERDES 0x00000020 3272#define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \ 3273 TG3_PHYFLG_MII_SERDES) 3274#define TG3_PHYFLG_IS_FET 0x00000040 3275#define TG3_PHYFLG_10_100_ONLY 0x00000080 3276#define TG3_PHYFLG_ENABLE_APD 0x00000100 3277#define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200 3278#define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400 3279#define TG3_PHYFLG_JITTER_BUG 0x00000800 3280#define TG3_PHYFLG_ADJUST_TRIM 0x00001000 3281#define TG3_PHYFLG_ADC_BUG 0x00002000 3282#define TG3_PHYFLG_5704_A0_BUG 0x00004000 3283#define TG3_PHYFLG_BER_BUG 0x00008000 3284#define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000 3285#define TG3_PHYFLG_PARALLEL_DETECT 0x00020000 3286#define TG3_PHYFLG_EEE_CAP 0x00040000 3287#define TG3_PHYFLG_MDIX_STATE 0x00200000 3288 3289 u32 led_ctrl; 3290 u32 phy_otp; 3291 u32 setlpicnt; 3292 u8 rss_ind_tbl[TG3_RSS_INDIR_TBL_SIZE]; 3293 3294#define TG3_BPN_SIZE 24 3295 char board_part_number[TG3_BPN_SIZE]; 3296#define TG3_VER_SIZE ETHTOOL_FWVERS_LEN 3297 char fw_ver[TG3_VER_SIZE]; 3298 u32 nic_sram_data_cfg; 3299 u32 pci_clock_ctrl; 3300 struct pci_dev *pdev_peer; 3301 3302 struct tg3_hw_stats *hw_stats; 3303 dma_addr_t stats_mapping; 3304 struct work_struct reset_task; 3305 3306 int nvram_lock_cnt; 3307 u32 nvram_size; 3308#define TG3_NVRAM_SIZE_2KB 0x00000800 3309#define TG3_NVRAM_SIZE_64KB 0x00010000 3310#define TG3_NVRAM_SIZE_128KB 0x00020000 3311#define TG3_NVRAM_SIZE_256KB 0x00040000 3312#define TG3_NVRAM_SIZE_512KB 0x00080000 3313#define TG3_NVRAM_SIZE_1MB 0x00100000 3314#define TG3_NVRAM_SIZE_2MB 0x00200000 3315 3316 u32 nvram_pagesize; 3317 u32 nvram_jedecnum; 3318 3319#define JEDEC_ATMEL 0x1f 3320#define JEDEC_ST 0x20 3321#define JEDEC_SAIFUN 0x4f 3322#define JEDEC_SST 0xbf 3323 3324#define ATMEL_AT24C02_CHIP_SIZE TG3_NVRAM_SIZE_2KB 3325#define ATMEL_AT24C02_PAGE_SIZE (8) 3326 3327#define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB 3328#define ATMEL_AT24C64_PAGE_SIZE (32) 3329 3330#define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB 3331#define ATMEL_AT24C512_PAGE_SIZE (128) 3332 3333#define ATMEL_AT45DB0X1B_PAGE_POS 9 3334#define ATMEL_AT45DB0X1B_PAGE_SIZE 264 3335 3336#define ATMEL_AT25F512_PAGE_SIZE 256 3337 3338#define ST_M45PEX0_PAGE_SIZE 256 3339 3340#define SAIFUN_SA25F0XX_PAGE_SIZE 256 3341 3342#define SST_25VF0X0_PAGE_SIZE 4098 3343 3344 unsigned int irq_max; 3345 unsigned int irq_cnt; 3346 3347 struct ethtool_coalesce coal; 3348 3349 /* firmware info */ 3350 const char *fw_needed; 3351 const struct firmware *fw; 3352 u32 fw_len; /* includes BSS */ 3353 3354 struct device *hwmon_dev; 3355 bool link_up; 3356}; 3357 3358/* Accessor macros for chip and asic attributes 3359 * 3360 * nb: Using static inlines equivalent to the accessor macros generates 3361 * larger object code with gcc 4.7. 3362 * Using statement expression macros to check tp with 3363 * typecheck(struct tg3 *, tp) also creates larger objects. 3364 */ 3365#define tg3_chip_rev_id(tp) \ 3366 ((tp)->pci_chip_rev_id) 3367#define tg3_asic_rev(tp) \ 3368 ((tp)->pci_chip_rev_id >> 12) 3369#define tg3_chip_rev(tp) \ 3370 ((tp)->pci_chip_rev_id >> 8) 3371 3372#endif /* !(_T3_H) */