tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1 /*
2 * iio/adc/max1363.c
3 * Copyright (C) 2008-2010 Jonathan Cameron
4 *
5 * based on linux/drivers/i2c/chips/max123x
6 * Copyright (C) 2002-2004 Stefan Eletzhofer
7 *
8 * based on linux/drivers/acron/char/pcf8583.c
9 * Copyright (C) 2000 Russell King
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * max1363.c
16 *
17 * Partial support for max1363 and similar chips.
18 *
19 * Not currently implemented.
20 *
21 * - Control of internal reference.
22 */
23
24#include <linux/interrupt.h>
25#include <linux/device.h>
26#include <linux/kernel.h>
27#include <linux/sysfs.h>
28#include <linux/list.h>
29#include <linux/i2c.h>
30#include <linux/regulator/consumer.h>
31#include <linux/slab.h>
32#include <linux/err.h>
33#include <linux/module.h>
34
35#include <linux/iio/iio.h>
36#include <linux/iio/sysfs.h>
37#include <linux/iio/events.h>
38#include <linux/iio/buffer.h>
39#include <linux/iio/driver.h>
40#include <linux/iio/kfifo_buf.h>
41#include <linux/iio/trigger_consumer.h>
42#include <linux/iio/triggered_buffer.h>
43
44#define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
45
46/* There is a fair bit more defined here than currently
47 * used, but the intention is to support everything these
48 * chips do in the long run */
49
50/* see data sheets */
51/* max1363 and max1236, max1237, max1238, max1239 */
52#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00
53#define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20
54#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40
55#define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60
56#define MAX1363_SETUP_POWER_UP_INT_REF 0x10
57#define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00
58
59/* think about including max11600 etc - more settings */
60#define MAX1363_SETUP_EXT_CLOCK 0x08
61#define MAX1363_SETUP_INT_CLOCK 0x00
62#define MAX1363_SETUP_UNIPOLAR 0x00
63#define MAX1363_SETUP_BIPOLAR 0x04
64#define MAX1363_SETUP_RESET 0x00
65#define MAX1363_SETUP_NORESET 0x02
66/* max1363 only - though don't care on others.
67 * For now monitor modes are not implemented as the relevant
68 * line is not connected on my test board.
69 * The definitions are here as I intend to add this soon.
70 */
71#define MAX1363_SETUP_MONITOR_SETUP 0x01
72
73/* Specific to the max1363 */
74#define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
75#define MAX1363_MON_INT_ENABLE 0x01
76
77/* defined for readability reasons */
78/* All chips */
79#define MAX1363_CONFIG_BYTE(a) ((a))
80
81#define MAX1363_CONFIG_SE 0x01
82#define MAX1363_CONFIG_DE 0x00
83#define MAX1363_CONFIG_SCAN_TO_CS 0x00
84#define MAX1363_CONFIG_SCAN_SINGLE_8 0x20
85#define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40
86#define MAX1363_CONFIG_SCAN_SINGLE_1 0x60
87/* max123{6-9} only */
88#define MAX1236_SCAN_MID_TO_CHANNEL 0x40
89
90/* max1363 only - merely part of channel selects or don't care for others */
91#define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
92
93#define MAX1363_CHANNEL_SEL(a) ((a) << 1)
94
95/* max1363 strictly 0x06 - but doesn't matter */
96#define MAX1363_CHANNEL_SEL_MASK 0x1E
97#define MAX1363_SCAN_MASK 0x60
98#define MAX1363_SE_DE_MASK 0x01
99
100#define MAX1363_MAX_CHANNELS 25
101/**
102 * struct max1363_mode - scan mode information
103 * @conf: The corresponding value of the configuration register
104 * @modemask: Bit mask corresponding to channels enabled in this mode
105 */
106struct max1363_mode {
107 int8_t conf;
108 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
109};
110
111/* This must be maintained along side the max1363_mode_table in max1363_core */
112enum max1363_modes {
113 /* Single read of a single channel */
114 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
115 /* Differential single read */
116 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
117 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
118 /* Scan to channel and mid to channel where overlapping */
119 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
120 s6to7, s0to7, s6to8, s0to8, s6to9,
121 s0to9, s6to10, s0to10, s6to11, s0to11,
122 /* Differential scan to channel and mid to channel where overlapping */
123 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
124 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
125 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
126 d7m6to11m10, d1m0to11m10,
127};
128
129/**
130 * struct max1363_chip_info - chip specifc information
131 * @info: iio core function callbacks structure
132 * @channels: channel specification
133 * @num_channels: number of channels
134 * @mode_list: array of available scan modes
135 * @default_mode: the scan mode in which the chip starts up
136 * @int_vref_mv: the internal reference voltage
137 * @num_modes: number of modes
138 * @bits: accuracy of the adc in bits
139 */
140struct max1363_chip_info {
141 const struct iio_info *info;
142 const struct iio_chan_spec *channels;
143 int num_channels;
144 const enum max1363_modes *mode_list;
145 enum max1363_modes default_mode;
146 u16 int_vref_mv;
147 u8 num_modes;
148 u8 bits;
149};
150
151/**
152 * struct max1363_state - driver instance specific data
153 * @client: i2c_client
154 * @setupbyte: cache of current device setup byte
155 * @configbyte: cache of current device config byte
156 * @chip_info: chip model specific constants, available modes, etc.
157 * @current_mode: the scan mode of this chip
158 * @requestedmask: a valid requested set of channels
159 * @reg: supply regulator
160 * @monitor_on: whether monitor mode is enabled
161 * @monitor_speed: parameter corresponding to device monitor speed setting
162 * @mask_high: bitmask for enabled high thresholds
163 * @mask_low: bitmask for enabled low thresholds
164 * @thresh_high: high threshold values
165 * @thresh_low: low threshold values
166 * @vref: Reference voltage regulator
167 * @vref_uv: Actual (external or internal) reference voltage
168 */
169struct max1363_state {
170 struct i2c_client *client;
171 u8 setupbyte;
172 u8 configbyte;
173 const struct max1363_chip_info *chip_info;
174 const struct max1363_mode *current_mode;
175 u32 requestedmask;
176 struct regulator *reg;
177
178 /* Using monitor modes and buffer at the same time is
179 currently not supported */
180 bool monitor_on;
181 unsigned int monitor_speed:3;
182 u8 mask_high;
183 u8 mask_low;
184 /* 4x unipolar first then the fours bipolar ones */
185 s16 thresh_high[8];
186 s16 thresh_low[8];
187 struct regulator *vref;
188 u32 vref_uv;
189};
190
191#define MAX1363_MODE_SINGLE(_num, _mask) { \
192 .conf = MAX1363_CHANNEL_SEL(_num) \
193 | MAX1363_CONFIG_SCAN_SINGLE_1 \
194 | MAX1363_CONFIG_SE, \
195 .modemask[0] = _mask, \
196 }
197
198#define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
199 .conf = MAX1363_CHANNEL_SEL(_num) \
200 | MAX1363_CONFIG_SCAN_TO_CS \
201 | MAX1363_CONFIG_SE, \
202 .modemask[0] = _mask, \
203 }
204
205/* note not available for max1363 hence naming */
206#define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
207 .conf = MAX1363_CHANNEL_SEL(_num) \
208 | MAX1236_SCAN_MID_TO_CHANNEL \
209 | MAX1363_CONFIG_SE, \
210 .modemask[0] = _mask \
211}
212
213#define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
214 .conf = MAX1363_CHANNEL_SEL(_nump) \
215 | MAX1363_CONFIG_SCAN_SINGLE_1 \
216 | MAX1363_CONFIG_DE, \
217 .modemask[0] = _mask \
218 }
219
220/* Can't think how to automate naming so specify for now */
221#define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
222 .conf = MAX1363_CHANNEL_SEL(_num) \
223 | MAX1363_CONFIG_SCAN_TO_CS \
224 | MAX1363_CONFIG_DE, \
225 .modemask[0] = _mask \
226 }
227
228/* note only available for max1363 hence naming */
229#define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
230 .conf = MAX1363_CHANNEL_SEL(_num) \
231 | MAX1236_SCAN_MID_TO_CHANNEL \
232 | MAX1363_CONFIG_SE, \
233 .modemask[0] = _mask \
234}
235
236static const struct max1363_mode max1363_mode_table[] = {
237 /* All of the single channel options first */
238 MAX1363_MODE_SINGLE(0, 1 << 0),
239 MAX1363_MODE_SINGLE(1, 1 << 1),
240 MAX1363_MODE_SINGLE(2, 1 << 2),
241 MAX1363_MODE_SINGLE(3, 1 << 3),
242 MAX1363_MODE_SINGLE(4, 1 << 4),
243 MAX1363_MODE_SINGLE(5, 1 << 5),
244 MAX1363_MODE_SINGLE(6, 1 << 6),
245 MAX1363_MODE_SINGLE(7, 1 << 7),
246 MAX1363_MODE_SINGLE(8, 1 << 8),
247 MAX1363_MODE_SINGLE(9, 1 << 9),
248 MAX1363_MODE_SINGLE(10, 1 << 10),
249 MAX1363_MODE_SINGLE(11, 1 << 11),
250
251 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
252 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
253 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
254 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
255 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
256 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
257 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
258 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
259 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
260 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
261 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
262 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
263
264 /* The multichannel scans next */
265 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
266 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
267 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
268 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
269 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
270 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
271 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
272 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
273 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
274 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
275 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
276 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
277 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
278 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
279 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
280 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
281 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
282
283 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
284 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
285 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
286 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
287 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
288 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
290 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
291 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
292 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
293 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
294 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
295 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
296 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
297};
298
299static const struct max1363_mode
300*max1363_match_mode(const unsigned long *mask,
301 const struct max1363_chip_info *ci)
302{
303 int i;
304 if (mask)
305 for (i = 0; i < ci->num_modes; i++)
306 if (bitmap_subset(mask,
307 max1363_mode_table[ci->mode_list[i]].
308 modemask,
309 MAX1363_MAX_CHANNELS))
310 return &max1363_mode_table[ci->mode_list[i]];
311 return NULL;
312}
313
314static int max1363_write_basic_config(struct i2c_client *client,
315 unsigned char d1,
316 unsigned char d2)
317{
318 u8 tx_buf[2] = {d1, d2};
319
320 return i2c_master_send(client, tx_buf, 2);
321}
322
323static int max1363_set_scan_mode(struct max1363_state *st)
324{
325 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
326 | MAX1363_SCAN_MASK
327 | MAX1363_SE_DE_MASK);
328 st->configbyte |= st->current_mode->conf;
329
330 return max1363_write_basic_config(st->client,
331 st->setupbyte,
332 st->configbyte);
333}
334
335static int max1363_read_single_chan(struct iio_dev *indio_dev,
336 struct iio_chan_spec const *chan,
337 int *val,
338 long m)
339{
340 int ret = 0;
341 s32 data;
342 u8 rxbuf[2];
343 struct max1363_state *st = iio_priv(indio_dev);
344 struct i2c_client *client = st->client;
345
346 mutex_lock(&indio_dev->mlock);
347 /*
348 * If monitor mode is enabled, the method for reading a single
349 * channel will have to be rather different and has not yet
350 * been implemented.
351 *
352 * Also, cannot read directly if buffered capture enabled.
353 */
354 if (st->monitor_on || iio_buffer_enabled(indio_dev)) {
355 ret = -EBUSY;
356 goto error_ret;
357 }
358
359 /* Check to see if current scan mode is correct */
360 if (st->current_mode != &max1363_mode_table[chan->address]) {
361 /* Update scan mode if needed */
362 st->current_mode = &max1363_mode_table[chan->address];
363 ret = max1363_set_scan_mode(st);
364 if (ret < 0)
365 goto error_ret;
366 }
367 if (st->chip_info->bits != 8) {
368 /* Get reading */
369 data = i2c_master_recv(client, rxbuf, 2);
370 if (data < 0) {
371 ret = data;
372 goto error_ret;
373 }
374 data = (rxbuf[1] | rxbuf[0] << 8) &
375 ((1 << st->chip_info->bits) - 1);
376 } else {
377 /* Get reading */
378 data = i2c_master_recv(client, rxbuf, 1);
379 if (data < 0) {
380 ret = data;
381 goto error_ret;
382 }
383 data = rxbuf[0];
384 }
385 *val = data;
386error_ret:
387 mutex_unlock(&indio_dev->mlock);
388 return ret;
389
390}
391
392static int max1363_read_raw(struct iio_dev *indio_dev,
393 struct iio_chan_spec const *chan,
394 int *val,
395 int *val2,
396 long m)
397{
398 struct max1363_state *st = iio_priv(indio_dev);
399 int ret;
400 unsigned long scale_uv;
401
402 switch (m) {
403 case IIO_CHAN_INFO_RAW:
404 ret = max1363_read_single_chan(indio_dev, chan, val, m);
405 if (ret < 0)
406 return ret;
407 return IIO_VAL_INT;
408 case IIO_CHAN_INFO_SCALE:
409 scale_uv = st->vref_uv >> st->chip_info->bits;
410 *val = scale_uv / 1000;
411 *val2 = (scale_uv % 1000) * 1000;
412 return IIO_VAL_INT_PLUS_MICRO;
413 default:
414 return -EINVAL;
415 }
416 return 0;
417}
418
419/* Applies to max1363 */
420static const enum max1363_modes max1363_mode_list[] = {
421 _s0, _s1, _s2, _s3,
422 s0to1, s0to2, s0to3,
423 d0m1, d2m3, d1m0, d3m2,
424 d0m1to2m3, d1m0to3m2,
425};
426
427#define MAX1363_EV_M \
428 (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) \
429 | IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
430#define MAX1363_INFO_MASK (IIO_CHAN_INFO_RAW_SEPARATE_BIT | \
431 IIO_CHAN_INFO_SCALE_SHARED_BIT)
432#define MAX1363_CHAN_U(num, addr, si, bits, evmask) \
433 { \
434 .type = IIO_VOLTAGE, \
435 .indexed = 1, \
436 .channel = num, \
437 .address = addr, \
438 .info_mask = MAX1363_INFO_MASK, \
439 .datasheet_name = "AIN"#num, \
440 .scan_type = { \
441 .sign = 'u', \
442 .realbits = bits, \
443 .storagebits = (bits > 8) ? 16 : 8, \
444 .endianness = IIO_BE, \
445 }, \
446 .scan_index = si, \
447 .event_mask = evmask, \
448 }
449
450/* bipolar channel */
451#define MAX1363_CHAN_B(num, num2, addr, si, bits, evmask) \
452 { \
453 .type = IIO_VOLTAGE, \
454 .differential = 1, \
455 .indexed = 1, \
456 .channel = num, \
457 .channel2 = num2, \
458 .address = addr, \
459 .info_mask = MAX1363_INFO_MASK, \
460 .datasheet_name = "AIN"#num"-AIN"#num2, \
461 .scan_type = { \
462 .sign = 's', \
463 .realbits = bits, \
464 .storagebits = (bits > 8) ? 16 : 8, \
465 .endianness = IIO_BE, \
466 }, \
467 .scan_index = si, \
468 .event_mask = evmask, \
469 }
470
471#define MAX1363_4X_CHANS(bits, em) { \
472 MAX1363_CHAN_U(0, _s0, 0, bits, em), \
473 MAX1363_CHAN_U(1, _s1, 1, bits, em), \
474 MAX1363_CHAN_U(2, _s2, 2, bits, em), \
475 MAX1363_CHAN_U(3, _s3, 3, bits, em), \
476 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, em), \
477 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, em), \
478 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, em), \
479 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, em), \
480 IIO_CHAN_SOFT_TIMESTAMP(8) \
481 }
482
483static const struct iio_chan_spec max1036_channels[] = MAX1363_4X_CHANS(8, 0);
484static const struct iio_chan_spec max1136_channels[] = MAX1363_4X_CHANS(10, 0);
485static const struct iio_chan_spec max1236_channels[] = MAX1363_4X_CHANS(12, 0);
486static const struct iio_chan_spec max1361_channels[] =
487 MAX1363_4X_CHANS(10, MAX1363_EV_M);
488static const struct iio_chan_spec max1363_channels[] =
489 MAX1363_4X_CHANS(12, MAX1363_EV_M);
490
491/* Applies to max1236, max1237 */
492static const enum max1363_modes max1236_mode_list[] = {
493 _s0, _s1, _s2, _s3,
494 s0to1, s0to2, s0to3,
495 d0m1, d2m3, d1m0, d3m2,
496 d0m1to2m3, d1m0to3m2,
497 s2to3,
498};
499
500/* Applies to max1238, max1239 */
501static const enum max1363_modes max1238_mode_list[] = {
502 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
503 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
504 s0to7, s0to8, s0to9, s0to10, s0to11,
505 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
506 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
507 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
508 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
509 s6to7, s6to8, s6to9, s6to10, s6to11,
510 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
511};
512
513#define MAX1363_12X_CHANS(bits) { \
514 MAX1363_CHAN_U(0, _s0, 0, bits, 0), \
515 MAX1363_CHAN_U(1, _s1, 1, bits, 0), \
516 MAX1363_CHAN_U(2, _s2, 2, bits, 0), \
517 MAX1363_CHAN_U(3, _s3, 3, bits, 0), \
518 MAX1363_CHAN_U(4, _s4, 4, bits, 0), \
519 MAX1363_CHAN_U(5, _s5, 5, bits, 0), \
520 MAX1363_CHAN_U(6, _s6, 6, bits, 0), \
521 MAX1363_CHAN_U(7, _s7, 7, bits, 0), \
522 MAX1363_CHAN_U(8, _s8, 8, bits, 0), \
523 MAX1363_CHAN_U(9, _s9, 9, bits, 0), \
524 MAX1363_CHAN_U(10, _s10, 10, bits, 0), \
525 MAX1363_CHAN_U(11, _s11, 11, bits, 0), \
526 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, 0), \
527 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, 0), \
528 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, 0), \
529 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, 0), \
530 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, 0), \
531 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, 0), \
532 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, 0), \
533 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, 0), \
534 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, 0), \
535 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, 0), \
536 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, 0), \
537 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, 0), \
538 IIO_CHAN_SOFT_TIMESTAMP(24) \
539 }
540static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
541static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
542static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
543
544static const enum max1363_modes max11607_mode_list[] = {
545 _s0, _s1, _s2, _s3,
546 s0to1, s0to2, s0to3,
547 s2to3,
548 d0m1, d2m3, d1m0, d3m2,
549 d0m1to2m3, d1m0to3m2,
550};
551
552static const enum max1363_modes max11608_mode_list[] = {
553 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
554 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
555 s6to7,
556 d0m1, d2m3, d4m5, d6m7,
557 d1m0, d3m2, d5m4, d7m6,
558 d0m1to2m3, d0m1to4m5, d0m1to6m7,
559 d1m0to3m2, d1m0to5m4, d1m0to7m6,
560};
561
562#define MAX1363_8X_CHANS(bits) { \
563 MAX1363_CHAN_U(0, _s0, 0, bits, 0), \
564 MAX1363_CHAN_U(1, _s1, 1, bits, 0), \
565 MAX1363_CHAN_U(2, _s2, 2, bits, 0), \
566 MAX1363_CHAN_U(3, _s3, 3, bits, 0), \
567 MAX1363_CHAN_U(4, _s4, 4, bits, 0), \
568 MAX1363_CHAN_U(5, _s5, 5, bits, 0), \
569 MAX1363_CHAN_U(6, _s6, 6, bits, 0), \
570 MAX1363_CHAN_U(7, _s7, 7, bits, 0), \
571 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, 0), \
572 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, 0), \
573 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, 0), \
574 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, 0), \
575 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, 0), \
576 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, 0), \
577 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, 0), \
578 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, 0), \
579 IIO_CHAN_SOFT_TIMESTAMP(16) \
580}
581static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
582static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
583static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
584
585static const enum max1363_modes max11644_mode_list[] = {
586 _s0, _s1, s0to1, d0m1, d1m0,
587};
588
589#define MAX1363_2X_CHANS(bits) { \
590 MAX1363_CHAN_U(0, _s0, 0, bits, 0), \
591 MAX1363_CHAN_U(1, _s1, 1, bits, 0), \
592 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, 0), \
593 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, 0), \
594 IIO_CHAN_SOFT_TIMESTAMP(4) \
595 }
596
597static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
598static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
599
600enum { max1361,
601 max1362,
602 max1363,
603 max1364,
604 max1036,
605 max1037,
606 max1038,
607 max1039,
608 max1136,
609 max1137,
610 max1138,
611 max1139,
612 max1236,
613 max1237,
614 max1238,
615 max1239,
616 max11600,
617 max11601,
618 max11602,
619 max11603,
620 max11604,
621 max11605,
622 max11606,
623 max11607,
624 max11608,
625 max11609,
626 max11610,
627 max11611,
628 max11612,
629 max11613,
630 max11614,
631 max11615,
632 max11616,
633 max11617,
634 max11644,
635 max11645,
636 max11646,
637 max11647
638};
639
640static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
641 8300, 4200, 2000, 1000 };
642
643static ssize_t max1363_monitor_show_freq(struct device *dev,
644 struct device_attribute *attr,
645 char *buf)
646{
647 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
648 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
649}
650
651static ssize_t max1363_monitor_store_freq(struct device *dev,
652 struct device_attribute *attr,
653 const char *buf,
654 size_t len)
655{
656 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
657 struct max1363_state *st = iio_priv(indio_dev);
658 int i, ret;
659 unsigned long val;
660 bool found = false;
661
662 ret = strict_strtoul(buf, 10, &val);
663 if (ret)
664 return -EINVAL;
665 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
666 if (val == max1363_monitor_speeds[i]) {
667 found = true;
668 break;
669 }
670 if (!found)
671 return -EINVAL;
672
673 mutex_lock(&indio_dev->mlock);
674 st->monitor_speed = i;
675 mutex_unlock(&indio_dev->mlock);
676
677 return 0;
678}
679
680static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
681 max1363_monitor_show_freq,
682 max1363_monitor_store_freq);
683
684static IIO_CONST_ATTR(sampling_frequency_available,
685 "133000 665000 33300 16600 8300 4200 2000 1000");
686
687static int max1363_read_thresh(struct iio_dev *indio_dev,
688 u64 event_code,
689 int *val)
690{
691 struct max1363_state *st = iio_priv(indio_dev);
692 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
693 *val = st->thresh_low[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)];
694 else
695 *val = st->thresh_high[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)];
696 return 0;
697}
698
699static int max1363_write_thresh(struct iio_dev *indio_dev,
700 u64 event_code,
701 int val)
702{
703 struct max1363_state *st = iio_priv(indio_dev);
704 /* make it handle signed correctly as well */
705 switch (st->chip_info->bits) {
706 case 10:
707 if (val > 0x3FF)
708 return -EINVAL;
709 break;
710 case 12:
711 if (val > 0xFFF)
712 return -EINVAL;
713 break;
714 }
715
716 switch (IIO_EVENT_CODE_EXTRACT_DIR(event_code)) {
717 case IIO_EV_DIR_FALLING:
718 st->thresh_low[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)] = val;
719 break;
720 case IIO_EV_DIR_RISING:
721 st->thresh_high[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)] = val;
722 break;
723 }
724
725 return 0;
726}
727
728static const u64 max1363_event_codes[] = {
729 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
730 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
731 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
732 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
733 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
734 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
735 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
736 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
737 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
738 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
739 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
740 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
741 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
742 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
743 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
744 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
745};
746
747static irqreturn_t max1363_event_handler(int irq, void *private)
748{
749 struct iio_dev *indio_dev = private;
750 struct max1363_state *st = iio_priv(indio_dev);
751 s64 timestamp = iio_get_time_ns();
752 unsigned long mask, loc;
753 u8 rx;
754 u8 tx[2] = { st->setupbyte,
755 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
756
757 i2c_master_recv(st->client, &rx, 1);
758 mask = rx;
759 for_each_set_bit(loc, &mask, 8)
760 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
761 i2c_master_send(st->client, tx, 2);
762
763 return IRQ_HANDLED;
764}
765
766static int max1363_read_event_config(struct iio_dev *indio_dev,
767 u64 event_code)
768{
769 struct max1363_state *st = iio_priv(indio_dev);
770 int val;
771 int number = IIO_EVENT_CODE_EXTRACT_CHAN(event_code);
772
773 mutex_lock(&indio_dev->mlock);
774 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
775 val = (1 << number) & st->mask_low;
776 else
777 val = (1 << number) & st->mask_high;
778 mutex_unlock(&indio_dev->mlock);
779
780 return val;
781}
782
783static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
784{
785 u8 *tx_buf;
786 int ret, i = 3, j;
787 unsigned long numelements;
788 int len;
789 const long *modemask;
790
791 if (!enabled) {
792 /* transition to buffered capture is not currently supported */
793 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
794 st->configbyte &= ~MAX1363_SCAN_MASK;
795 st->monitor_on = false;
796 return max1363_write_basic_config(st->client,
797 st->setupbyte,
798 st->configbyte);
799 }
800
801 /* Ensure we are in the relevant mode */
802 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
803 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
804 | MAX1363_SCAN_MASK
805 | MAX1363_SE_DE_MASK);
806 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
807 if ((st->mask_low | st->mask_high) & 0x0F) {
808 st->configbyte |= max1363_mode_table[s0to3].conf;
809 modemask = max1363_mode_table[s0to3].modemask;
810 } else if ((st->mask_low | st->mask_high) & 0x30) {
811 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
812 modemask = max1363_mode_table[d0m1to2m3].modemask;
813 } else {
814 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
815 modemask = max1363_mode_table[d1m0to3m2].modemask;
816 }
817 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
818 len = 3 * numelements + 3;
819 tx_buf = kmalloc(len, GFP_KERNEL);
820 if (!tx_buf) {
821 ret = -ENOMEM;
822 goto error_ret;
823 }
824 tx_buf[0] = st->configbyte;
825 tx_buf[1] = st->setupbyte;
826 tx_buf[2] = (st->monitor_speed << 1);
827
828 /*
829 * So we need to do yet another bit of nefarious scan mode
830 * setup to match what we need.
831 */
832 for (j = 0; j < 8; j++)
833 if (test_bit(j, modemask)) {
834 /* Establish the mode is in the scan */
835 if (st->mask_low & (1 << j)) {
836 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
837 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
838 } else if (j < 4) {
839 tx_buf[i] = 0;
840 tx_buf[i + 1] = 0;
841 } else {
842 tx_buf[i] = 0x80;
843 tx_buf[i + 1] = 0;
844 }
845 if (st->mask_high & (1 << j)) {
846 tx_buf[i + 1] |=
847 (st->thresh_high[j] >> 8) & 0x0F;
848 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
849 } else if (j < 4) {
850 tx_buf[i + 1] |= 0x0F;
851 tx_buf[i + 2] = 0xFF;
852 } else {
853 tx_buf[i + 1] |= 0x07;
854 tx_buf[i + 2] = 0xFF;
855 }
856 i += 3;
857 }
858
859
860 ret = i2c_master_send(st->client, tx_buf, len);
861 if (ret < 0)
862 goto error_ret;
863 if (ret != len) {
864 ret = -EIO;
865 goto error_ret;
866 }
867
868 /*
869 * Now that we hopefully have sensible thresholds in place it is
870 * time to turn the interrupts on.
871 * It is unclear from the data sheet if this should be necessary
872 * (i.e. whether monitor mode setup is atomic) but it appears to
873 * be in practice.
874 */
875 tx_buf[0] = st->setupbyte;
876 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
877 ret = i2c_master_send(st->client, tx_buf, 2);
878 if (ret < 0)
879 goto error_ret;
880 if (ret != 2) {
881 ret = -EIO;
882 goto error_ret;
883 }
884 ret = 0;
885 st->monitor_on = true;
886error_ret:
887
888 kfree(tx_buf);
889
890 return ret;
891}
892
893/*
894 * To keep this manageable we always use one of 3 scan modes.
895 * Scan 0...3, 0-1,2-3 and 1-0,3-2
896 */
897
898static inline int __max1363_check_event_mask(int thismask, int checkmask)
899{
900 int ret = 0;
901 /* Is it unipolar */
902 if (thismask < 4) {
903 if (checkmask & ~0x0F) {
904 ret = -EBUSY;
905 goto error_ret;
906 }
907 } else if (thismask < 6) {
908 if (checkmask & ~0x30) {
909 ret = -EBUSY;
910 goto error_ret;
911 }
912 } else if (checkmask & ~0xC0)
913 ret = -EBUSY;
914error_ret:
915 return ret;
916}
917
918static int max1363_write_event_config(struct iio_dev *indio_dev,
919 u64 event_code,
920 int state)
921{
922 int ret = 0;
923 struct max1363_state *st = iio_priv(indio_dev);
924 u16 unifiedmask;
925 int number = IIO_EVENT_CODE_EXTRACT_CHAN(event_code);
926
927 mutex_lock(&indio_dev->mlock);
928 unifiedmask = st->mask_low | st->mask_high;
929 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING) {
930
931 if (state == 0)
932 st->mask_low &= ~(1 << number);
933 else {
934 ret = __max1363_check_event_mask((1 << number),
935 unifiedmask);
936 if (ret)
937 goto error_ret;
938 st->mask_low |= (1 << number);
939 }
940 } else {
941 if (state == 0)
942 st->mask_high &= ~(1 << number);
943 else {
944 ret = __max1363_check_event_mask((1 << number),
945 unifiedmask);
946 if (ret)
947 goto error_ret;
948 st->mask_high |= (1 << number);
949 }
950 }
951
952 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
953error_ret:
954 mutex_unlock(&indio_dev->mlock);
955
956 return ret;
957}
958
959/*
960 * As with scan_elements, only certain sets of these can
961 * be combined.
962 */
963static struct attribute *max1363_event_attributes[] = {
964 &iio_dev_attr_sampling_frequency.dev_attr.attr,
965 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
966 NULL,
967};
968
969static struct attribute_group max1363_event_attribute_group = {
970 .attrs = max1363_event_attributes,
971 .name = "events",
972};
973
974static int max1363_update_scan_mode(struct iio_dev *indio_dev,
975 const unsigned long *scan_mask)
976{
977 struct max1363_state *st = iio_priv(indio_dev);
978
979 /*
980 * Need to figure out the current mode based upon the requested
981 * scan mask in iio_dev
982 */
983 st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
984 if (!st->current_mode)
985 return -EINVAL;
986 max1363_set_scan_mode(st);
987 return 0;
988}
989
990static const struct iio_info max1238_info = {
991 .read_raw = &max1363_read_raw,
992 .driver_module = THIS_MODULE,
993 .update_scan_mode = &max1363_update_scan_mode,
994};
995
996static const struct iio_info max1363_info = {
997 .read_event_value = &max1363_read_thresh,
998 .write_event_value = &max1363_write_thresh,
999 .read_event_config = &max1363_read_event_config,
1000 .write_event_config = &max1363_write_event_config,
1001 .read_raw = &max1363_read_raw,
1002 .update_scan_mode = &max1363_update_scan_mode,
1003 .driver_module = THIS_MODULE,
1004 .event_attrs = &max1363_event_attribute_group,
1005};
1006
1007/* max1363 and max1368 tested - rest from data sheet */
1008static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1009 [max1361] = {
1010 .bits = 10,
1011 .int_vref_mv = 2048,
1012 .mode_list = max1363_mode_list,
1013 .num_modes = ARRAY_SIZE(max1363_mode_list),
1014 .default_mode = s0to3,
1015 .channels = max1361_channels,
1016 .num_channels = ARRAY_SIZE(max1361_channels),
1017 .info = &max1363_info,
1018 },
1019 [max1362] = {
1020 .bits = 10,
1021 .int_vref_mv = 4096,
1022 .mode_list = max1363_mode_list,
1023 .num_modes = ARRAY_SIZE(max1363_mode_list),
1024 .default_mode = s0to3,
1025 .channels = max1361_channels,
1026 .num_channels = ARRAY_SIZE(max1361_channels),
1027 .info = &max1363_info,
1028 },
1029 [max1363] = {
1030 .bits = 12,
1031 .int_vref_mv = 2048,
1032 .mode_list = max1363_mode_list,
1033 .num_modes = ARRAY_SIZE(max1363_mode_list),
1034 .default_mode = s0to3,
1035 .channels = max1363_channels,
1036 .num_channels = ARRAY_SIZE(max1363_channels),
1037 .info = &max1363_info,
1038 },
1039 [max1364] = {
1040 .bits = 12,
1041 .int_vref_mv = 4096,
1042 .mode_list = max1363_mode_list,
1043 .num_modes = ARRAY_SIZE(max1363_mode_list),
1044 .default_mode = s0to3,
1045 .channels = max1363_channels,
1046 .num_channels = ARRAY_SIZE(max1363_channels),
1047 .info = &max1363_info,
1048 },
1049 [max1036] = {
1050 .bits = 8,
1051 .int_vref_mv = 4096,
1052 .mode_list = max1236_mode_list,
1053 .num_modes = ARRAY_SIZE(max1236_mode_list),
1054 .default_mode = s0to3,
1055 .info = &max1238_info,
1056 .channels = max1036_channels,
1057 .num_channels = ARRAY_SIZE(max1036_channels),
1058 },
1059 [max1037] = {
1060 .bits = 8,
1061 .int_vref_mv = 2048,
1062 .mode_list = max1236_mode_list,
1063 .num_modes = ARRAY_SIZE(max1236_mode_list),
1064 .default_mode = s0to3,
1065 .info = &max1238_info,
1066 .channels = max1036_channels,
1067 .num_channels = ARRAY_SIZE(max1036_channels),
1068 },
1069 [max1038] = {
1070 .bits = 8,
1071 .int_vref_mv = 4096,
1072 .mode_list = max1238_mode_list,
1073 .num_modes = ARRAY_SIZE(max1238_mode_list),
1074 .default_mode = s0to11,
1075 .info = &max1238_info,
1076 .channels = max1038_channels,
1077 .num_channels = ARRAY_SIZE(max1038_channels),
1078 },
1079 [max1039] = {
1080 .bits = 8,
1081 .int_vref_mv = 2048,
1082 .mode_list = max1238_mode_list,
1083 .num_modes = ARRAY_SIZE(max1238_mode_list),
1084 .default_mode = s0to11,
1085 .info = &max1238_info,
1086 .channels = max1038_channels,
1087 .num_channels = ARRAY_SIZE(max1038_channels),
1088 },
1089 [max1136] = {
1090 .bits = 10,
1091 .int_vref_mv = 4096,
1092 .mode_list = max1236_mode_list,
1093 .num_modes = ARRAY_SIZE(max1236_mode_list),
1094 .default_mode = s0to3,
1095 .info = &max1238_info,
1096 .channels = max1136_channels,
1097 .num_channels = ARRAY_SIZE(max1136_channels),
1098 },
1099 [max1137] = {
1100 .bits = 10,
1101 .int_vref_mv = 2048,
1102 .mode_list = max1236_mode_list,
1103 .num_modes = ARRAY_SIZE(max1236_mode_list),
1104 .default_mode = s0to3,
1105 .info = &max1238_info,
1106 .channels = max1136_channels,
1107 .num_channels = ARRAY_SIZE(max1136_channels),
1108 },
1109 [max1138] = {
1110 .bits = 10,
1111 .int_vref_mv = 4096,
1112 .mode_list = max1238_mode_list,
1113 .num_modes = ARRAY_SIZE(max1238_mode_list),
1114 .default_mode = s0to11,
1115 .info = &max1238_info,
1116 .channels = max1138_channels,
1117 .num_channels = ARRAY_SIZE(max1138_channels),
1118 },
1119 [max1139] = {
1120 .bits = 10,
1121 .int_vref_mv = 2048,
1122 .mode_list = max1238_mode_list,
1123 .num_modes = ARRAY_SIZE(max1238_mode_list),
1124 .default_mode = s0to11,
1125 .info = &max1238_info,
1126 .channels = max1138_channels,
1127 .num_channels = ARRAY_SIZE(max1138_channels),
1128 },
1129 [max1236] = {
1130 .bits = 12,
1131 .int_vref_mv = 4096,
1132 .mode_list = max1236_mode_list,
1133 .num_modes = ARRAY_SIZE(max1236_mode_list),
1134 .default_mode = s0to3,
1135 .info = &max1238_info,
1136 .channels = max1236_channels,
1137 .num_channels = ARRAY_SIZE(max1236_channels),
1138 },
1139 [max1237] = {
1140 .bits = 12,
1141 .int_vref_mv = 2048,
1142 .mode_list = max1236_mode_list,
1143 .num_modes = ARRAY_SIZE(max1236_mode_list),
1144 .default_mode = s0to3,
1145 .info = &max1238_info,
1146 .channels = max1236_channels,
1147 .num_channels = ARRAY_SIZE(max1236_channels),
1148 },
1149 [max1238] = {
1150 .bits = 12,
1151 .int_vref_mv = 4096,
1152 .mode_list = max1238_mode_list,
1153 .num_modes = ARRAY_SIZE(max1238_mode_list),
1154 .default_mode = s0to11,
1155 .info = &max1238_info,
1156 .channels = max1238_channels,
1157 .num_channels = ARRAY_SIZE(max1238_channels),
1158 },
1159 [max1239] = {
1160 .bits = 12,
1161 .int_vref_mv = 2048,
1162 .mode_list = max1238_mode_list,
1163 .num_modes = ARRAY_SIZE(max1238_mode_list),
1164 .default_mode = s0to11,
1165 .info = &max1238_info,
1166 .channels = max1238_channels,
1167 .num_channels = ARRAY_SIZE(max1238_channels),
1168 },
1169 [max11600] = {
1170 .bits = 8,
1171 .int_vref_mv = 4096,
1172 .mode_list = max11607_mode_list,
1173 .num_modes = ARRAY_SIZE(max11607_mode_list),
1174 .default_mode = s0to3,
1175 .info = &max1238_info,
1176 .channels = max1036_channels,
1177 .num_channels = ARRAY_SIZE(max1036_channels),
1178 },
1179 [max11601] = {
1180 .bits = 8,
1181 .int_vref_mv = 2048,
1182 .mode_list = max11607_mode_list,
1183 .num_modes = ARRAY_SIZE(max11607_mode_list),
1184 .default_mode = s0to3,
1185 .info = &max1238_info,
1186 .channels = max1036_channels,
1187 .num_channels = ARRAY_SIZE(max1036_channels),
1188 },
1189 [max11602] = {
1190 .bits = 8,
1191 .int_vref_mv = 4096,
1192 .mode_list = max11608_mode_list,
1193 .num_modes = ARRAY_SIZE(max11608_mode_list),
1194 .default_mode = s0to7,
1195 .info = &max1238_info,
1196 .channels = max11602_channels,
1197 .num_channels = ARRAY_SIZE(max11602_channels),
1198 },
1199 [max11603] = {
1200 .bits = 8,
1201 .int_vref_mv = 2048,
1202 .mode_list = max11608_mode_list,
1203 .num_modes = ARRAY_SIZE(max11608_mode_list),
1204 .default_mode = s0to7,
1205 .info = &max1238_info,
1206 .channels = max11602_channels,
1207 .num_channels = ARRAY_SIZE(max11602_channels),
1208 },
1209 [max11604] = {
1210 .bits = 8,
1211 .int_vref_mv = 4098,
1212 .mode_list = max1238_mode_list,
1213 .num_modes = ARRAY_SIZE(max1238_mode_list),
1214 .default_mode = s0to11,
1215 .info = &max1238_info,
1216 .channels = max1238_channels,
1217 .num_channels = ARRAY_SIZE(max1238_channels),
1218 },
1219 [max11605] = {
1220 .bits = 8,
1221 .int_vref_mv = 2048,
1222 .mode_list = max1238_mode_list,
1223 .num_modes = ARRAY_SIZE(max1238_mode_list),
1224 .default_mode = s0to11,
1225 .info = &max1238_info,
1226 .channels = max1238_channels,
1227 .num_channels = ARRAY_SIZE(max1238_channels),
1228 },
1229 [max11606] = {
1230 .bits = 10,
1231 .int_vref_mv = 4096,
1232 .mode_list = max11607_mode_list,
1233 .num_modes = ARRAY_SIZE(max11607_mode_list),
1234 .default_mode = s0to3,
1235 .info = &max1238_info,
1236 .channels = max1136_channels,
1237 .num_channels = ARRAY_SIZE(max1136_channels),
1238 },
1239 [max11607] = {
1240 .bits = 10,
1241 .int_vref_mv = 2048,
1242 .mode_list = max11607_mode_list,
1243 .num_modes = ARRAY_SIZE(max11607_mode_list),
1244 .default_mode = s0to3,
1245 .info = &max1238_info,
1246 .channels = max1136_channels,
1247 .num_channels = ARRAY_SIZE(max1136_channels),
1248 },
1249 [max11608] = {
1250 .bits = 10,
1251 .int_vref_mv = 4096,
1252 .mode_list = max11608_mode_list,
1253 .num_modes = ARRAY_SIZE(max11608_mode_list),
1254 .default_mode = s0to7,
1255 .info = &max1238_info,
1256 .channels = max11608_channels,
1257 .num_channels = ARRAY_SIZE(max11608_channels),
1258 },
1259 [max11609] = {
1260 .bits = 10,
1261 .int_vref_mv = 2048,
1262 .mode_list = max11608_mode_list,
1263 .num_modes = ARRAY_SIZE(max11608_mode_list),
1264 .default_mode = s0to7,
1265 .info = &max1238_info,
1266 .channels = max11608_channels,
1267 .num_channels = ARRAY_SIZE(max11608_channels),
1268 },
1269 [max11610] = {
1270 .bits = 10,
1271 .int_vref_mv = 4098,
1272 .mode_list = max1238_mode_list,
1273 .num_modes = ARRAY_SIZE(max1238_mode_list),
1274 .default_mode = s0to11,
1275 .info = &max1238_info,
1276 .channels = max1238_channels,
1277 .num_channels = ARRAY_SIZE(max1238_channels),
1278 },
1279 [max11611] = {
1280 .bits = 10,
1281 .int_vref_mv = 2048,
1282 .mode_list = max1238_mode_list,
1283 .num_modes = ARRAY_SIZE(max1238_mode_list),
1284 .default_mode = s0to11,
1285 .info = &max1238_info,
1286 .channels = max1238_channels,
1287 .num_channels = ARRAY_SIZE(max1238_channels),
1288 },
1289 [max11612] = {
1290 .bits = 12,
1291 .int_vref_mv = 4096,
1292 .mode_list = max11607_mode_list,
1293 .num_modes = ARRAY_SIZE(max11607_mode_list),
1294 .default_mode = s0to3,
1295 .info = &max1238_info,
1296 .channels = max1363_channels,
1297 .num_channels = ARRAY_SIZE(max1363_channels),
1298 },
1299 [max11613] = {
1300 .bits = 12,
1301 .int_vref_mv = 2048,
1302 .mode_list = max11607_mode_list,
1303 .num_modes = ARRAY_SIZE(max11607_mode_list),
1304 .default_mode = s0to3,
1305 .info = &max1238_info,
1306 .channels = max1363_channels,
1307 .num_channels = ARRAY_SIZE(max1363_channels),
1308 },
1309 [max11614] = {
1310 .bits = 12,
1311 .int_vref_mv = 4096,
1312 .mode_list = max11608_mode_list,
1313 .num_modes = ARRAY_SIZE(max11608_mode_list),
1314 .default_mode = s0to7,
1315 .info = &max1238_info,
1316 .channels = max11614_channels,
1317 .num_channels = ARRAY_SIZE(max11614_channels),
1318 },
1319 [max11615] = {
1320 .bits = 12,
1321 .int_vref_mv = 2048,
1322 .mode_list = max11608_mode_list,
1323 .num_modes = ARRAY_SIZE(max11608_mode_list),
1324 .default_mode = s0to7,
1325 .info = &max1238_info,
1326 .channels = max11614_channels,
1327 .num_channels = ARRAY_SIZE(max11614_channels),
1328 },
1329 [max11616] = {
1330 .bits = 12,
1331 .int_vref_mv = 4098,
1332 .mode_list = max1238_mode_list,
1333 .num_modes = ARRAY_SIZE(max1238_mode_list),
1334 .default_mode = s0to11,
1335 .info = &max1238_info,
1336 .channels = max1238_channels,
1337 .num_channels = ARRAY_SIZE(max1238_channels),
1338 },
1339 [max11617] = {
1340 .bits = 12,
1341 .int_vref_mv = 2048,
1342 .mode_list = max1238_mode_list,
1343 .num_modes = ARRAY_SIZE(max1238_mode_list),
1344 .default_mode = s0to11,
1345 .info = &max1238_info,
1346 .channels = max1238_channels,
1347 .num_channels = ARRAY_SIZE(max1238_channels),
1348 },
1349 [max11644] = {
1350 .bits = 12,
1351 .int_vref_mv = 2048,
1352 .mode_list = max11644_mode_list,
1353 .num_modes = ARRAY_SIZE(max11644_mode_list),
1354 .default_mode = s0to1,
1355 .info = &max1238_info,
1356 .channels = max11644_channels,
1357 .num_channels = ARRAY_SIZE(max11644_channels),
1358 },
1359 [max11645] = {
1360 .bits = 12,
1361 .int_vref_mv = 4096,
1362 .mode_list = max11644_mode_list,
1363 .num_modes = ARRAY_SIZE(max11644_mode_list),
1364 .default_mode = s0to1,
1365 .info = &max1238_info,
1366 .channels = max11644_channels,
1367 .num_channels = ARRAY_SIZE(max11644_channels),
1368 },
1369 [max11646] = {
1370 .bits = 10,
1371 .int_vref_mv = 2048,
1372 .mode_list = max11644_mode_list,
1373 .num_modes = ARRAY_SIZE(max11644_mode_list),
1374 .default_mode = s0to1,
1375 .info = &max1238_info,
1376 .channels = max11646_channels,
1377 .num_channels = ARRAY_SIZE(max11646_channels),
1378 },
1379 [max11647] = {
1380 .bits = 10,
1381 .int_vref_mv = 4096,
1382 .mode_list = max11644_mode_list,
1383 .num_modes = ARRAY_SIZE(max11644_mode_list),
1384 .default_mode = s0to1,
1385 .info = &max1238_info,
1386 .channels = max11646_channels,
1387 .num_channels = ARRAY_SIZE(max11646_channels),
1388 },
1389};
1390
1391static int max1363_initial_setup(struct max1363_state *st)
1392{
1393 st->setupbyte = MAX1363_SETUP_INT_CLOCK
1394 | MAX1363_SETUP_UNIPOLAR
1395 | MAX1363_SETUP_NORESET;
1396
1397 if (st->vref)
1398 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
1399 else
1400 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
1401 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
1402
1403 /* Set scan mode writes the config anyway so wait until then */
1404 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1405 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1406 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1407
1408 return max1363_set_scan_mode(st);
1409}
1410
1411static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
1412{
1413 struct max1363_state *st = iio_priv(indio_dev);
1414 unsigned long *masks;
1415 int i;
1416
1417 masks = devm_kzalloc(&indio_dev->dev,
1418 BITS_TO_LONGS(MAX1363_MAX_CHANNELS) * sizeof(long) *
1419 (st->chip_info->num_modes + 1), GFP_KERNEL);
1420 if (!masks)
1421 return -ENOMEM;
1422
1423 for (i = 0; i < st->chip_info->num_modes; i++)
1424 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1425 max1363_mode_table[st->chip_info->mode_list[i]]
1426 .modemask, MAX1363_MAX_CHANNELS);
1427
1428 indio_dev->available_scan_masks = masks;
1429
1430 return 0;
1431}
1432
1433static irqreturn_t max1363_trigger_handler(int irq, void *p)
1434{
1435 struct iio_poll_func *pf = p;
1436 struct iio_dev *indio_dev = pf->indio_dev;
1437 struct max1363_state *st = iio_priv(indio_dev);
1438 s64 time_ns;
1439 __u8 *rxbuf;
1440 int b_sent;
1441 size_t d_size;
1442 unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1443 MAX1363_MAX_CHANNELS);
1444
1445 /* Ensure the timestamp is 8 byte aligned */
1446 if (st->chip_info->bits != 8)
1447 d_size = numvals*2;
1448 else
1449 d_size = numvals;
1450 if (indio_dev->scan_timestamp) {
1451 d_size += sizeof(s64);
1452 if (d_size % sizeof(s64))
1453 d_size += sizeof(s64) - (d_size % sizeof(s64));
1454 }
1455 /* Monitor mode prevents reading. Whilst not currently implemented
1456 * might as well have this test in here in the meantime as it does
1457 * no harm.
1458 */
1459 if (numvals == 0)
1460 goto done;
1461
1462 rxbuf = kmalloc(d_size, GFP_KERNEL);
1463 if (rxbuf == NULL)
1464 goto done;
1465 if (st->chip_info->bits != 8)
1466 b_sent = i2c_master_recv(st->client, rxbuf, numvals*2);
1467 else
1468 b_sent = i2c_master_recv(st->client, rxbuf, numvals);
1469 if (b_sent < 0)
1470 goto done_free;
1471
1472 time_ns = iio_get_time_ns();
1473
1474 if (indio_dev->scan_timestamp)
1475 memcpy(rxbuf + d_size - sizeof(s64), &time_ns, sizeof(time_ns));
1476 iio_push_to_buffers(indio_dev, rxbuf);
1477
1478done_free:
1479 kfree(rxbuf);
1480done:
1481 iio_trigger_notify_done(indio_dev->trig);
1482
1483 return IRQ_HANDLED;
1484}
1485
1486static const struct iio_buffer_setup_ops max1363_buffered_setup_ops = {
1487 .postenable = &iio_triggered_buffer_postenable,
1488 .preenable = &iio_sw_buffer_preenable,
1489 .predisable = &iio_triggered_buffer_predisable,
1490};
1491
1492static int max1363_probe(struct i2c_client *client,
1493 const struct i2c_device_id *id)
1494{
1495 int ret;
1496 struct max1363_state *st;
1497 struct iio_dev *indio_dev;
1498 struct regulator *vref;
1499
1500 indio_dev = iio_device_alloc(sizeof(struct max1363_state));
1501 if (indio_dev == NULL) {
1502 ret = -ENOMEM;
1503 goto error_out;
1504 }
1505
1506 indio_dev->dev.of_node = client->dev.of_node;
1507 ret = iio_map_array_register(indio_dev, client->dev.platform_data);
1508 if (ret < 0)
1509 goto error_free_device;
1510
1511 st = iio_priv(indio_dev);
1512
1513 st->reg = devm_regulator_get(&client->dev, "vcc");
1514 if (IS_ERR(st->reg)) {
1515 ret = PTR_ERR(st->reg);
1516 goto error_unregister_map;
1517 }
1518
1519 ret = regulator_enable(st->reg);
1520 if (ret)
1521 goto error_unregister_map;
1522
1523 /* this is only used for device removal purposes */
1524 i2c_set_clientdata(client, indio_dev);
1525
1526 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1527 st->client = client;
1528
1529 st->vref_uv = st->chip_info->int_vref_mv * 1000;
1530 vref = devm_regulator_get(&client->dev, "vref");
1531 if (!IS_ERR(vref)) {
1532 int vref_uv;
1533
1534 ret = regulator_enable(vref);
1535 if (ret)
1536 goto error_disable_reg;
1537 st->vref = vref;
1538 vref_uv = regulator_get_voltage(vref);
1539 if (vref_uv <= 0) {
1540 ret = -EINVAL;
1541 goto error_disable_reg;
1542 }
1543 st->vref_uv = vref_uv;
1544 }
1545
1546 ret = max1363_alloc_scan_masks(indio_dev);
1547 if (ret)
1548 goto error_disable_reg;
1549
1550 /* Establish that the iio_dev is a child of the i2c device */
1551 indio_dev->dev.parent = &client->dev;
1552 indio_dev->name = id->name;
1553 indio_dev->channels = st->chip_info->channels;
1554 indio_dev->num_channels = st->chip_info->num_channels;
1555 indio_dev->info = st->chip_info->info;
1556 indio_dev->modes = INDIO_DIRECT_MODE;
1557 ret = max1363_initial_setup(st);
1558 if (ret < 0)
1559 goto error_disable_reg;
1560
1561 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1562 &max1363_trigger_handler, &max1363_buffered_setup_ops);
1563 if (ret)
1564 goto error_disable_reg;
1565
1566 if (client->irq) {
1567 ret = devm_request_threaded_irq(&client->dev, st->client->irq,
1568 NULL,
1569 &max1363_event_handler,
1570 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1571 "max1363_event",
1572 indio_dev);
1573
1574 if (ret)
1575 goto error_uninit_buffer;
1576 }
1577
1578 ret = iio_device_register(indio_dev);
1579 if (ret < 0)
1580 goto error_uninit_buffer;
1581
1582 return 0;
1583
1584error_uninit_buffer:
1585 iio_triggered_buffer_cleanup(indio_dev);
1586error_disable_reg:
1587 if (st->vref)
1588 regulator_disable(st->vref);
1589 regulator_disable(st->reg);
1590error_unregister_map:
1591 iio_map_array_unregister(indio_dev);
1592error_free_device:
1593 iio_device_free(indio_dev);
1594error_out:
1595 return ret;
1596}
1597
1598static int max1363_remove(struct i2c_client *client)
1599{
1600 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1601 struct max1363_state *st = iio_priv(indio_dev);
1602
1603 iio_device_unregister(indio_dev);
1604 iio_triggered_buffer_cleanup(indio_dev);
1605 if (st->vref)
1606 regulator_disable(st->vref);
1607 regulator_disable(st->reg);
1608 iio_map_array_unregister(indio_dev);
1609 iio_device_free(indio_dev);
1610
1611 return 0;
1612}
1613
1614static const struct i2c_device_id max1363_id[] = {
1615 { "max1361", max1361 },
1616 { "max1362", max1362 },
1617 { "max1363", max1363 },
1618 { "max1364", max1364 },
1619 { "max1036", max1036 },
1620 { "max1037", max1037 },
1621 { "max1038", max1038 },
1622 { "max1039", max1039 },
1623 { "max1136", max1136 },
1624 { "max1137", max1137 },
1625 { "max1138", max1138 },
1626 { "max1139", max1139 },
1627 { "max1236", max1236 },
1628 { "max1237", max1237 },
1629 { "max1238", max1238 },
1630 { "max1239", max1239 },
1631 { "max11600", max11600 },
1632 { "max11601", max11601 },
1633 { "max11602", max11602 },
1634 { "max11603", max11603 },
1635 { "max11604", max11604 },
1636 { "max11605", max11605 },
1637 { "max11606", max11606 },
1638 { "max11607", max11607 },
1639 { "max11608", max11608 },
1640 { "max11609", max11609 },
1641 { "max11610", max11610 },
1642 { "max11611", max11611 },
1643 { "max11612", max11612 },
1644 { "max11613", max11613 },
1645 { "max11614", max11614 },
1646 { "max11615", max11615 },
1647 { "max11616", max11616 },
1648 { "max11617", max11617 },
1649 {}
1650};
1651
1652MODULE_DEVICE_TABLE(i2c, max1363_id);
1653
1654static struct i2c_driver max1363_driver = {
1655 .driver = {
1656 .name = "max1363",
1657 },
1658 .probe = max1363_probe,
1659 .remove = max1363_remove,
1660 .id_table = max1363_id,
1661};
1662module_i2c_driver(max1363_driver);
1663
1664MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1665MODULE_DESCRIPTION("Maxim 1363 ADC");
1666MODULE_LICENSE("GPL v2");