tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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kernel / drivers / pinctrl / pinctrl-sunxi.c
at v3.9-rc3 1505 lines 45 kB view raw
1/* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13#include <linux/io.h> 14#include <linux/gpio.h> 15#include <linux/module.h> 16#include <linux/of.h> 17#include <linux/of_address.h> 18#include <linux/of_device.h> 19#include <linux/pinctrl/consumer.h> 20#include <linux/pinctrl/machine.h> 21#include <linux/pinctrl/pinctrl.h> 22#include <linux/pinctrl/pinconf-generic.h> 23#include <linux/pinctrl/pinmux.h> 24#include <linux/platform_device.h> 25#include <linux/slab.h> 26 27#include "core.h" 28#include "pinctrl-sunxi.h" 29 30static const struct sunxi_desc_pin sun4i_a10_pins[] = { 31 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, 32 SUNXI_FUNCTION(0x0, "gpio_in"), 33 SUNXI_FUNCTION(0x1, "gpio_out")), 34 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, 35 SUNXI_FUNCTION(0x0, "gpio_in"), 36 SUNXI_FUNCTION(0x1, "gpio_out")), 37 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, 38 SUNXI_FUNCTION(0x0, "gpio_in"), 39 SUNXI_FUNCTION(0x1, "gpio_out")), 40 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, 41 SUNXI_FUNCTION(0x0, "gpio_in"), 42 SUNXI_FUNCTION(0x1, "gpio_out")), 43 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, 44 SUNXI_FUNCTION(0x0, "gpio_in"), 45 SUNXI_FUNCTION(0x1, "gpio_out")), 46 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, 47 SUNXI_FUNCTION(0x0, "gpio_in"), 48 SUNXI_FUNCTION(0x1, "gpio_out")), 49 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, 50 SUNXI_FUNCTION(0x0, "gpio_in"), 51 SUNXI_FUNCTION(0x1, "gpio_out")), 52 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, 53 SUNXI_FUNCTION(0x0, "gpio_in"), 54 SUNXI_FUNCTION(0x1, "gpio_out")), 55 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, 56 SUNXI_FUNCTION(0x0, "gpio_in"), 57 SUNXI_FUNCTION(0x1, "gpio_out")), 58 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, 59 SUNXI_FUNCTION(0x0, "gpio_in"), 60 SUNXI_FUNCTION(0x1, "gpio_out")), 61 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, 62 SUNXI_FUNCTION(0x0, "gpio_in"), 63 SUNXI_FUNCTION(0x1, "gpio_out"), 64 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 65 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, 66 SUNXI_FUNCTION(0x0, "gpio_in"), 67 SUNXI_FUNCTION(0x1, "gpio_out"), 68 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 69 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, 70 SUNXI_FUNCTION(0x0, "gpio_in"), 71 SUNXI_FUNCTION(0x1, "gpio_out"), 72 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ 73 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, 74 SUNXI_FUNCTION(0x0, "gpio_in"), 75 SUNXI_FUNCTION(0x1, "gpio_out"), 76 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ 77 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, 78 SUNXI_FUNCTION(0x0, "gpio_in"), 79 SUNXI_FUNCTION(0x1, "gpio_out"), 80 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ 81 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, 82 SUNXI_FUNCTION(0x0, "gpio_in"), 83 SUNXI_FUNCTION(0x1, "gpio_out"), 84 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ 85 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, 86 SUNXI_FUNCTION(0x0, "gpio_in"), 87 SUNXI_FUNCTION(0x1, "gpio_out"), 88 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ 89 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, 90 SUNXI_FUNCTION(0x0, "gpio_in"), 91 SUNXI_FUNCTION(0x1, "gpio_out"), 92 SUNXI_FUNCTION(0x4, "uart1")), /* RING */ 93 /* Hole */ 94 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, 95 SUNXI_FUNCTION(0x0, "gpio_in"), 96 SUNXI_FUNCTION(0x1, "gpio_out")), 97 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, 98 SUNXI_FUNCTION(0x0, "gpio_in"), 99 SUNXI_FUNCTION(0x1, "gpio_out")), 100 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, 101 SUNXI_FUNCTION(0x0, "gpio_in"), 102 SUNXI_FUNCTION(0x1, "gpio_out")), 103 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, 104 SUNXI_FUNCTION(0x0, "gpio_in"), 105 SUNXI_FUNCTION(0x1, "gpio_out")), 106 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, 107 SUNXI_FUNCTION(0x0, "gpio_in"), 108 SUNXI_FUNCTION(0x1, "gpio_out")), 109 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, 110 SUNXI_FUNCTION(0x0, "gpio_in"), 111 SUNXI_FUNCTION(0x1, "gpio_out")), 112 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, 113 SUNXI_FUNCTION(0x0, "gpio_in"), 114 SUNXI_FUNCTION(0x1, "gpio_out")), 115 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, 116 SUNXI_FUNCTION(0x0, "gpio_in"), 117 SUNXI_FUNCTION(0x1, "gpio_out")), 118 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, 119 SUNXI_FUNCTION(0x0, "gpio_in"), 120 SUNXI_FUNCTION(0x1, "gpio_out")), 121 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, 122 SUNXI_FUNCTION(0x0, "gpio_in"), 123 SUNXI_FUNCTION(0x1, "gpio_out")), 124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, 125 SUNXI_FUNCTION(0x0, "gpio_in"), 126 SUNXI_FUNCTION(0x1, "gpio_out")), 127 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, 128 SUNXI_FUNCTION(0x0, "gpio_in"), 129 SUNXI_FUNCTION(0x1, "gpio_out")), 130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, 131 SUNXI_FUNCTION(0x0, "gpio_in"), 132 SUNXI_FUNCTION(0x1, "gpio_out")), 133 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, 134 SUNXI_FUNCTION(0x0, "gpio_in"), 135 SUNXI_FUNCTION(0x1, "gpio_out")), 136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, 137 SUNXI_FUNCTION(0x0, "gpio_in"), 138 SUNXI_FUNCTION(0x1, "gpio_out")), 139 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, 140 SUNXI_FUNCTION(0x0, "gpio_in"), 141 SUNXI_FUNCTION(0x1, "gpio_out")), 142 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, 143 SUNXI_FUNCTION(0x0, "gpio_in"), 144 SUNXI_FUNCTION(0x1, "gpio_out")), 145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, 146 SUNXI_FUNCTION(0x0, "gpio_in"), 147 SUNXI_FUNCTION(0x1, "gpio_out")), 148 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, 149 SUNXI_FUNCTION(0x0, "gpio_in"), 150 SUNXI_FUNCTION(0x1, "gpio_out")), 151 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, 152 SUNXI_FUNCTION(0x0, "gpio_in"), 153 SUNXI_FUNCTION(0x1, "gpio_out")), 154 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, 155 SUNXI_FUNCTION(0x0, "gpio_in"), 156 SUNXI_FUNCTION(0x1, "gpio_out")), 157 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21, 158 SUNXI_FUNCTION(0x0, "gpio_in"), 159 SUNXI_FUNCTION(0x1, "gpio_out")), 160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22, 161 SUNXI_FUNCTION(0x0, "gpio_in"), 162 SUNXI_FUNCTION(0x1, "gpio_out"), 163 SUNXI_FUNCTION(0x2, "uart0")), /* TX */ 164 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23, 165 SUNXI_FUNCTION(0x0, "gpio_in"), 166 SUNXI_FUNCTION(0x1, "gpio_out"), 167 SUNXI_FUNCTION(0x2, "uart0")), /* RX */ 168 /* Hole */ 169 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, 170 SUNXI_FUNCTION(0x0, "gpio_in"), 171 SUNXI_FUNCTION(0x1, "gpio_out")), 172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, 173 SUNXI_FUNCTION(0x0, "gpio_in"), 174 SUNXI_FUNCTION(0x1, "gpio_out")), 175 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, 176 SUNXI_FUNCTION(0x0, "gpio_in"), 177 SUNXI_FUNCTION(0x1, "gpio_out")), 178 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, 179 SUNXI_FUNCTION(0x0, "gpio_in"), 180 SUNXI_FUNCTION(0x1, "gpio_out")), 181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, 182 SUNXI_FUNCTION(0x0, "gpio_in"), 183 SUNXI_FUNCTION(0x1, "gpio_out")), 184 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, 185 SUNXI_FUNCTION(0x0, "gpio_in"), 186 SUNXI_FUNCTION(0x1, "gpio_out")), 187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, 188 SUNXI_FUNCTION(0x0, "gpio_in"), 189 SUNXI_FUNCTION(0x1, "gpio_out")), 190 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, 191 SUNXI_FUNCTION(0x0, "gpio_in"), 192 SUNXI_FUNCTION(0x1, "gpio_out")), 193 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, 194 SUNXI_FUNCTION(0x0, "gpio_in"), 195 SUNXI_FUNCTION(0x1, "gpio_out")), 196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, 197 SUNXI_FUNCTION(0x0, "gpio_in"), 198 SUNXI_FUNCTION(0x1, "gpio_out")), 199 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, 200 SUNXI_FUNCTION(0x0, "gpio_in"), 201 SUNXI_FUNCTION(0x1, "gpio_out")), 202 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, 203 SUNXI_FUNCTION(0x0, "gpio_in"), 204 SUNXI_FUNCTION(0x1, "gpio_out")), 205 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, 206 SUNXI_FUNCTION(0x0, "gpio_in"), 207 SUNXI_FUNCTION(0x1, "gpio_out")), 208 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, 209 SUNXI_FUNCTION(0x0, "gpio_in"), 210 SUNXI_FUNCTION(0x1, "gpio_out")), 211 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, 212 SUNXI_FUNCTION(0x0, "gpio_in"), 213 SUNXI_FUNCTION(0x1, "gpio_out")), 214 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, 215 SUNXI_FUNCTION(0x0, "gpio_in"), 216 SUNXI_FUNCTION(0x1, "gpio_out")), 217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, 218 SUNXI_FUNCTION(0x0, "gpio_in"), 219 SUNXI_FUNCTION(0x1, "gpio_out")), 220 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, 221 SUNXI_FUNCTION(0x0, "gpio_in"), 222 SUNXI_FUNCTION(0x1, "gpio_out")), 223 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, 224 SUNXI_FUNCTION(0x0, "gpio_in"), 225 SUNXI_FUNCTION(0x1, "gpio_out")), 226 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, 227 SUNXI_FUNCTION(0x0, "gpio_in"), 228 SUNXI_FUNCTION(0x1, "gpio_out")), 229 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20, 230 SUNXI_FUNCTION(0x0, "gpio_in"), 231 SUNXI_FUNCTION(0x1, "gpio_out")), 232 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21, 233 SUNXI_FUNCTION(0x0, "gpio_in"), 234 SUNXI_FUNCTION(0x1, "gpio_out")), 235 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22, 236 SUNXI_FUNCTION(0x0, "gpio_in"), 237 SUNXI_FUNCTION(0x1, "gpio_out")), 238 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23, 239 SUNXI_FUNCTION(0x0, "gpio_in"), 240 SUNXI_FUNCTION(0x1, "gpio_out")), 241 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24, 242 SUNXI_FUNCTION(0x0, "gpio_in"), 243 SUNXI_FUNCTION(0x1, "gpio_out")), 244 /* Hole */ 245 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, 246 SUNXI_FUNCTION(0x0, "gpio_in"), 247 SUNXI_FUNCTION(0x1, "gpio_out")), 248 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, 249 SUNXI_FUNCTION(0x0, "gpio_in"), 250 SUNXI_FUNCTION(0x1, "gpio_out")), 251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, 252 SUNXI_FUNCTION(0x0, "gpio_in"), 253 SUNXI_FUNCTION(0x1, "gpio_out")), 254 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, 255 SUNXI_FUNCTION(0x0, "gpio_in"), 256 SUNXI_FUNCTION(0x1, "gpio_out")), 257 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, 258 SUNXI_FUNCTION(0x0, "gpio_in"), 259 SUNXI_FUNCTION(0x1, "gpio_out")), 260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, 261 SUNXI_FUNCTION(0x0, "gpio_in"), 262 SUNXI_FUNCTION(0x1, "gpio_out")), 263 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, 264 SUNXI_FUNCTION(0x0, "gpio_in"), 265 SUNXI_FUNCTION(0x1, "gpio_out")), 266 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, 267 SUNXI_FUNCTION(0x0, "gpio_in"), 268 SUNXI_FUNCTION(0x1, "gpio_out")), 269 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, 270 SUNXI_FUNCTION(0x0, "gpio_in"), 271 SUNXI_FUNCTION(0x1, "gpio_out")), 272 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, 273 SUNXI_FUNCTION(0x0, "gpio_in"), 274 SUNXI_FUNCTION(0x1, "gpio_out")), 275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, 276 SUNXI_FUNCTION(0x0, "gpio_in"), 277 SUNXI_FUNCTION(0x1, "gpio_out")), 278 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, 279 SUNXI_FUNCTION(0x0, "gpio_in"), 280 SUNXI_FUNCTION(0x1, "gpio_out")), 281 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, 282 SUNXI_FUNCTION(0x0, "gpio_in"), 283 SUNXI_FUNCTION(0x1, "gpio_out")), 284 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, 285 SUNXI_FUNCTION(0x0, "gpio_in"), 286 SUNXI_FUNCTION(0x1, "gpio_out")), 287 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, 288 SUNXI_FUNCTION(0x0, "gpio_in"), 289 SUNXI_FUNCTION(0x1, "gpio_out")), 290 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, 291 SUNXI_FUNCTION(0x0, "gpio_in"), 292 SUNXI_FUNCTION(0x1, "gpio_out")), 293 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, 294 SUNXI_FUNCTION(0x0, "gpio_in"), 295 SUNXI_FUNCTION(0x1, "gpio_out")), 296 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, 297 SUNXI_FUNCTION(0x0, "gpio_in"), 298 SUNXI_FUNCTION(0x1, "gpio_out")), 299 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, 300 SUNXI_FUNCTION(0x0, "gpio_in"), 301 SUNXI_FUNCTION(0x1, "gpio_out")), 302 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, 303 SUNXI_FUNCTION(0x0, "gpio_in"), 304 SUNXI_FUNCTION(0x1, "gpio_out")), 305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, 306 SUNXI_FUNCTION(0x0, "gpio_in"), 307 SUNXI_FUNCTION(0x1, "gpio_out")), 308 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, 309 SUNXI_FUNCTION(0x0, "gpio_in"), 310 SUNXI_FUNCTION(0x1, "gpio_out")), 311 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, 312 SUNXI_FUNCTION(0x0, "gpio_in"), 313 SUNXI_FUNCTION(0x1, "gpio_out")), 314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, 315 SUNXI_FUNCTION(0x0, "gpio_in"), 316 SUNXI_FUNCTION(0x1, "gpio_out")), 317 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, 318 SUNXI_FUNCTION(0x0, "gpio_in"), 319 SUNXI_FUNCTION(0x1, "gpio_out")), 320 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, 321 SUNXI_FUNCTION(0x0, "gpio_in"), 322 SUNXI_FUNCTION(0x1, "gpio_out")), 323 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, 324 SUNXI_FUNCTION(0x0, "gpio_in"), 325 SUNXI_FUNCTION(0x1, "gpio_out")), 326 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, 327 SUNXI_FUNCTION(0x0, "gpio_in"), 328 SUNXI_FUNCTION(0x1, "gpio_out")), 329 /* Hole */ 330 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, 331 SUNXI_FUNCTION(0x0, "gpio_in"), 332 SUNXI_FUNCTION(0x1, "gpio_out")), 333 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, 334 SUNXI_FUNCTION(0x0, "gpio_in"), 335 SUNXI_FUNCTION(0x1, "gpio_out")), 336 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, 337 SUNXI_FUNCTION(0x0, "gpio_in"), 338 SUNXI_FUNCTION(0x1, "gpio_out")), 339 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, 340 SUNXI_FUNCTION(0x0, "gpio_in"), 341 SUNXI_FUNCTION(0x1, "gpio_out")), 342 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, 343 SUNXI_FUNCTION(0x0, "gpio_in"), 344 SUNXI_FUNCTION(0x1, "gpio_out")), 345 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, 346 SUNXI_FUNCTION(0x0, "gpio_in"), 347 SUNXI_FUNCTION(0x1, "gpio_out")), 348 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, 349 SUNXI_FUNCTION(0x0, "gpio_in"), 350 SUNXI_FUNCTION(0x1, "gpio_out")), 351 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, 352 SUNXI_FUNCTION(0x0, "gpio_in"), 353 SUNXI_FUNCTION(0x1, "gpio_out")), 354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, 355 SUNXI_FUNCTION(0x0, "gpio_in"), 356 SUNXI_FUNCTION(0x1, "gpio_out")), 357 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, 358 SUNXI_FUNCTION(0x0, "gpio_in"), 359 SUNXI_FUNCTION(0x1, "gpio_out")), 360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, 361 SUNXI_FUNCTION(0x0, "gpio_in"), 362 SUNXI_FUNCTION(0x1, "gpio_out")), 363 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, 364 SUNXI_FUNCTION(0x0, "gpio_in"), 365 SUNXI_FUNCTION(0x1, "gpio_out")), 366 /* Hole */ 367 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, 368 SUNXI_FUNCTION(0x0, "gpio_in"), 369 SUNXI_FUNCTION(0x1, "gpio_out")), 370 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, 371 SUNXI_FUNCTION(0x0, "gpio_in"), 372 SUNXI_FUNCTION(0x1, "gpio_out")), 373 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, 374 SUNXI_FUNCTION(0x0, "gpio_in"), 375 SUNXI_FUNCTION(0x1, "gpio_out"), 376 SUNXI_FUNCTION(0x4, "uart0")), /* TX */ 377 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, 378 SUNXI_FUNCTION(0x0, "gpio_in"), 379 SUNXI_FUNCTION(0x1, "gpio_out")), 380 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, 381 SUNXI_FUNCTION(0x0, "gpio_in"), 382 SUNXI_FUNCTION(0x1, "gpio_out"), 383 SUNXI_FUNCTION(0x4, "uart0")), /* RX */ 384 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, 385 SUNXI_FUNCTION(0x0, "gpio_in"), 386 SUNXI_FUNCTION(0x1, "gpio_out")), 387 /* Hole */ 388 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, 389 SUNXI_FUNCTION(0x0, "gpio_in"), 390 SUNXI_FUNCTION(0x1, "gpio_out")), 391 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, 392 SUNXI_FUNCTION(0x0, "gpio_in"), 393 SUNXI_FUNCTION(0x1, "gpio_out")), 394 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, 395 SUNXI_FUNCTION(0x0, "gpio_in"), 396 SUNXI_FUNCTION(0x1, "gpio_out")), 397 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, 398 SUNXI_FUNCTION(0x0, "gpio_in"), 399 SUNXI_FUNCTION(0x1, "gpio_out")), 400 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, 401 SUNXI_FUNCTION(0x0, "gpio_in"), 402 SUNXI_FUNCTION(0x1, "gpio_out")), 403 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, 404 SUNXI_FUNCTION(0x0, "gpio_in"), 405 SUNXI_FUNCTION(0x1, "gpio_out")), 406 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, 407 SUNXI_FUNCTION(0x0, "gpio_in"), 408 SUNXI_FUNCTION(0x1, "gpio_out")), 409 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, 410 SUNXI_FUNCTION(0x0, "gpio_in"), 411 SUNXI_FUNCTION(0x1, "gpio_out")), 412 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, 413 SUNXI_FUNCTION(0x0, "gpio_in"), 414 SUNXI_FUNCTION(0x1, "gpio_out")), 415 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, 416 SUNXI_FUNCTION(0x0, "gpio_in"), 417 SUNXI_FUNCTION(0x1, "gpio_out")), 418 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, 419 SUNXI_FUNCTION(0x0, "gpio_in"), 420 SUNXI_FUNCTION(0x1, "gpio_out")), 421 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, 422 SUNXI_FUNCTION(0x0, "gpio_in"), 423 SUNXI_FUNCTION(0x1, "gpio_out")), 424 /* Hole */ 425 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0, 426 SUNXI_FUNCTION(0x0, "gpio_in"), 427 SUNXI_FUNCTION(0x1, "gpio_out")), 428 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1, 429 SUNXI_FUNCTION(0x0, "gpio_in"), 430 SUNXI_FUNCTION(0x1, "gpio_out")), 431 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2, 432 SUNXI_FUNCTION(0x0, "gpio_in"), 433 SUNXI_FUNCTION(0x1, "gpio_out")), 434 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3, 435 SUNXI_FUNCTION(0x0, "gpio_in"), 436 SUNXI_FUNCTION(0x1, "gpio_out")), 437 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4, 438 SUNXI_FUNCTION(0x0, "gpio_in"), 439 SUNXI_FUNCTION(0x1, "gpio_out")), 440 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5, 441 SUNXI_FUNCTION(0x0, "gpio_in"), 442 SUNXI_FUNCTION(0x1, "gpio_out")), 443 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6, 444 SUNXI_FUNCTION(0x0, "gpio_in"), 445 SUNXI_FUNCTION(0x1, "gpio_out")), 446 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7, 447 SUNXI_FUNCTION(0x0, "gpio_in"), 448 SUNXI_FUNCTION(0x1, "gpio_out")), 449 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8, 450 SUNXI_FUNCTION(0x0, "gpio_in"), 451 SUNXI_FUNCTION(0x1, "gpio_out")), 452 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9, 453 SUNXI_FUNCTION(0x0, "gpio_in"), 454 SUNXI_FUNCTION(0x1, "gpio_out")), 455 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10, 456 SUNXI_FUNCTION(0x0, "gpio_in"), 457 SUNXI_FUNCTION(0x1, "gpio_out")), 458 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11, 459 SUNXI_FUNCTION(0x0, "gpio_in"), 460 SUNXI_FUNCTION(0x1, "gpio_out")), 461 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12, 462 SUNXI_FUNCTION(0x0, "gpio_in"), 463 SUNXI_FUNCTION(0x1, "gpio_out")), 464 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13, 465 SUNXI_FUNCTION(0x0, "gpio_in"), 466 SUNXI_FUNCTION(0x1, "gpio_out")), 467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14, 468 SUNXI_FUNCTION(0x0, "gpio_in"), 469 SUNXI_FUNCTION(0x1, "gpio_out")), 470 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15, 471 SUNXI_FUNCTION(0x0, "gpio_in"), 472 SUNXI_FUNCTION(0x1, "gpio_out")), 473 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16, 474 SUNXI_FUNCTION(0x0, "gpio_in"), 475 SUNXI_FUNCTION(0x1, "gpio_out")), 476 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17, 477 SUNXI_FUNCTION(0x0, "gpio_in"), 478 SUNXI_FUNCTION(0x1, "gpio_out")), 479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18, 480 SUNXI_FUNCTION(0x0, "gpio_in"), 481 SUNXI_FUNCTION(0x1, "gpio_out")), 482 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19, 483 SUNXI_FUNCTION(0x0, "gpio_in"), 484 SUNXI_FUNCTION(0x1, "gpio_out")), 485 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20, 486 SUNXI_FUNCTION(0x0, "gpio_in"), 487 SUNXI_FUNCTION(0x1, "gpio_out")), 488 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21, 489 SUNXI_FUNCTION(0x0, "gpio_in"), 490 SUNXI_FUNCTION(0x1, "gpio_out")), 491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22, 492 SUNXI_FUNCTION(0x0, "gpio_in"), 493 SUNXI_FUNCTION(0x1, "gpio_out")), 494 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23, 495 SUNXI_FUNCTION(0x0, "gpio_in"), 496 SUNXI_FUNCTION(0x1, "gpio_out")), 497 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24, 498 SUNXI_FUNCTION(0x0, "gpio_in"), 499 SUNXI_FUNCTION(0x1, "gpio_out")), 500 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25, 501 SUNXI_FUNCTION(0x0, "gpio_in"), 502 SUNXI_FUNCTION(0x1, "gpio_out")), 503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26, 504 SUNXI_FUNCTION(0x0, "gpio_in"), 505 SUNXI_FUNCTION(0x1, "gpio_out")), 506 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27, 507 SUNXI_FUNCTION(0x0, "gpio_in"), 508 SUNXI_FUNCTION(0x1, "gpio_out")), 509 /* Hole */ 510 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0, 511 SUNXI_FUNCTION(0x0, "gpio_in"), 512 SUNXI_FUNCTION(0x1, "gpio_out")), 513 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1, 514 SUNXI_FUNCTION(0x0, "gpio_in"), 515 SUNXI_FUNCTION(0x1, "gpio_out")), 516 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2, 517 SUNXI_FUNCTION(0x0, "gpio_in"), 518 SUNXI_FUNCTION(0x1, "gpio_out")), 519 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3, 520 SUNXI_FUNCTION(0x0, "gpio_in"), 521 SUNXI_FUNCTION(0x1, "gpio_out")), 522 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4, 523 SUNXI_FUNCTION(0x0, "gpio_in"), 524 SUNXI_FUNCTION(0x1, "gpio_out")), 525 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5, 526 SUNXI_FUNCTION(0x0, "gpio_in"), 527 SUNXI_FUNCTION(0x1, "gpio_out")), 528 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6, 529 SUNXI_FUNCTION(0x0, "gpio_in"), 530 SUNXI_FUNCTION(0x1, "gpio_out")), 531 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7, 532 SUNXI_FUNCTION(0x0, "gpio_in"), 533 SUNXI_FUNCTION(0x1, "gpio_out")), 534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8, 535 SUNXI_FUNCTION(0x0, "gpio_in"), 536 SUNXI_FUNCTION(0x1, "gpio_out")), 537 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9, 538 SUNXI_FUNCTION(0x0, "gpio_in"), 539 SUNXI_FUNCTION(0x1, "gpio_out")), 540 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10, 541 SUNXI_FUNCTION(0x0, "gpio_in"), 542 SUNXI_FUNCTION(0x1, "gpio_out")), 543 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11, 544 SUNXI_FUNCTION(0x0, "gpio_in"), 545 SUNXI_FUNCTION(0x1, "gpio_out")), 546 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12, 547 SUNXI_FUNCTION(0x0, "gpio_in"), 548 SUNXI_FUNCTION(0x1, "gpio_out")), 549 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13, 550 SUNXI_FUNCTION(0x0, "gpio_in"), 551 SUNXI_FUNCTION(0x1, "gpio_out")), 552 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14, 553 SUNXI_FUNCTION(0x0, "gpio_in"), 554 SUNXI_FUNCTION(0x1, "gpio_out")), 555 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15, 556 SUNXI_FUNCTION(0x0, "gpio_in"), 557 SUNXI_FUNCTION(0x1, "gpio_out")), 558 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16, 559 SUNXI_FUNCTION(0x0, "gpio_in"), 560 SUNXI_FUNCTION(0x1, "gpio_out")), 561 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17, 562 SUNXI_FUNCTION(0x0, "gpio_in"), 563 SUNXI_FUNCTION(0x1, "gpio_out")), 564 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18, 565 SUNXI_FUNCTION(0x0, "gpio_in"), 566 SUNXI_FUNCTION(0x1, "gpio_out")), 567 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19, 568 SUNXI_FUNCTION(0x0, "gpio_in"), 569 SUNXI_FUNCTION(0x1, "gpio_out")), 570 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20, 571 SUNXI_FUNCTION(0x0, "gpio_in"), 572 SUNXI_FUNCTION(0x1, "gpio_out")), 573 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21, 574 SUNXI_FUNCTION(0x0, "gpio_in"), 575 SUNXI_FUNCTION(0x1, "gpio_out")), 576}; 577 578static const struct sunxi_desc_pin sun5i_a13_pins[] = { 579 /* Hole */ 580 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, 581 SUNXI_FUNCTION(0x0, "gpio_in"), 582 SUNXI_FUNCTION(0x1, "gpio_out")), 583 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, 584 SUNXI_FUNCTION(0x0, "gpio_in"), 585 SUNXI_FUNCTION(0x1, "gpio_out")), 586 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, 587 SUNXI_FUNCTION(0x0, "gpio_in"), 588 SUNXI_FUNCTION(0x1, "gpio_out")), 589 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, 590 SUNXI_FUNCTION(0x0, "gpio_in"), 591 SUNXI_FUNCTION(0x1, "gpio_out")), 592 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, 593 SUNXI_FUNCTION(0x0, "gpio_in"), 594 SUNXI_FUNCTION(0x1, "gpio_out")), 595 /* Hole */ 596 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, 597 SUNXI_FUNCTION(0x0, "gpio_in"), 598 SUNXI_FUNCTION(0x1, "gpio_out")), 599 /* Hole */ 600 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, 601 SUNXI_FUNCTION(0x0, "gpio_in"), 602 SUNXI_FUNCTION(0x1, "gpio_out")), 603 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, 604 SUNXI_FUNCTION(0x0, "gpio_in"), 605 SUNXI_FUNCTION(0x1, "gpio_out")), 606 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, 607 SUNXI_FUNCTION(0x0, "gpio_in"), 608 SUNXI_FUNCTION(0x1, "gpio_out")), 609 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, 610 SUNXI_FUNCTION(0x0, "gpio_in"), 611 SUNXI_FUNCTION(0x1, "gpio_out")), 612 /* Hole */ 613 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, 614 SUNXI_FUNCTION(0x0, "gpio_in"), 615 SUNXI_FUNCTION(0x1, "gpio_out")), 616 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, 617 SUNXI_FUNCTION(0x0, "gpio_in"), 618 SUNXI_FUNCTION(0x1, "gpio_out")), 619 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, 620 SUNXI_FUNCTION(0x0, "gpio_in"), 621 SUNXI_FUNCTION(0x1, "gpio_out")), 622 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, 623 SUNXI_FUNCTION(0x0, "gpio_in"), 624 SUNXI_FUNCTION(0x1, "gpio_out")), 625 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, 626 SUNXI_FUNCTION(0x0, "gpio_in"), 627 SUNXI_FUNCTION(0x1, "gpio_out")), 628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, 629 SUNXI_FUNCTION(0x0, "gpio_in"), 630 SUNXI_FUNCTION(0x1, "gpio_out")), 631 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, 632 SUNXI_FUNCTION(0x0, "gpio_in"), 633 SUNXI_FUNCTION(0x1, "gpio_out")), 634 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, 635 SUNXI_FUNCTION(0x0, "gpio_in"), 636 SUNXI_FUNCTION(0x1, "gpio_out")), 637 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, 638 SUNXI_FUNCTION(0x0, "gpio_in"), 639 SUNXI_FUNCTION(0x1, "gpio_out")), 640 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, 641 SUNXI_FUNCTION(0x0, "gpio_in"), 642 SUNXI_FUNCTION(0x1, "gpio_out")), 643 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, 644 SUNXI_FUNCTION(0x0, "gpio_in"), 645 SUNXI_FUNCTION(0x1, "gpio_out")), 646 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, 647 SUNXI_FUNCTION(0x0, "gpio_in"), 648 SUNXI_FUNCTION(0x1, "gpio_out")), 649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, 650 SUNXI_FUNCTION(0x0, "gpio_in"), 651 SUNXI_FUNCTION(0x1, "gpio_out")), 652 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, 653 SUNXI_FUNCTION(0x0, "gpio_in"), 654 SUNXI_FUNCTION(0x1, "gpio_out")), 655 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, 656 SUNXI_FUNCTION(0x0, "gpio_in"), 657 SUNXI_FUNCTION(0x1, "gpio_out")), 658 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, 659 SUNXI_FUNCTION(0x0, "gpio_in"), 660 SUNXI_FUNCTION(0x1, "gpio_out")), 661 /* Hole */ 662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, 663 SUNXI_FUNCTION(0x0, "gpio_in"), 664 SUNXI_FUNCTION(0x1, "gpio_out")), 665 /* Hole */ 666 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, 667 SUNXI_FUNCTION(0x0, "gpio_in"), 668 SUNXI_FUNCTION(0x1, "gpio_out")), 669 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, 670 SUNXI_FUNCTION(0x0, "gpio_in"), 671 SUNXI_FUNCTION(0x1, "gpio_out")), 672 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, 673 SUNXI_FUNCTION(0x0, "gpio_in"), 674 SUNXI_FUNCTION(0x1, "gpio_out")), 675 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, 676 SUNXI_FUNCTION(0x0, "gpio_in"), 677 SUNXI_FUNCTION(0x1, "gpio_out")), 678 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, 679 SUNXI_FUNCTION(0x0, "gpio_in"), 680 SUNXI_FUNCTION(0x1, "gpio_out")), 681 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, 682 SUNXI_FUNCTION(0x0, "gpio_in"), 683 SUNXI_FUNCTION(0x1, "gpio_out")), 684 /* Hole */ 685 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, 686 SUNXI_FUNCTION(0x0, "gpio_in"), 687 SUNXI_FUNCTION(0x1, "gpio_out")), 688 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, 689 SUNXI_FUNCTION(0x0, "gpio_in"), 690 SUNXI_FUNCTION(0x1, "gpio_out")), 691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, 692 SUNXI_FUNCTION(0x0, "gpio_in"), 693 SUNXI_FUNCTION(0x1, "gpio_out")), 694 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, 695 SUNXI_FUNCTION(0x0, "gpio_in"), 696 SUNXI_FUNCTION(0x1, "gpio_out")), 697 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, 698 SUNXI_FUNCTION(0x0, "gpio_in"), 699 SUNXI_FUNCTION(0x1, "gpio_out")), 700 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, 701 SUNXI_FUNCTION(0x0, "gpio_in"), 702 SUNXI_FUNCTION(0x1, "gpio_out")), 703 /* Hole */ 704 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, 705 SUNXI_FUNCTION(0x0, "gpio_in"), 706 SUNXI_FUNCTION(0x1, "gpio_out")), 707 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, 708 SUNXI_FUNCTION(0x0, "gpio_in"), 709 SUNXI_FUNCTION(0x1, "gpio_out")), 710 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, 711 SUNXI_FUNCTION(0x0, "gpio_in"), 712 SUNXI_FUNCTION(0x1, "gpio_out")), 713 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, 714 SUNXI_FUNCTION(0x0, "gpio_in"), 715 SUNXI_FUNCTION(0x1, "gpio_out")), 716 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, 717 SUNXI_FUNCTION(0x0, "gpio_in"), 718 SUNXI_FUNCTION(0x1, "gpio_out")), 719 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, 720 SUNXI_FUNCTION(0x0, "gpio_in"), 721 SUNXI_FUNCTION(0x1, "gpio_out")), 722 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, 723 SUNXI_FUNCTION(0x0, "gpio_in"), 724 SUNXI_FUNCTION(0x1, "gpio_out")), 725 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, 726 SUNXI_FUNCTION(0x0, "gpio_in"), 727 SUNXI_FUNCTION(0x1, "gpio_out")), 728 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, 729 SUNXI_FUNCTION(0x0, "gpio_in"), 730 SUNXI_FUNCTION(0x1, "gpio_out")), 731 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, 732 SUNXI_FUNCTION(0x0, "gpio_in"), 733 SUNXI_FUNCTION(0x1, "gpio_out")), 734 /* Hole */ 735 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, 736 SUNXI_FUNCTION(0x0, "gpio_in"), 737 SUNXI_FUNCTION(0x1, "gpio_out")), 738 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, 739 SUNXI_FUNCTION(0x0, "gpio_in"), 740 SUNXI_FUNCTION(0x1, "gpio_out")), 741 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, 742 SUNXI_FUNCTION(0x0, "gpio_in"), 743 SUNXI_FUNCTION(0x1, "gpio_out")), 744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, 745 SUNXI_FUNCTION(0x0, "gpio_in"), 746 SUNXI_FUNCTION(0x1, "gpio_out")), 747 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, 748 SUNXI_FUNCTION(0x0, "gpio_in"), 749 SUNXI_FUNCTION(0x1, "gpio_out")), 750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, 751 SUNXI_FUNCTION(0x0, "gpio_in"), 752 SUNXI_FUNCTION(0x1, "gpio_out")), 753 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, 754 SUNXI_FUNCTION(0x0, "gpio_in"), 755 SUNXI_FUNCTION(0x1, "gpio_out")), 756 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, 757 SUNXI_FUNCTION(0x0, "gpio_in"), 758 SUNXI_FUNCTION(0x1, "gpio_out")), 759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, 760 SUNXI_FUNCTION(0x0, "gpio_in"), 761 SUNXI_FUNCTION(0x1, "gpio_out")), 762 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, 763 SUNXI_FUNCTION(0x0, "gpio_in"), 764 SUNXI_FUNCTION(0x1, "gpio_out")), 765 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, 766 SUNXI_FUNCTION(0x0, "gpio_in"), 767 SUNXI_FUNCTION(0x1, "gpio_out"), 768 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 769 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, 770 SUNXI_FUNCTION(0x0, "gpio_in"), 771 SUNXI_FUNCTION(0x1, "gpio_out"), 772 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 773 /* Hole */ 774 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, 775 SUNXI_FUNCTION(0x0, "gpio_in"), 776 SUNXI_FUNCTION(0x1, "gpio_out")), 777 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, 778 SUNXI_FUNCTION(0x0, "gpio_in"), 779 SUNXI_FUNCTION(0x1, "gpio_out")), 780 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, 781 SUNXI_FUNCTION(0x0, "gpio_in"), 782 SUNXI_FUNCTION(0x1, "gpio_out")), 783 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, 784 SUNXI_FUNCTION(0x0, "gpio_in"), 785 SUNXI_FUNCTION(0x1, "gpio_out")), 786 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, 787 SUNXI_FUNCTION(0x0, "gpio_in"), 788 SUNXI_FUNCTION(0x1, "gpio_out")), 789 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, 790 SUNXI_FUNCTION(0x0, "gpio_in"), 791 SUNXI_FUNCTION(0x1, "gpio_out")), 792 /* Hole */ 793 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, 794 SUNXI_FUNCTION(0x0, "gpio_in"), 795 SUNXI_FUNCTION(0x1, "gpio_out")), 796 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, 797 SUNXI_FUNCTION(0x0, "gpio_in"), 798 SUNXI_FUNCTION(0x1, "gpio_out")), 799 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, 800 SUNXI_FUNCTION(0x0, "gpio_in"), 801 SUNXI_FUNCTION(0x1, "gpio_out")), 802 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, 803 SUNXI_FUNCTION(0x0, "gpio_in"), 804 SUNXI_FUNCTION(0x1, "gpio_out"), 805 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 806 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, 807 SUNXI_FUNCTION(0x0, "gpio_in"), 808 SUNXI_FUNCTION(0x1, "gpio_out"), 809 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 810 /* Hole */ 811 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, 812 SUNXI_FUNCTION(0x0, "gpio_in"), 813 SUNXI_FUNCTION(0x1, "gpio_out")), 814 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, 815 SUNXI_FUNCTION(0x0, "gpio_in"), 816 SUNXI_FUNCTION(0x1, "gpio_out")), 817 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, 818 SUNXI_FUNCTION(0x0, "gpio_in"), 819 SUNXI_FUNCTION(0x1, "gpio_out")), 820 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12, 821 SUNXI_FUNCTION(0x0, "gpio_in"), 822 SUNXI_FUNCTION(0x1, "gpio_out")), 823}; 824 825static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { 826 .pins = sun4i_a10_pins, 827 .npins = ARRAY_SIZE(sun4i_a10_pins), 828}; 829 830static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = { 831 .pins = sun5i_a13_pins, 832 .npins = ARRAY_SIZE(sun5i_a13_pins), 833}; 834 835static struct sunxi_pinctrl_group * 836sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 837{ 838 int i; 839 840 for (i = 0; i < pctl->ngroups; i++) { 841 struct sunxi_pinctrl_group *grp = pctl->groups + i; 842 843 if (!strcmp(grp->name, group)) 844 return grp; 845 } 846 847 return NULL; 848} 849 850static struct sunxi_pinctrl_function * 851sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, 852 const char *name) 853{ 854 struct sunxi_pinctrl_function *func = pctl->functions; 855 int i; 856 857 for (i = 0; i < pctl->nfunctions; i++) { 858 if (!func[i].name) 859 break; 860 861 if (!strcmp(func[i].name, name)) 862 return func + i; 863 } 864 865 return NULL; 866} 867 868static struct sunxi_desc_function * 869sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, 870 const char *pin_name, 871 const char *func_name) 872{ 873 int i; 874 875 for (i = 0; i < pctl->desc->npins; i++) { 876 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 877 878 if (!strcmp(pin->pin.name, pin_name)) { 879 struct sunxi_desc_function *func = pin->functions; 880 881 while (func->name) { 882 if (!strcmp(func->name, func_name)) 883 return func; 884 885 func++; 886 } 887 } 888 } 889 890 return NULL; 891} 892 893static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 894{ 895 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 896 897 return pctl->ngroups; 898} 899 900static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, 901 unsigned group) 902{ 903 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 904 905 return pctl->groups[group].name; 906} 907 908static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 909 unsigned group, 910 const unsigned **pins, 911 unsigned *num_pins) 912{ 913 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 914 915 *pins = (unsigned *)&pctl->groups[group].pin; 916 *num_pins = 1; 917 918 return 0; 919} 920 921static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 922 struct device_node *node, 923 struct pinctrl_map **map, 924 unsigned *num_maps) 925{ 926 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 927 unsigned long *pinconfig; 928 struct property *prop; 929 const char *function; 930 const char *group; 931 int ret, nmaps, i = 0; 932 u32 val; 933 934 *map = NULL; 935 *num_maps = 0; 936 937 ret = of_property_read_string(node, "allwinner,function", &function); 938 if (ret) { 939 dev_err(pctl->dev, 940 "missing allwinner,function property in node %s\n", 941 node->name); 942 return -EINVAL; 943 } 944 945 nmaps = of_property_count_strings(node, "allwinner,pins") * 2; 946 if (nmaps < 0) { 947 dev_err(pctl->dev, 948 "missing allwinner,pins property in node %s\n", 949 node->name); 950 return -EINVAL; 951 } 952 953 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); 954 if (!map) 955 return -ENOMEM; 956 957 of_property_for_each_string(node, "allwinner,pins", prop, group) { 958 struct sunxi_pinctrl_group *grp = 959 sunxi_pinctrl_find_group_by_name(pctl, group); 960 int j = 0, configlen = 0; 961 962 if (!grp) { 963 dev_err(pctl->dev, "unknown pin %s", group); 964 continue; 965 } 966 967 if (!sunxi_pinctrl_desc_find_function_by_name(pctl, 968 grp->name, 969 function)) { 970 dev_err(pctl->dev, "unsupported function %s on pin %s", 971 function, group); 972 continue; 973 } 974 975 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 976 (*map)[i].data.mux.group = group; 977 (*map)[i].data.mux.function = function; 978 979 i++; 980 981 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; 982 (*map)[i].data.configs.group_or_pin = group; 983 984 if (of_find_property(node, "allwinner,drive", NULL)) 985 configlen++; 986 if (of_find_property(node, "allwinner,pull", NULL)) 987 configlen++; 988 989 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); 990 991 if (!of_property_read_u32(node, "allwinner,drive", &val)) { 992 u16 strength = (val + 1) * 10; 993 pinconfig[j++] = 994 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 995 strength); 996 } 997 998 if (!of_property_read_u32(node, "allwinner,pull", &val)) { 999 enum pin_config_param pull = PIN_CONFIG_END; 1000 if (val == 1) 1001 pull = PIN_CONFIG_BIAS_PULL_UP; 1002 else if (val == 2) 1003 pull = PIN_CONFIG_BIAS_PULL_DOWN; 1004 pinconfig[j++] = pinconf_to_config_packed(pull, 0); 1005 } 1006 1007 (*map)[i].data.configs.configs = pinconfig; 1008 (*map)[i].data.configs.num_configs = configlen; 1009 1010 i++; 1011 } 1012 1013 *num_maps = nmaps; 1014 1015 return 0; 1016} 1017 1018static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, 1019 struct pinctrl_map *map, 1020 unsigned num_maps) 1021{ 1022 int i; 1023 1024 for (i = 0; i < num_maps; i++) { 1025 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) 1026 kfree(map[i].data.configs.configs); 1027 } 1028 1029 kfree(map); 1030} 1031 1032static struct pinctrl_ops sunxi_pctrl_ops = { 1033 .dt_node_to_map = sunxi_pctrl_dt_node_to_map, 1034 .dt_free_map = sunxi_pctrl_dt_free_map, 1035 .get_groups_count = sunxi_pctrl_get_groups_count, 1036 .get_group_name = sunxi_pctrl_get_group_name, 1037 .get_group_pins = sunxi_pctrl_get_group_pins, 1038}; 1039 1040static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, 1041 unsigned group, 1042 unsigned long *config) 1043{ 1044 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1045 1046 *config = pctl->groups[group].config; 1047 1048 return 0; 1049} 1050 1051static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, 1052 unsigned group, 1053 unsigned long config) 1054{ 1055 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1056 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 1057 u32 val, mask; 1058 u16 strength; 1059 u8 dlevel; 1060 1061 switch (pinconf_to_config_param(config)) { 1062 case PIN_CONFIG_DRIVE_STRENGTH: 1063 strength = pinconf_to_config_argument(config); 1064 if (strength > 40) 1065 return -EINVAL; 1066 /* 1067 * We convert from mA to what the register expects: 1068 * 0: 10mA 1069 * 1: 20mA 1070 * 2: 30mA 1071 * 3: 40mA 1072 */ 1073 dlevel = strength / 10 - 1; 1074 val = readl(pctl->membase + sunxi_dlevel_reg(g->pin)); 1075 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin); 1076 writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin), 1077 pctl->membase + sunxi_dlevel_reg(g->pin)); 1078 break; 1079 case PIN_CONFIG_BIAS_PULL_UP: 1080 val = readl(pctl->membase + sunxi_pull_reg(g->pin)); 1081 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); 1082 writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin), 1083 pctl->membase + sunxi_pull_reg(g->pin)); 1084 break; 1085 case PIN_CONFIG_BIAS_PULL_DOWN: 1086 val = readl(pctl->membase + sunxi_pull_reg(g->pin)); 1087 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); 1088 writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin), 1089 pctl->membase + sunxi_pull_reg(g->pin)); 1090 break; 1091 default: 1092 break; 1093 } 1094 1095 /* cache the config value */ 1096 g->config = config; 1097 1098 return 0; 1099} 1100 1101static struct pinconf_ops sunxi_pconf_ops = { 1102 .pin_config_group_get = sunxi_pconf_group_get, 1103 .pin_config_group_set = sunxi_pconf_group_set, 1104}; 1105 1106static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 1107{ 1108 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1109 1110 return pctl->nfunctions; 1111} 1112 1113static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, 1114 unsigned function) 1115{ 1116 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1117 1118 return pctl->functions[function].name; 1119} 1120 1121static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, 1122 unsigned function, 1123 const char * const **groups, 1124 unsigned * const num_groups) 1125{ 1126 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1127 1128 *groups = pctl->functions[function].groups; 1129 *num_groups = pctl->functions[function].ngroups; 1130 1131 return 0; 1132} 1133 1134static void sunxi_pmx_set(struct pinctrl_dev *pctldev, 1135 unsigned pin, 1136 u8 config) 1137{ 1138 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1139 1140 u32 val = readl(pctl->membase + sunxi_mux_reg(pin)); 1141 u32 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); 1142 writel((val & ~mask) | config << sunxi_mux_offset(pin), 1143 pctl->membase + sunxi_mux_reg(pin)); 1144} 1145 1146static int sunxi_pmx_enable(struct pinctrl_dev *pctldev, 1147 unsigned function, 1148 unsigned group) 1149{ 1150 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1151 struct sunxi_pinctrl_group *g = pctl->groups + group; 1152 struct sunxi_pinctrl_function *func = pctl->functions + function; 1153 struct sunxi_desc_function *desc = 1154 sunxi_pinctrl_desc_find_function_by_name(pctl, 1155 g->name, 1156 func->name); 1157 1158 if (!desc) 1159 return -EINVAL; 1160 1161 sunxi_pmx_set(pctldev, g->pin, desc->muxval); 1162 1163 return 0; 1164} 1165 1166static int 1167sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 1168 struct pinctrl_gpio_range *range, 1169 unsigned offset, 1170 bool input) 1171{ 1172 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1173 struct sunxi_desc_function *desc; 1174 char pin_name[SUNXI_PIN_NAME_MAX_LEN]; 1175 const char *func; 1176 u8 bank, pin; 1177 int ret; 1178 1179 bank = (offset) / PINS_PER_BANK; 1180 pin = (offset) % PINS_PER_BANK; 1181 1182 ret = sprintf(pin_name, "P%c%d", 'A' + bank, pin); 1183 if (!ret) 1184 goto error; 1185 1186 if (input) 1187 func = "gpio_in"; 1188 else 1189 func = "gpio_out"; 1190 1191 desc = sunxi_pinctrl_desc_find_function_by_name(pctl, 1192 pin_name, 1193 func); 1194 if (!desc) { 1195 ret = -EINVAL; 1196 goto error; 1197 } 1198 1199 sunxi_pmx_set(pctldev, offset, desc->muxval); 1200 1201 ret = 0; 1202 1203error: 1204 return ret; 1205} 1206 1207static struct pinmux_ops sunxi_pmx_ops = { 1208 .get_functions_count = sunxi_pmx_get_funcs_cnt, 1209 .get_function_name = sunxi_pmx_get_func_name, 1210 .get_function_groups = sunxi_pmx_get_func_groups, 1211 .enable = sunxi_pmx_enable, 1212 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 1213}; 1214 1215static struct pinctrl_desc sunxi_pctrl_desc = { 1216 .confops = &sunxi_pconf_ops, 1217 .pctlops = &sunxi_pctrl_ops, 1218 .pmxops = &sunxi_pmx_ops, 1219}; 1220 1221static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset) 1222{ 1223 return pinctrl_request_gpio(chip->base + offset); 1224} 1225 1226static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset) 1227{ 1228 pinctrl_free_gpio(chip->base + offset); 1229} 1230 1231static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, 1232 unsigned offset) 1233{ 1234 return pinctrl_gpio_direction_input(chip->base + offset); 1235} 1236 1237static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) 1238{ 1239 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 1240 1241 u32 reg = sunxi_data_reg(offset); 1242 u8 index = sunxi_data_offset(offset); 1243 u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; 1244 1245 return val; 1246} 1247 1248static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, 1249 unsigned offset, int value) 1250{ 1251 return pinctrl_gpio_direction_output(chip->base + offset); 1252} 1253 1254static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, 1255 unsigned offset, int value) 1256{ 1257 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 1258 u32 reg = sunxi_data_reg(offset); 1259 u8 index = sunxi_data_offset(offset); 1260 1261 writel((value & DATA_PINS_MASK) << index, pctl->membase + reg); 1262} 1263 1264static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 1265 const struct of_phandle_args *gpiospec, 1266 u32 *flags) 1267{ 1268 int pin, base; 1269 1270 base = PINS_PER_BANK * gpiospec->args[0]; 1271 pin = base + gpiospec->args[1]; 1272 1273 if (pin > (gc->base + gc->ngpio)) 1274 return -EINVAL; 1275 1276 if (flags) 1277 *flags = gpiospec->args[2]; 1278 1279 return pin; 1280} 1281 1282static struct gpio_chip sunxi_pinctrl_gpio_chip = { 1283 .owner = THIS_MODULE, 1284 .request = sunxi_pinctrl_gpio_request, 1285 .free = sunxi_pinctrl_gpio_free, 1286 .direction_input = sunxi_pinctrl_gpio_direction_input, 1287 .direction_output = sunxi_pinctrl_gpio_direction_output, 1288 .get = sunxi_pinctrl_gpio_get, 1289 .set = sunxi_pinctrl_gpio_set, 1290 .of_xlate = sunxi_pinctrl_gpio_of_xlate, 1291 .of_gpio_n_cells = 3, 1292 .can_sleep = 0, 1293}; 1294 1295static struct of_device_id sunxi_pinctrl_match[] = { 1296 { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data }, 1297 { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data }, 1298 {} 1299}; 1300MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match); 1301 1302static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 1303 const char *name) 1304{ 1305 struct sunxi_pinctrl_function *func = pctl->functions; 1306 1307 while (func->name) { 1308 /* function already there */ 1309 if (strcmp(func->name, name) == 0) { 1310 func->ngroups++; 1311 return -EEXIST; 1312 } 1313 func++; 1314 } 1315 1316 func->name = name; 1317 func->ngroups = 1; 1318 1319 pctl->nfunctions++; 1320 1321 return 0; 1322} 1323 1324static int sunxi_pinctrl_build_state(struct platform_device *pdev) 1325{ 1326 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); 1327 int i; 1328 1329 pctl->ngroups = pctl->desc->npins; 1330 1331 /* Allocate groups */ 1332 pctl->groups = devm_kzalloc(&pdev->dev, 1333 pctl->ngroups * sizeof(*pctl->groups), 1334 GFP_KERNEL); 1335 if (!pctl->groups) 1336 return -ENOMEM; 1337 1338 for (i = 0; i < pctl->desc->npins; i++) { 1339 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1340 struct sunxi_pinctrl_group *group = pctl->groups + i; 1341 1342 group->name = pin->pin.name; 1343 group->pin = pin->pin.number; 1344 } 1345 1346 /* 1347 * We suppose that we won't have any more functions than pins, 1348 * we'll reallocate that later anyway 1349 */ 1350 pctl->functions = devm_kzalloc(&pdev->dev, 1351 pctl->desc->npins * sizeof(*pctl->functions), 1352 GFP_KERNEL); 1353 if (!pctl->functions) 1354 return -ENOMEM; 1355 1356 /* Count functions and their associated groups */ 1357 for (i = 0; i < pctl->desc->npins; i++) { 1358 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1359 struct sunxi_desc_function *func = pin->functions; 1360 1361 while (func->name) { 1362 sunxi_pinctrl_add_function(pctl, func->name); 1363 func++; 1364 } 1365 } 1366 1367 pctl->functions = krealloc(pctl->functions, 1368 pctl->nfunctions * sizeof(*pctl->functions), 1369 GFP_KERNEL); 1370 1371 for (i = 0; i < pctl->desc->npins; i++) { 1372 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1373 struct sunxi_desc_function *func = pin->functions; 1374 1375 while (func->name) { 1376 struct sunxi_pinctrl_function *func_item; 1377 const char **func_grp; 1378 1379 func_item = sunxi_pinctrl_find_function_by_name(pctl, 1380 func->name); 1381 if (!func_item) 1382 return -EINVAL; 1383 1384 if (!func_item->groups) { 1385 func_item->groups = 1386 devm_kzalloc(&pdev->dev, 1387 func_item->ngroups * sizeof(*func_item->groups), 1388 GFP_KERNEL); 1389 if (!func_item->groups) 1390 return -ENOMEM; 1391 } 1392 1393 func_grp = func_item->groups; 1394 while (*func_grp) 1395 func_grp++; 1396 1397 *func_grp = pin->pin.name; 1398 func++; 1399 } 1400 } 1401 1402 return 0; 1403} 1404 1405static int sunxi_pinctrl_probe(struct platform_device *pdev) 1406{ 1407 struct device_node *node = pdev->dev.of_node; 1408 const struct of_device_id *device; 1409 struct pinctrl_pin_desc *pins; 1410 struct sunxi_pinctrl *pctl; 1411 int i, ret, last_pin; 1412 1413 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 1414 if (!pctl) 1415 return -ENOMEM; 1416 platform_set_drvdata(pdev, pctl); 1417 1418 pctl->membase = of_iomap(node, 0); 1419 if (!pctl->membase) 1420 return -ENOMEM; 1421 1422 device = of_match_device(sunxi_pinctrl_match, &pdev->dev); 1423 if (!device) 1424 return -ENODEV; 1425 1426 pctl->desc = (struct sunxi_pinctrl_desc *)device->data; 1427 1428 ret = sunxi_pinctrl_build_state(pdev); 1429 if (ret) { 1430 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 1431 return ret; 1432 } 1433 1434 pins = devm_kzalloc(&pdev->dev, 1435 pctl->desc->npins * sizeof(*pins), 1436 GFP_KERNEL); 1437 if (!pins) 1438 return -ENOMEM; 1439 1440 for (i = 0; i < pctl->desc->npins; i++) 1441 pins[i] = pctl->desc->pins[i].pin; 1442 1443 sunxi_pctrl_desc.name = dev_name(&pdev->dev); 1444 sunxi_pctrl_desc.owner = THIS_MODULE; 1445 sunxi_pctrl_desc.pins = pins; 1446 sunxi_pctrl_desc.npins = pctl->desc->npins; 1447 pctl->dev = &pdev->dev; 1448 pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc, 1449 &pdev->dev, pctl); 1450 if (!pctl->pctl_dev) { 1451 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 1452 return -EINVAL; 1453 } 1454 1455 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 1456 if (!pctl->chip) { 1457 ret = -ENOMEM; 1458 goto pinctrl_error; 1459 } 1460 1461 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 1462 pctl->chip = &sunxi_pinctrl_gpio_chip; 1463 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK); 1464 pctl->chip->label = dev_name(&pdev->dev); 1465 pctl->chip->dev = &pdev->dev; 1466 pctl->chip->base = 0; 1467 1468 ret = gpiochip_add(pctl->chip); 1469 if (ret) 1470 goto pinctrl_error; 1471 1472 for (i = 0; i < pctl->desc->npins; i++) { 1473 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1474 1475 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 1476 pin->pin.number, 1477 pin->pin.number, 1); 1478 if (ret) 1479 goto gpiochip_error; 1480 } 1481 1482 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 1483 1484 return 0; 1485 1486gpiochip_error: 1487 ret = gpiochip_remove(pctl->chip); 1488pinctrl_error: 1489 pinctrl_unregister(pctl->pctl_dev); 1490 return ret; 1491} 1492 1493static struct platform_driver sunxi_pinctrl_driver = { 1494 .probe = sunxi_pinctrl_probe, 1495 .driver = { 1496 .name = "sunxi-pinctrl", 1497 .owner = THIS_MODULE, 1498 .of_match_table = sunxi_pinctrl_match, 1499 }, 1500}; 1501module_platform_driver(sunxi_pinctrl_driver); 1502 1503MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com"); 1504MODULE_DESCRIPTION("Allwinner A1X pinctrl driver"); 1505MODULE_LICENSE("GPL");