Linux kernel mirror (for testing)
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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
8 */
9#ifndef __ASM_CPU_FEATURES_H
10#define __ASM_CPU_FEATURES_H
11
12#include <asm/cpu.h>
13#include <asm/cpu-info.h>
14#include <cpu-feature-overrides.h>
15
16#ifndef current_cpu_type
17#define current_cpu_type() current_cpu_data.cputype
18#endif
19
20/*
21 * SMP assumption: Options of CPU 0 are a superset of all processors.
22 * This is true for all known MIPS systems.
23 */
24#ifndef cpu_has_tlb
25#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
26#endif
27#ifndef cpu_has_4kex
28#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
29#endif
30#ifndef cpu_has_3k_cache
31#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
32#endif
33#define cpu_has_6k_cache 0
34#define cpu_has_8k_cache 0
35#ifndef cpu_has_4k_cache
36#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
37#endif
38#ifndef cpu_has_tx39_cache
39#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
40#endif
41#ifndef cpu_has_octeon_cache
42#define cpu_has_octeon_cache 0
43#endif
44#ifndef cpu_has_fpu
45#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
46#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
47#else
48#define raw_cpu_has_fpu cpu_has_fpu
49#endif
50#ifndef cpu_has_32fpr
51#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
52#endif
53#ifndef cpu_has_counter
54#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
55#endif
56#ifndef cpu_has_watch
57#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
58#endif
59#ifndef cpu_has_divec
60#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
61#endif
62#ifndef cpu_has_vce
63#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
64#endif
65#ifndef cpu_has_cache_cdex_p
66#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
67#endif
68#ifndef cpu_has_cache_cdex_s
69#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
70#endif
71#ifndef cpu_has_prefetch
72#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
73#endif
74#ifndef cpu_has_mcheck
75#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
76#endif
77#ifndef cpu_has_ejtag
78#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
79#endif
80#ifndef cpu_has_llsc
81#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
82#endif
83#ifndef kernel_uses_llsc
84#define kernel_uses_llsc cpu_has_llsc
85#endif
86#ifndef cpu_has_mips16
87#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
88#endif
89#ifndef cpu_has_mdmx
90#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
91#endif
92#ifndef cpu_has_mips3d
93#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
94#endif
95#ifndef cpu_has_smartmips
96#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
97#endif
98#ifndef cpu_has_rixi
99#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
100#endif
101#ifndef cpu_has_mmips
102#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
103#endif
104#ifndef cpu_has_vtag_icache
105#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
106#endif
107#ifndef cpu_has_dc_aliases
108#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
109#endif
110#ifndef cpu_has_ic_fills_f_dc
111#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
112#endif
113#ifndef cpu_has_pindexed_dcache
114#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
115#endif
116
117/*
118 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
119 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
120 * don't. For maintaining I-cache coherency this means we need to flush the
121 * D-cache all the way back to whever the I-cache does refills from, so the
122 * I-cache has a chance to see the new data at all. Then we have to flush the
123 * I-cache also.
124 * Note we may have been rescheduled and may no longer be running on the CPU
125 * that did the store so we can't optimize this into only doing the flush on
126 * the local CPU.
127 */
128#ifndef cpu_icache_snoops_remote_store
129#ifdef CONFIG_SMP
130#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
131#else
132#define cpu_icache_snoops_remote_store 1
133#endif
134#endif
135
136# define cpu_has_mips_1 (cpu_data[0].isa_level & MIPS_CPU_ISA_I)
137#ifndef cpu_has_mips_2
138# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
139#endif
140#ifndef cpu_has_mips_3
141# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
142#endif
143#ifndef cpu_has_mips_4
144# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
145#endif
146#ifndef cpu_has_mips_5
147# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
148#endif
149# ifndef cpu_has_mips32r1
150# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
151# endif
152# ifndef cpu_has_mips32r2
153# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
154# endif
155# ifndef cpu_has_mips64r1
156# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
157# endif
158# ifndef cpu_has_mips64r2
159# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
160# endif
161
162/*
163 * Shortcuts ...
164 */
165#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
166#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
167#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
168#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
169#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
170 cpu_has_mips64r1 | cpu_has_mips64r2)
171
172#ifndef cpu_has_mips_r2_exec_hazard
173#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
174#endif
175
176/*
177 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
178 * pre-MIPS32/MIPS53 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
179 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
180 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
181 */
182# ifndef cpu_has_clo_clz
183# define cpu_has_clo_clz cpu_has_mips_r
184# endif
185
186#ifndef cpu_has_dsp
187#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
188#endif
189
190#ifndef cpu_has_dsp2
191#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
192#endif
193
194#ifndef cpu_has_mipsmt
195#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
196#endif
197
198#ifndef cpu_has_userlocal
199#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
200#endif
201
202#ifdef CONFIG_32BIT
203# ifndef cpu_has_nofpuex
204# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
205# endif
206# ifndef cpu_has_64bits
207# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
208# endif
209# ifndef cpu_has_64bit_zero_reg
210# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
211# endif
212# ifndef cpu_has_64bit_gp_regs
213# define cpu_has_64bit_gp_regs 0
214# endif
215# ifndef cpu_has_64bit_addresses
216# define cpu_has_64bit_addresses 0
217# endif
218# ifndef cpu_vmbits
219# define cpu_vmbits 31
220# endif
221#endif
222
223#ifdef CONFIG_64BIT
224# ifndef cpu_has_nofpuex
225# define cpu_has_nofpuex 0
226# endif
227# ifndef cpu_has_64bits
228# define cpu_has_64bits 1
229# endif
230# ifndef cpu_has_64bit_zero_reg
231# define cpu_has_64bit_zero_reg 1
232# endif
233# ifndef cpu_has_64bit_gp_regs
234# define cpu_has_64bit_gp_regs 1
235# endif
236# ifndef cpu_has_64bit_addresses
237# define cpu_has_64bit_addresses 1
238# endif
239# ifndef cpu_vmbits
240# define cpu_vmbits cpu_data[0].vmbits
241# define __NEED_VMBITS_PROBE
242# endif
243#endif
244
245#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
246# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
247#elif !defined(cpu_has_vint)
248# define cpu_has_vint 0
249#endif
250
251#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
252# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
253#elif !defined(cpu_has_veic)
254# define cpu_has_veic 0
255#endif
256
257#ifndef cpu_has_inclusive_pcaches
258#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
259#endif
260
261#ifndef cpu_dcache_line_size
262#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
263#endif
264#ifndef cpu_icache_line_size
265#define cpu_icache_line_size() cpu_data[0].icache.linesz
266#endif
267#ifndef cpu_scache_line_size
268#define cpu_scache_line_size() cpu_data[0].scache.linesz
269#endif
270
271#ifndef cpu_hwrena_impl_bits
272#define cpu_hwrena_impl_bits 0
273#endif
274
275#ifndef cpu_has_perf_cntr_intr_bit
276#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
277#endif
278
279#ifndef cpu_has_vz
280#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
281#endif
282
283#endif /* __ASM_CPU_FEATURES_H */