tjh.dev
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1/*
2 * max77693-private.h - Voltage regulator driver for the Maxim 77693
3 *
4 * Copyright (C) 2012 Samsung Electrnoics
5 * SangYoung Son <hello.son@samsung.com>
6 *
7 * This program is not provided / owned by Maxim Integrated Products.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#ifndef __LINUX_MFD_MAX77693_PRIV_H
25#define __LINUX_MFD_MAX77693_PRIV_H
26
27#include <linux/i2c.h>
28
29#define MAX77693_NUM_IRQ_MUIC_REGS 3
30#define MAX77693_REG_INVALID (0xff)
31
32/* Slave addr = 0xCC: PMIC, Charger, Flash LED */
33enum max77693_pmic_reg {
34 MAX77693_LED_REG_IFLASH1 = 0x00,
35 MAX77693_LED_REG_IFLASH2 = 0x01,
36 MAX77693_LED_REG_ITORCH = 0x02,
37 MAX77693_LED_REG_ITORCHTIMER = 0x03,
38 MAX77693_LED_REG_FLASH_TIMER = 0x04,
39 MAX77693_LED_REG_FLASH_EN = 0x05,
40 MAX77693_LED_REG_MAX_FLASH1 = 0x06,
41 MAX77693_LED_REG_MAX_FLASH2 = 0x07,
42 MAX77693_LED_REG_MAX_FLASH3 = 0x08,
43 MAX77693_LED_REG_MAX_FLASH4 = 0x09,
44 MAX77693_LED_REG_VOUT_CNTL = 0x0A,
45 MAX77693_LED_REG_VOUT_FLASH1 = 0x0B,
46 MAX77693_LED_REG_VOUT_FLASH2 = 0x0C,
47 MAX77693_LED_REG_FLASH_INT = 0x0E,
48 MAX77693_LED_REG_FLASH_INT_MASK = 0x0F,
49 MAX77693_LED_REG_FLASH_INT_STATUS = 0x10,
50
51 MAX77693_PMIC_REG_PMIC_ID1 = 0x20,
52 MAX77693_PMIC_REG_PMIC_ID2 = 0x21,
53 MAX77693_PMIC_REG_INTSRC = 0x22,
54 MAX77693_PMIC_REG_INTSRC_MASK = 0x23,
55 MAX77693_PMIC_REG_TOPSYS_INT = 0x24,
56 MAX77693_PMIC_REG_TOPSYS_INT_MASK = 0x26,
57 MAX77693_PMIC_REG_TOPSYS_STAT = 0x28,
58 MAX77693_PMIC_REG_MAINCTRL1 = 0x2A,
59 MAX77693_PMIC_REG_LSCNFG = 0x2B,
60
61 MAX77693_CHG_REG_CHG_INT = 0xB0,
62 MAX77693_CHG_REG_CHG_INT_MASK = 0xB1,
63 MAX77693_CHG_REG_CHG_INT_OK = 0xB2,
64 MAX77693_CHG_REG_CHG_DETAILS_00 = 0xB3,
65 MAX77693_CHG_REG_CHG_DETAILS_01 = 0xB4,
66 MAX77693_CHG_REG_CHG_DETAILS_02 = 0xB5,
67 MAX77693_CHG_REG_CHG_DETAILS_03 = 0xB6,
68 MAX77693_CHG_REG_CHG_CNFG_00 = 0xB7,
69 MAX77693_CHG_REG_CHG_CNFG_01 = 0xB8,
70 MAX77693_CHG_REG_CHG_CNFG_02 = 0xB9,
71 MAX77693_CHG_REG_CHG_CNFG_03 = 0xBA,
72 MAX77693_CHG_REG_CHG_CNFG_04 = 0xBB,
73 MAX77693_CHG_REG_CHG_CNFG_05 = 0xBC,
74 MAX77693_CHG_REG_CHG_CNFG_06 = 0xBD,
75 MAX77693_CHG_REG_CHG_CNFG_07 = 0xBE,
76 MAX77693_CHG_REG_CHG_CNFG_08 = 0xBF,
77 MAX77693_CHG_REG_CHG_CNFG_09 = 0xC0,
78 MAX77693_CHG_REG_CHG_CNFG_10 = 0xC1,
79 MAX77693_CHG_REG_CHG_CNFG_11 = 0xC2,
80 MAX77693_CHG_REG_CHG_CNFG_12 = 0xC3,
81 MAX77693_CHG_REG_CHG_CNFG_13 = 0xC4,
82 MAX77693_CHG_REG_CHG_CNFG_14 = 0xC5,
83 MAX77693_CHG_REG_SAFEOUT_CTRL = 0xC6,
84
85 MAX77693_PMIC_REG_END,
86};
87
88/* Slave addr = 0x4A: MUIC */
89enum max77693_muic_reg {
90 MAX77693_MUIC_REG_ID = 0x00,
91 MAX77693_MUIC_REG_INT1 = 0x01,
92 MAX77693_MUIC_REG_INT2 = 0x02,
93 MAX77693_MUIC_REG_INT3 = 0x03,
94 MAX77693_MUIC_REG_STATUS1 = 0x04,
95 MAX77693_MUIC_REG_STATUS2 = 0x05,
96 MAX77693_MUIC_REG_STATUS3 = 0x06,
97 MAX77693_MUIC_REG_INTMASK1 = 0x07,
98 MAX77693_MUIC_REG_INTMASK2 = 0x08,
99 MAX77693_MUIC_REG_INTMASK3 = 0x09,
100 MAX77693_MUIC_REG_CDETCTRL1 = 0x0A,
101 MAX77693_MUIC_REG_CDETCTRL2 = 0x0B,
102 MAX77693_MUIC_REG_CTRL1 = 0x0C,
103 MAX77693_MUIC_REG_CTRL2 = 0x0D,
104 MAX77693_MUIC_REG_CTRL3 = 0x0E,
105
106 MAX77693_MUIC_REG_END,
107};
108
109/* MAX77693 MUIC - STATUS1~3 Register */
110#define STATUS1_ADC_SHIFT (0)
111#define STATUS1_ADCLOW_SHIFT (5)
112#define STATUS1_ADCERR_SHIFT (6)
113#define STATUS1_ADC1K_SHIFT (7)
114#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
115#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
116#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
117#define STATUS1_ADC1K_MASK (0x1 << STATUS1_ADC1K_SHIFT)
118
119#define STATUS2_CHGTYP_SHIFT (0)
120#define STATUS2_CHGDETRUN_SHIFT (3)
121#define STATUS2_DCDTMR_SHIFT (4)
122#define STATUS2_DXOVP_SHIFT (5)
123#define STATUS2_VBVOLT_SHIFT (6)
124#define STATUS2_VIDRM_SHIFT (7)
125#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
126#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
127#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
128#define STATUS2_DXOVP_MASK (0x1 << STATUS2_DXOVP_SHIFT)
129#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
130#define STATUS2_VIDRM_MASK (0x1 << STATUS2_VIDRM_SHIFT)
131
132#define STATUS3_OVP_SHIFT (2)
133#define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
134
135/* MAX77693 CDETCTRL1~2 register */
136#define CDETCTRL1_CHGDETEN_SHIFT (0)
137#define CDETCTRL1_CHGTYPMAN_SHIFT (1)
138#define CDETCTRL1_DCDEN_SHIFT (2)
139#define CDETCTRL1_DCD2SCT_SHIFT (3)
140#define CDETCTRL1_CDDELAY_SHIFT (4)
141#define CDETCTRL1_DCDCPL_SHIFT (5)
142#define CDETCTRL1_CDPDET_SHIFT (7)
143#define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT)
144#define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
145#define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT)
146#define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT)
147#define CDETCTRL1_CDDELAY_MASK (0x1 << CDETCTRL1_CDDELAY_SHIFT)
148#define CDETCTRL1_DCDCPL_MASK (0x1 << CDETCTRL1_DCDCPL_SHIFT)
149#define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT)
150
151#define CDETCTRL2_VIDRMEN_SHIFT (1)
152#define CDETCTRL2_DXOVPEN_SHIFT (3)
153#define CDETCTRL2_VIDRMEN_MASK (0x1 << CDETCTRL2_VIDRMEN_SHIFT)
154#define CDETCTRL2_DXOVPEN_MASK (0x1 << CDETCTRL2_DXOVPEN_SHIFT)
155
156/* MAX77693 MUIC - CONTROL1~3 register */
157#define COMN1SW_SHIFT (0)
158#define COMP2SW_SHIFT (3)
159#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
160#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
161#define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK)
162#define CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \
163 | (1 << COMN1SW_SHIFT))
164#define CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
165 | (2 << COMN1SW_SHIFT))
166#define CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \
167 | (3 << COMN1SW_SHIFT))
168#define CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
169 | (0 << COMN1SW_SHIFT))
170
171#define CONTROL2_LOWPWR_SHIFT (0)
172#define CONTROL2_ADCEN_SHIFT (1)
173#define CONTROL2_CPEN_SHIFT (2)
174#define CONTROL2_SFOUTASRT_SHIFT (3)
175#define CONTROL2_SFOUTORD_SHIFT (4)
176#define CONTROL2_ACCDET_SHIFT (5)
177#define CONTROL2_USBCPINT_SHIFT (6)
178#define CONTROL2_RCPS_SHIFT (7)
179#define CONTROL2_LOWPWR_MASK (0x1 << CONTROL2_LOWPWR_SHIFT)
180#define CONTROL2_ADCEN_MASK (0x1 << CONTROL2_ADCEN_SHIFT)
181#define CONTROL2_CPEN_MASK (0x1 << CONTROL2_CPEN_SHIFT)
182#define CONTROL2_SFOUTASRT_MASK (0x1 << CONTROL2_SFOUTASRT_SHIFT)
183#define CONTROL2_SFOUTORD_MASK (0x1 << CONTROL2_SFOUTORD_SHIFT)
184#define CONTROL2_ACCDET_MASK (0x1 << CONTROL2_ACCDET_SHIFT)
185#define CONTROL2_USBCPINT_MASK (0x1 << CONTROL2_USBCPINT_SHIFT)
186#define CONTROL2_RCPS_MASK (0x1 << CONTROL2_RCPS_SHIFT)
187
188#define CONTROL3_JIGSET_SHIFT (0)
189#define CONTROL3_BTLDSET_SHIFT (2)
190#define CONTROL3_ADCDBSET_SHIFT (4)
191#define CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
192#define CONTROL3_BTLDSET_MASK (0x3 << CONTROL3_BTLDSET_SHIFT)
193#define CONTROL3_ADCDBSET_MASK (0x3 << CONTROL3_ADCDBSET_SHIFT)
194
195/* Slave addr = 0x90: Haptic */
196enum max77693_haptic_reg {
197 MAX77693_HAPTIC_REG_STATUS = 0x00,
198 MAX77693_HAPTIC_REG_CONFIG1 = 0x01,
199 MAX77693_HAPTIC_REG_CONFIG2 = 0x02,
200 MAX77693_HAPTIC_REG_CONFIG_CHNL = 0x03,
201 MAX77693_HAPTIC_REG_CONFG_CYC1 = 0x04,
202 MAX77693_HAPTIC_REG_CONFG_CYC2 = 0x05,
203 MAX77693_HAPTIC_REG_CONFIG_PER1 = 0x06,
204 MAX77693_HAPTIC_REG_CONFIG_PER2 = 0x07,
205 MAX77693_HAPTIC_REG_CONFIG_PER3 = 0x08,
206 MAX77693_HAPTIC_REG_CONFIG_PER4 = 0x09,
207 MAX77693_HAPTIC_REG_CONFIG_DUTY1 = 0x0A,
208 MAX77693_HAPTIC_REG_CONFIG_DUTY2 = 0x0B,
209 MAX77693_HAPTIC_REG_CONFIG_PWM1 = 0x0C,
210 MAX77693_HAPTIC_REG_CONFIG_PWM2 = 0x0D,
211 MAX77693_HAPTIC_REG_CONFIG_PWM3 = 0x0E,
212 MAX77693_HAPTIC_REG_CONFIG_PWM4 = 0x0F,
213 MAX77693_HAPTIC_REG_REV = 0x10,
214
215 MAX77693_HAPTIC_REG_END,
216};
217
218enum max77693_irq_source {
219 LED_INT = 0,
220 TOPSYS_INT,
221 CHG_INT,
222 MUIC_INT1,
223 MUIC_INT2,
224 MUIC_INT3,
225
226 MAX77693_IRQ_GROUP_NR,
227};
228
229enum max77693_irq {
230 /* PMIC - FLASH */
231 MAX77693_LED_IRQ_FLED2_OPEN,
232 MAX77693_LED_IRQ_FLED2_SHORT,
233 MAX77693_LED_IRQ_FLED1_OPEN,
234 MAX77693_LED_IRQ_FLED1_SHORT,
235 MAX77693_LED_IRQ_MAX_FLASH,
236
237 /* PMIC - TOPSYS */
238 MAX77693_TOPSYS_IRQ_T120C_INT,
239 MAX77693_TOPSYS_IRQ_T140C_INT,
240 MAX77693_TOPSYS_IRQ_LOWSYS_INT,
241
242 /* PMIC - Charger */
243 MAX77693_CHG_IRQ_BYP_I,
244 MAX77693_CHG_IRQ_THM_I,
245 MAX77693_CHG_IRQ_BAT_I,
246 MAX77693_CHG_IRQ_CHG_I,
247 MAX77693_CHG_IRQ_CHGIN_I,
248
249 /* MUIC INT1 */
250 MAX77693_MUIC_IRQ_INT1_ADC,
251 MAX77693_MUIC_IRQ_INT1_ADC_LOW,
252 MAX77693_MUIC_IRQ_INT1_ADC_ERR,
253 MAX77693_MUIC_IRQ_INT1_ADC1K,
254
255 /* MUIC INT2 */
256 MAX77693_MUIC_IRQ_INT2_CHGTYP,
257 MAX77693_MUIC_IRQ_INT2_CHGDETREUN,
258 MAX77693_MUIC_IRQ_INT2_DCDTMR,
259 MAX77693_MUIC_IRQ_INT2_DXOVP,
260 MAX77693_MUIC_IRQ_INT2_VBVOLT,
261 MAX77693_MUIC_IRQ_INT2_VIDRM,
262
263 /* MUIC INT3 */
264 MAX77693_MUIC_IRQ_INT3_EOC,
265 MAX77693_MUIC_IRQ_INT3_CGMBC,
266 MAX77693_MUIC_IRQ_INT3_OVP,
267 MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR,
268 MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
269 MAX77693_MUIC_IRQ_INT3_BAT_DET,
270
271 MAX77693_IRQ_NR,
272};
273
274struct max77693_dev {
275 struct device *dev;
276 struct i2c_client *i2c; /* 0xCC , PMIC, Charger, Flash LED */
277 struct i2c_client *muic; /* 0x4A , MUIC */
278 struct i2c_client *haptic; /* 0x90 , Haptic */
279
280 int type;
281
282 struct regmap *regmap;
283 struct regmap *regmap_muic;
284 struct regmap *regmap_haptic;
285
286 struct irq_domain *irq_domain;
287
288 int irq;
289 int irq_gpio;
290 bool wakeup;
291 struct mutex irqlock;
292 int irq_masks_cur[MAX77693_IRQ_GROUP_NR];
293 int irq_masks_cache[MAX77693_IRQ_GROUP_NR];
294};
295
296enum max77693_types {
297 TYPE_MAX77693,
298};
299
300extern int max77693_read_reg(struct regmap *map, u8 reg, u8 *dest);
301extern int max77693_bulk_read(struct regmap *map, u8 reg, int count,
302 u8 *buf);
303extern int max77693_write_reg(struct regmap *map, u8 reg, u8 value);
304extern int max77693_bulk_write(struct regmap *map, u8 reg, int count,
305 u8 *buf);
306extern int max77693_update_reg(struct regmap *map, u8 reg, u8 val, u8 mask);
307
308extern int max77693_irq_init(struct max77693_dev *max77686);
309extern void max77693_irq_exit(struct max77693_dev *max77686);
310extern int max77693_irq_resume(struct max77693_dev *max77686);
311
312#endif /* __LINUX_MFD_MAX77693_PRIV_H */