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Linux kernel mirror (for testing)
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linux
1/**
2 * dwc3-omap.c - OMAP Specific Glue layer
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/module.h>
40#include <linux/kernel.h>
41#include <linux/slab.h>
42#include <linux/interrupt.h>
43#include <linux/spinlock.h>
44#include <linux/platform_device.h>
45#include <linux/platform_data/dwc3-omap.h>
46#include <linux/usb/dwc3-omap.h>
47#include <linux/pm_runtime.h>
48#include <linux/dma-mapping.h>
49#include <linux/ioport.h>
50#include <linux/io.h>
51#include <linux/of.h>
52#include <linux/of_platform.h>
53
54#include <linux/usb/otg.h>
55#include <linux/usb/nop-usb-xceiv.h>
56
57#include "core.h"
58
59/*
60 * All these registers belong to OMAP's Wrapper around the
61 * DesignWare USB3 Core.
62 */
63
64#define USBOTGSS_REVISION 0x0000
65#define USBOTGSS_SYSCONFIG 0x0010
66#define USBOTGSS_IRQ_EOI 0x0020
67#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
68#define USBOTGSS_IRQSTATUS_0 0x0028
69#define USBOTGSS_IRQENABLE_SET_0 0x002c
70#define USBOTGSS_IRQENABLE_CLR_0 0x0030
71#define USBOTGSS_IRQSTATUS_RAW_1 0x0034
72#define USBOTGSS_IRQSTATUS_1 0x0038
73#define USBOTGSS_IRQENABLE_SET_1 0x003c
74#define USBOTGSS_IRQENABLE_CLR_1 0x0040
75#define USBOTGSS_UTMI_OTG_CTRL 0x0080
76#define USBOTGSS_UTMI_OTG_STATUS 0x0084
77#define USBOTGSS_MMRAM_OFFSET 0x0100
78#define USBOTGSS_FLADJ 0x0104
79#define USBOTGSS_DEBUG_CFG 0x0108
80#define USBOTGSS_DEBUG_DATA 0x010c
81
82/* SYSCONFIG REGISTER */
83#define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
84
85/* IRQ_EOI REGISTER */
86#define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
87
88/* IRQS0 BITS */
89#define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
90
91/* IRQ1 BITS */
92#define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17)
93#define USBOTGSS_IRQ1_OEVT (1 << 16)
94#define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13)
95#define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12)
96#define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11)
97#define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8)
98#define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5)
99#define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4)
100#define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3)
101#define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0)
102
103/* UTMI_OTG_CTRL REGISTER */
104#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
105#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
106#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
107#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
108
109/* UTMI_OTG_STATUS REGISTER */
110#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
111#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
112#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
113#define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
114#define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
115#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
116#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
117
118struct dwc3_omap {
119 /* device lock */
120 spinlock_t lock;
121
122 struct platform_device *usb2_phy;
123 struct platform_device *usb3_phy;
124 struct device *dev;
125
126 int irq;
127 void __iomem *base;
128
129 void *context;
130 u32 resource_size;
131
132 u32 dma_status:1;
133};
134
135struct dwc3_omap *_omap;
136
137static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
138{
139 return readl(base + offset);
140}
141
142static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
143{
144 writel(value, base + offset);
145}
146
147void dwc3_omap_mailbox(enum omap_dwc3_vbus_id_status status)
148{
149 u32 val;
150 struct dwc3_omap *omap = _omap;
151
152 switch (status) {
153 case OMAP_DWC3_ID_GROUND:
154 dev_dbg(omap->dev, "ID GND\n");
155
156 val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
157 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
158 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
159 | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
160 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
161 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
162 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
163 break;
164
165 case OMAP_DWC3_VBUS_VALID:
166 dev_dbg(omap->dev, "VBUS Connect\n");
167
168 val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
169 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
170 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
171 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
172 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
173 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
174 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
175 break;
176
177 case OMAP_DWC3_ID_FLOAT:
178 case OMAP_DWC3_VBUS_OFF:
179 dev_dbg(omap->dev, "VBUS Disconnect\n");
180
181 val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
182 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
183 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
184 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
185 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
186 | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
187 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
188 break;
189
190 default:
191 dev_dbg(omap->dev, "ID float\n");
192 }
193
194 return;
195}
196EXPORT_SYMBOL_GPL(dwc3_omap_mailbox);
197
198static int dwc3_omap_register_phys(struct dwc3_omap *omap)
199{
200 struct nop_usb_xceiv_platform_data pdata;
201 struct platform_device *pdev;
202 int ret;
203
204 memset(&pdata, 0x00, sizeof(pdata));
205
206 pdev = platform_device_alloc("nop_usb_xceiv", PLATFORM_DEVID_AUTO);
207 if (!pdev)
208 return -ENOMEM;
209
210 omap->usb2_phy = pdev;
211 pdata.type = USB_PHY_TYPE_USB2;
212
213 ret = platform_device_add_data(omap->usb2_phy, &pdata, sizeof(pdata));
214 if (ret)
215 goto err1;
216
217 pdev = platform_device_alloc("nop_usb_xceiv", PLATFORM_DEVID_AUTO);
218 if (!pdev) {
219 ret = -ENOMEM;
220 goto err1;
221 }
222
223 omap->usb3_phy = pdev;
224 pdata.type = USB_PHY_TYPE_USB3;
225
226 ret = platform_device_add_data(omap->usb3_phy, &pdata, sizeof(pdata));
227 if (ret)
228 goto err2;
229
230 ret = platform_device_add(omap->usb2_phy);
231 if (ret)
232 goto err2;
233
234 ret = platform_device_add(omap->usb3_phy);
235 if (ret)
236 goto err3;
237
238 return 0;
239
240err3:
241 platform_device_del(omap->usb2_phy);
242
243err2:
244 platform_device_put(omap->usb3_phy);
245
246err1:
247 platform_device_put(omap->usb2_phy);
248
249 return ret;
250}
251
252static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
253{
254 struct dwc3_omap *omap = _omap;
255 u32 reg;
256
257 spin_lock(&omap->lock);
258
259 reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_1);
260
261 if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
262 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
263 omap->dma_status = false;
264 }
265
266 if (reg & USBOTGSS_IRQ1_OEVT)
267 dev_dbg(omap->dev, "OTG Event\n");
268
269 if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
270 dev_dbg(omap->dev, "DRVVBUS Rise\n");
271
272 if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
273 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
274
275 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
276 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
277
278 if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
279 dev_dbg(omap->dev, "IDPULLUP Rise\n");
280
281 if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
282 dev_dbg(omap->dev, "DRVVBUS Fall\n");
283
284 if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
285 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
286
287 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
288 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
289
290 if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
291 dev_dbg(omap->dev, "IDPULLUP Fall\n");
292
293 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);
294
295 reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0);
296 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);
297
298 spin_unlock(&omap->lock);
299
300 return IRQ_HANDLED;
301}
302
303static int dwc3_omap_remove_core(struct device *dev, void *c)
304{
305 struct platform_device *pdev = to_platform_device(dev);
306
307 platform_device_unregister(pdev);
308
309 return 0;
310}
311
312static int dwc3_omap_probe(struct platform_device *pdev)
313{
314 struct dwc3_omap_data *pdata = pdev->dev.platform_data;
315 struct device_node *node = pdev->dev.of_node;
316
317 struct dwc3_omap *omap;
318 struct resource *res;
319 struct device *dev = &pdev->dev;
320
321 int size;
322 int ret = -ENOMEM;
323 int irq;
324
325 const u32 *utmi_mode;
326 u32 reg;
327
328 void __iomem *base;
329 void *context;
330
331 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
332 if (!omap) {
333 dev_err(dev, "not enough memory\n");
334 return -ENOMEM;
335 }
336
337 platform_set_drvdata(pdev, omap);
338
339 irq = platform_get_irq(pdev, 1);
340 if (irq < 0) {
341 dev_err(dev, "missing IRQ resource\n");
342 return -EINVAL;
343 }
344
345 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
346 if (!res) {
347 dev_err(dev, "missing memory base resource\n");
348 return -EINVAL;
349 }
350
351 base = devm_ioremap_nocache(dev, res->start, resource_size(res));
352 if (!base) {
353 dev_err(dev, "ioremap failed\n");
354 return -ENOMEM;
355 }
356
357 ret = dwc3_omap_register_phys(omap);
358 if (ret) {
359 dev_err(dev, "couldn't register PHYs\n");
360 return ret;
361 }
362
363 context = devm_kzalloc(dev, resource_size(res), GFP_KERNEL);
364 if (!context) {
365 dev_err(dev, "couldn't allocate dwc3 context memory\n");
366 return -ENOMEM;
367 }
368
369 spin_lock_init(&omap->lock);
370
371 omap->resource_size = resource_size(res);
372 omap->context = context;
373 omap->dev = dev;
374 omap->irq = irq;
375 omap->base = base;
376
377 /*
378 * REVISIT if we ever have two instances of the wrapper, we will be
379 * in big trouble
380 */
381 _omap = omap;
382
383 pm_runtime_enable(dev);
384 ret = pm_runtime_get_sync(dev);
385 if (ret < 0) {
386 dev_err(dev, "get_sync failed with err %d\n", ret);
387 return ret;
388 }
389
390 reg = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
391
392 utmi_mode = of_get_property(node, "utmi-mode", &size);
393 if (utmi_mode && size == sizeof(*utmi_mode)) {
394 reg |= *utmi_mode;
395 } else {
396 if (!pdata) {
397 dev_dbg(dev, "missing platform data\n");
398 } else {
399 switch (pdata->utmi_mode) {
400 case DWC3_OMAP_UTMI_MODE_SW:
401 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
402 break;
403 case DWC3_OMAP_UTMI_MODE_HW:
404 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
405 break;
406 default:
407 dev_dbg(dev, "UNKNOWN utmi mode %d\n",
408 pdata->utmi_mode);
409 }
410 }
411 }
412
413 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);
414
415 /* check the DMA Status */
416 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
417 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
418
419 ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
420 "dwc3-omap", omap);
421 if (ret) {
422 dev_err(dev, "failed to request IRQ #%d --> %d\n",
423 omap->irq, ret);
424 return ret;
425 }
426
427 /* enable all IRQs */
428 reg = USBOTGSS_IRQO_COREIRQ_ST;
429 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);
430
431 reg = (USBOTGSS_IRQ1_OEVT |
432 USBOTGSS_IRQ1_DRVVBUS_RISE |
433 USBOTGSS_IRQ1_CHRGVBUS_RISE |
434 USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
435 USBOTGSS_IRQ1_IDPULLUP_RISE |
436 USBOTGSS_IRQ1_DRVVBUS_FALL |
437 USBOTGSS_IRQ1_CHRGVBUS_FALL |
438 USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
439 USBOTGSS_IRQ1_IDPULLUP_FALL);
440
441 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
442
443 if (node) {
444 ret = of_platform_populate(node, NULL, NULL, dev);
445 if (ret) {
446 dev_err(&pdev->dev,
447 "failed to add create dwc3 core\n");
448 return ret;
449 }
450 }
451
452 return 0;
453}
454
455static int dwc3_omap_remove(struct platform_device *pdev)
456{
457 struct dwc3_omap *omap = platform_get_drvdata(pdev);
458
459 platform_device_unregister(omap->usb2_phy);
460 platform_device_unregister(omap->usb3_phy);
461 pm_runtime_put_sync(&pdev->dev);
462 pm_runtime_disable(&pdev->dev);
463 device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);
464
465 return 0;
466}
467
468static const struct of_device_id of_dwc3_matach[] = {
469 {
470 "ti,dwc3",
471 },
472 { },
473};
474MODULE_DEVICE_TABLE(of, of_dwc3_matach);
475
476static struct platform_driver dwc3_omap_driver = {
477 .probe = dwc3_omap_probe,
478 .remove = dwc3_omap_remove,
479 .driver = {
480 .name = "omap-dwc3",
481 .of_match_table = of_dwc3_matach,
482 },
483};
484
485module_platform_driver(dwc3_omap_driver);
486
487MODULE_ALIAS("platform:omap-dwc3");
488MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
489MODULE_LICENSE("Dual BSD/GPL");
490MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");