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Linux kernel mirror (for testing)
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1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28
29/* Linux PRO/1000 Ethernet Driver main header file */
30
31#ifndef _IGB_H_
32#define _IGB_H_
33
34#include "e1000_mac.h"
35#include "e1000_82575.h"
36
37#include <linux/clocksource.h>
38#include <linux/net_tstamp.h>
39#include <linux/ptp_clock_kernel.h>
40#include <linux/bitops.h>
41#include <linux/if_vlan.h>
42
43struct igb_adapter;
44
45#define E1000_PCS_CFG_IGN_SD 1
46
47/* Interrupt defines */
48#define IGB_START_ITR 648 /* ~6000 ints/sec */
49#define IGB_4K_ITR 980
50#define IGB_20K_ITR 196
51#define IGB_70K_ITR 56
52
53/* TX/RX descriptor defines */
54#define IGB_DEFAULT_TXD 256
55#define IGB_DEFAULT_TX_WORK 128
56#define IGB_MIN_TXD 80
57#define IGB_MAX_TXD 4096
58
59#define IGB_DEFAULT_RXD 256
60#define IGB_MIN_RXD 80
61#define IGB_MAX_RXD 4096
62
63#define IGB_DEFAULT_ITR 3 /* dynamic */
64#define IGB_MAX_ITR_USECS 10000
65#define IGB_MIN_ITR_USECS 10
66#define NON_Q_VECTORS 1
67#define MAX_Q_VECTORS 8
68
69/* Transmit and receive queues */
70#define IGB_MAX_RX_QUEUES 8
71#define IGB_MAX_RX_QUEUES_82575 4
72#define IGB_MAX_RX_QUEUES_I211 2
73#define IGB_MAX_TX_QUEUES 8
74#define IGB_MAX_VF_MC_ENTRIES 30
75#define IGB_MAX_VF_FUNCTIONS 8
76#define IGB_MAX_VFTA_ENTRIES 128
77#define IGB_82576_VF_DEV_ID 0x10CA
78#define IGB_I350_VF_DEV_ID 0x1520
79
80/* NVM version defines */
81#define IGB_MAJOR_MASK 0xF000
82#define IGB_MINOR_MASK 0x0FF0
83#define IGB_BUILD_MASK 0x000F
84#define IGB_COMB_VER_MASK 0x00FF
85#define IGB_MAJOR_SHIFT 12
86#define IGB_MINOR_SHIFT 4
87#define IGB_COMB_VER_SHFT 8
88#define IGB_NVM_VER_INVALID 0xFFFF
89#define IGB_ETRACK_SHIFT 16
90#define NVM_ETRACK_WORD 0x0042
91#define NVM_COMB_VER_OFF 0x0083
92#define NVM_COMB_VER_PTR 0x003d
93
94struct vf_data_storage {
95 unsigned char vf_mac_addresses[ETH_ALEN];
96 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
97 u16 num_vf_mc_hashes;
98 u16 vlans_enabled;
99 u32 flags;
100 unsigned long last_nack;
101 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
102 u16 pf_qos;
103 u16 tx_rate;
104};
105
106#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
107#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
108#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
109#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
110
111/* RX descriptor control thresholds.
112 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
113 * descriptors available in its onboard memory.
114 * Setting this to 0 disables RX descriptor prefetch.
115 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
116 * available in host memory.
117 * If PTHRESH is 0, this should also be 0.
118 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
119 * descriptors until either it has this many to write back, or the
120 * ITR timer expires.
121 */
122#define IGB_RX_PTHRESH 8
123#define IGB_RX_HTHRESH 8
124#define IGB_TX_PTHRESH 8
125#define IGB_TX_HTHRESH 1
126#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
127 adapter->msix_entries) ? 1 : 4)
128#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
129 adapter->msix_entries) ? 1 : 16)
130
131/* this is the size past which hardware will drop packets when setting LPE=0 */
132#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
133
134/* Supported Rx Buffer Sizes */
135#define IGB_RXBUFFER_256 256
136#define IGB_RXBUFFER_2048 2048
137#define IGB_RX_HDR_LEN IGB_RXBUFFER_256
138#define IGB_RX_BUFSZ IGB_RXBUFFER_2048
139
140/* How many Tx Descriptors do we need to call netif_wake_queue ? */
141#define IGB_TX_QUEUE_WAKE 16
142/* How many Rx Buffers do we bundle into one write to the hardware ? */
143#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
144
145#define AUTO_ALL_MODES 0
146#define IGB_EEPROM_APME 0x0400
147
148#ifndef IGB_MASTER_SLAVE
149/* Switch to override PHY master/slave setting */
150#define IGB_MASTER_SLAVE e1000_ms_hw_default
151#endif
152
153#define IGB_MNG_VLAN_NONE -1
154
155enum igb_tx_flags {
156 /* cmd_type flags */
157 IGB_TX_FLAGS_VLAN = 0x01,
158 IGB_TX_FLAGS_TSO = 0x02,
159 IGB_TX_FLAGS_TSTAMP = 0x04,
160
161 /* olinfo flags */
162 IGB_TX_FLAGS_IPV4 = 0x10,
163 IGB_TX_FLAGS_CSUM = 0x20,
164};
165
166/* VLAN info */
167#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
168#define IGB_TX_FLAGS_VLAN_SHIFT 16
169
170/* wrapper around a pointer to a socket buffer,
171 * so a DMA handle can be stored along with the buffer */
172struct igb_tx_buffer {
173 union e1000_adv_tx_desc *next_to_watch;
174 unsigned long time_stamp;
175 struct sk_buff *skb;
176 unsigned int bytecount;
177 u16 gso_segs;
178 __be16 protocol;
179 DEFINE_DMA_UNMAP_ADDR(dma);
180 DEFINE_DMA_UNMAP_LEN(len);
181 u32 tx_flags;
182};
183
184struct igb_rx_buffer {
185 dma_addr_t dma;
186 struct page *page;
187 unsigned int page_offset;
188};
189
190struct igb_tx_queue_stats {
191 u64 packets;
192 u64 bytes;
193 u64 restart_queue;
194 u64 restart_queue2;
195};
196
197struct igb_rx_queue_stats {
198 u64 packets;
199 u64 bytes;
200 u64 drops;
201 u64 csum_err;
202 u64 alloc_failed;
203};
204
205struct igb_ring_container {
206 struct igb_ring *ring; /* pointer to linked list of rings */
207 unsigned int total_bytes; /* total bytes processed this int */
208 unsigned int total_packets; /* total packets processed this int */
209 u16 work_limit; /* total work allowed per interrupt */
210 u8 count; /* total number of rings in vector */
211 u8 itr; /* current ITR setting for ring */
212};
213
214struct igb_ring {
215 struct igb_q_vector *q_vector; /* backlink to q_vector */
216 struct net_device *netdev; /* back pointer to net_device */
217 struct device *dev; /* device pointer for dma mapping */
218 union { /* array of buffer info structs */
219 struct igb_tx_buffer *tx_buffer_info;
220 struct igb_rx_buffer *rx_buffer_info;
221 };
222 void *desc; /* descriptor ring memory */
223 unsigned long flags; /* ring specific flags */
224 void __iomem *tail; /* pointer to ring tail register */
225 dma_addr_t dma; /* phys address of the ring */
226 unsigned int size; /* length of desc. ring in bytes */
227
228 u16 count; /* number of desc. in the ring */
229 u8 queue_index; /* logical index of the ring*/
230 u8 reg_idx; /* physical index of the ring */
231
232 /* everything past this point are written often */
233 u16 next_to_clean;
234 u16 next_to_use;
235 u16 next_to_alloc;
236
237 union {
238 /* TX */
239 struct {
240 struct igb_tx_queue_stats tx_stats;
241 struct u64_stats_sync tx_syncp;
242 struct u64_stats_sync tx_syncp2;
243 };
244 /* RX */
245 struct {
246 struct sk_buff *skb;
247 struct igb_rx_queue_stats rx_stats;
248 struct u64_stats_sync rx_syncp;
249 };
250 };
251} ____cacheline_internodealigned_in_smp;
252
253struct igb_q_vector {
254 struct igb_adapter *adapter; /* backlink */
255 int cpu; /* CPU for DCA */
256 u32 eims_value; /* EIMS mask value */
257
258 u16 itr_val;
259 u8 set_itr;
260 void __iomem *itr_register;
261
262 struct igb_ring_container rx, tx;
263
264 struct napi_struct napi;
265 struct rcu_head rcu; /* to avoid race with update stats on free */
266 char name[IFNAMSIZ + 9];
267
268 /* for dynamic allocation of rings associated with this q_vector */
269 struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
270};
271
272enum e1000_ring_flags_t {
273 IGB_RING_FLAG_RX_SCTP_CSUM,
274 IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
275 IGB_RING_FLAG_TX_CTX_IDX,
276 IGB_RING_FLAG_TX_DETECT_HANG
277};
278
279#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
280
281#define IGB_RX_DESC(R, i) \
282 (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
283#define IGB_TX_DESC(R, i) \
284 (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
285#define IGB_TX_CTXTDESC(R, i) \
286 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
287
288/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
289static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
290 const u32 stat_err_bits)
291{
292 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
293}
294
295/* igb_desc_unused - calculate if we have unused descriptors */
296static inline int igb_desc_unused(struct igb_ring *ring)
297{
298 if (ring->next_to_clean > ring->next_to_use)
299 return ring->next_to_clean - ring->next_to_use - 1;
300
301 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
302}
303
304/* board specific private data structure */
305struct igb_adapter {
306 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
307
308 struct net_device *netdev;
309
310 unsigned long state;
311 unsigned int flags;
312
313 unsigned int num_q_vectors;
314 struct msix_entry *msix_entries;
315
316 /* Interrupt Throttle Rate */
317 u32 rx_itr_setting;
318 u32 tx_itr_setting;
319 u16 tx_itr;
320 u16 rx_itr;
321
322 /* TX */
323 u16 tx_work_limit;
324 u32 tx_timeout_count;
325 int num_tx_queues;
326 struct igb_ring *tx_ring[16];
327
328 /* RX */
329 int num_rx_queues;
330 struct igb_ring *rx_ring[16];
331
332 u32 max_frame_size;
333 u32 min_frame_size;
334
335 struct timer_list watchdog_timer;
336 struct timer_list phy_info_timer;
337
338 u16 mng_vlan_id;
339 u32 bd_number;
340 u32 wol;
341 u32 en_mng_pt;
342 u16 link_speed;
343 u16 link_duplex;
344
345 struct work_struct reset_task;
346 struct work_struct watchdog_task;
347 bool fc_autoneg;
348 u8 tx_timeout_factor;
349 struct timer_list blink_timer;
350 unsigned long led_status;
351
352 /* OS defined structs */
353 struct pci_dev *pdev;
354
355 spinlock_t stats64_lock;
356 struct rtnl_link_stats64 stats64;
357
358 /* structs defined in e1000_hw.h */
359 struct e1000_hw hw;
360 struct e1000_hw_stats stats;
361 struct e1000_phy_info phy_info;
362 struct e1000_phy_stats phy_stats;
363
364 u32 test_icr;
365 struct igb_ring test_tx_ring;
366 struct igb_ring test_rx_ring;
367
368 int msg_enable;
369
370 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
371 u32 eims_enable_mask;
372 u32 eims_other;
373
374 /* to not mess up cache alignment, always add to the bottom */
375 u16 tx_ring_count;
376 u16 rx_ring_count;
377 unsigned int vfs_allocated_count;
378 struct vf_data_storage *vf_data;
379 int vf_rate_link_speed;
380 u32 rss_queues;
381 u32 wvbr;
382 u32 *shadow_vfta;
383
384 struct ptp_clock *ptp_clock;
385 struct ptp_clock_info ptp_caps;
386 struct delayed_work ptp_overflow_work;
387 struct work_struct ptp_tx_work;
388 struct sk_buff *ptp_tx_skb;
389 spinlock_t tmreg_lock;
390 struct cyclecounter cc;
391 struct timecounter tc;
392
393 char fw_version[32];
394};
395
396#define IGB_FLAG_HAS_MSI (1 << 0)
397#define IGB_FLAG_DCA_ENABLED (1 << 1)
398#define IGB_FLAG_QUAD_PORT_A (1 << 2)
399#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
400#define IGB_FLAG_DMAC (1 << 4)
401#define IGB_FLAG_PTP (1 << 5)
402#define IGB_FLAG_RSS_FIELD_IPV4_UDP (1 << 6)
403#define IGB_FLAG_RSS_FIELD_IPV6_UDP (1 << 7)
404#define IGB_FLAG_WOL_SUPPORTED (1 << 8)
405
406/* DMA Coalescing defines */
407#define IGB_MIN_TXPBSIZE 20408
408#define IGB_TX_BUF_4096 4096
409#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
410
411#define IGB_82576_TSYNC_SHIFT 19
412#define IGB_TS_HDR_LEN 16
413enum e1000_state_t {
414 __IGB_TESTING,
415 __IGB_RESETTING,
416 __IGB_DOWN
417};
418
419enum igb_boards {
420 board_82575,
421};
422
423extern char igb_driver_name[];
424extern char igb_driver_version[];
425
426extern int igb_up(struct igb_adapter *);
427extern void igb_down(struct igb_adapter *);
428extern void igb_reinit_locked(struct igb_adapter *);
429extern void igb_reset(struct igb_adapter *);
430extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
431extern int igb_setup_tx_resources(struct igb_ring *);
432extern int igb_setup_rx_resources(struct igb_ring *);
433extern void igb_free_tx_resources(struct igb_ring *);
434extern void igb_free_rx_resources(struct igb_ring *);
435extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
436extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
437extern void igb_setup_tctl(struct igb_adapter *);
438extern void igb_setup_rctl(struct igb_adapter *);
439extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
440extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
441 struct igb_tx_buffer *);
442extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
443extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
444extern bool igb_has_link(struct igb_adapter *adapter);
445extern void igb_set_ethtool_ops(struct net_device *);
446extern void igb_power_up_link(struct igb_adapter *);
447extern void igb_set_fw_version(struct igb_adapter *);
448extern void igb_ptp_init(struct igb_adapter *adapter);
449extern void igb_ptp_stop(struct igb_adapter *adapter);
450extern void igb_ptp_reset(struct igb_adapter *adapter);
451extern void igb_ptp_tx_work(struct work_struct *work);
452extern void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
453extern void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
454 struct sk_buff *skb);
455extern void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
456 unsigned char *va,
457 struct sk_buff *skb);
458static inline void igb_ptp_rx_hwtstamp(struct igb_q_vector *q_vector,
459 union e1000_adv_rx_desc *rx_desc,
460 struct sk_buff *skb)
461{
462 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
463 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
464 igb_ptp_rx_rgtstamp(q_vector, skb);
465}
466
467extern int igb_ptp_hwtstamp_ioctl(struct net_device *netdev,
468 struct ifreq *ifr, int cmd);
469
470static inline s32 igb_reset_phy(struct e1000_hw *hw)
471{
472 if (hw->phy.ops.reset)
473 return hw->phy.ops.reset(hw);
474
475 return 0;
476}
477
478static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
479{
480 if (hw->phy.ops.read_reg)
481 return hw->phy.ops.read_reg(hw, offset, data);
482
483 return 0;
484}
485
486static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
487{
488 if (hw->phy.ops.write_reg)
489 return hw->phy.ops.write_reg(hw, offset, data);
490
491 return 0;
492}
493
494static inline s32 igb_get_phy_info(struct e1000_hw *hw)
495{
496 if (hw->phy.ops.get_phy_info)
497 return hw->phy.ops.get_phy_info(hw);
498
499 return 0;
500}
501
502static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
503{
504 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
505}
506
507#endif /* _IGB_H_ */