tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#include <drm/drmP.h>
27#include <drm/radeon_drm.h>
28#include "radeon.h"
29
30#include "r600d.h"
31#include "r600_blit_shaders.h"
32#include "radeon_blit_common.h"
33
34/* emits 21 on rv770+, 23 on r600 */
35static void
36set_render_target(struct radeon_device *rdev, int format,
37 int w, int h, u64 gpu_addr)
38{
39 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
40 u32 cb_color_info;
41 int pitch, slice;
42
43 h = ALIGN(h, 8);
44 if (h < 8)
45 h = 8;
46
47 cb_color_info = CB_FORMAT(format) |
48 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
49 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
50 pitch = (w / 8) - 1;
51 slice = ((w * h) / 64) - 1;
52
53 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
54 radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
55 radeon_ring_write(ring, gpu_addr >> 8);
56
57 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
58 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
59 radeon_ring_write(ring, 2 << 0);
60 }
61
62 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
63 radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
64 radeon_ring_write(ring, (pitch << 0) | (slice << 10));
65
66 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
67 radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
68 radeon_ring_write(ring, 0);
69
70 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
71 radeon_ring_write(ring, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
72 radeon_ring_write(ring, cb_color_info);
73
74 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
75 radeon_ring_write(ring, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
76 radeon_ring_write(ring, 0);
77
78 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
79 radeon_ring_write(ring, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
80 radeon_ring_write(ring, 0);
81
82 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
83 radeon_ring_write(ring, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
84 radeon_ring_write(ring, 0);
85}
86
87/* emits 5dw */
88static void
89cp_set_surface_sync(struct radeon_device *rdev,
90 u32 sync_type, u32 size,
91 u64 mc_addr)
92{
93 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
94 u32 cp_coher_size;
95
96 if (size == 0xffffffff)
97 cp_coher_size = 0xffffffff;
98 else
99 cp_coher_size = ((size + 255) >> 8);
100
101 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
102 radeon_ring_write(ring, sync_type);
103 radeon_ring_write(ring, cp_coher_size);
104 radeon_ring_write(ring, mc_addr >> 8);
105 radeon_ring_write(ring, 10); /* poll interval */
106}
107
108/* emits 21dw + 1 surface sync = 26dw */
109static void
110set_shaders(struct radeon_device *rdev)
111{
112 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
113 u64 gpu_addr;
114 u32 sq_pgm_resources;
115
116 /* setup shader regs */
117 sq_pgm_resources = (1 << 0);
118
119 /* VS */
120 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
121 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
122 radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
123 radeon_ring_write(ring, gpu_addr >> 8);
124
125 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
126 radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
127 radeon_ring_write(ring, sq_pgm_resources);
128
129 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
130 radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
131 radeon_ring_write(ring, 0);
132
133 /* PS */
134 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
135 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
136 radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
137 radeon_ring_write(ring, gpu_addr >> 8);
138
139 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
140 radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
141 radeon_ring_write(ring, sq_pgm_resources | (1 << 28));
142
143 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
144 radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
145 radeon_ring_write(ring, 2);
146
147 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
148 radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
149 radeon_ring_write(ring, 0);
150
151 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
152 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
153}
154
155/* emits 9 + 1 sync (5) = 14*/
156static void
157set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
158{
159 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
160 u32 sq_vtx_constant_word2;
161
162 sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
163 SQ_VTXC_STRIDE(16);
164#ifdef __BIG_ENDIAN
165 sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
166#endif
167
168 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
169 radeon_ring_write(ring, 0x460);
170 radeon_ring_write(ring, gpu_addr & 0xffffffff);
171 radeon_ring_write(ring, 48 - 1);
172 radeon_ring_write(ring, sq_vtx_constant_word2);
173 radeon_ring_write(ring, 1 << 0);
174 radeon_ring_write(ring, 0);
175 radeon_ring_write(ring, 0);
176 radeon_ring_write(ring, SQ_TEX_VTX_VALID_BUFFER << 30);
177
178 if ((rdev->family == CHIP_RV610) ||
179 (rdev->family == CHIP_RV620) ||
180 (rdev->family == CHIP_RS780) ||
181 (rdev->family == CHIP_RS880) ||
182 (rdev->family == CHIP_RV710))
183 cp_set_surface_sync(rdev,
184 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
185 else
186 cp_set_surface_sync(rdev,
187 PACKET3_VC_ACTION_ENA, 48, gpu_addr);
188}
189
190/* emits 9 */
191static void
192set_tex_resource(struct radeon_device *rdev,
193 int format, int w, int h, int pitch,
194 u64 gpu_addr, u32 size)
195{
196 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
197 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
198
199 if (h < 1)
200 h = 1;
201
202 sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) |
203 S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
204 sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) |
205 S_038000_TEX_WIDTH(w - 1);
206
207 sq_tex_resource_word1 = S_038004_DATA_FORMAT(format);
208 sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1);
209
210 sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) |
211 S_038010_DST_SEL_X(SQ_SEL_X) |
212 S_038010_DST_SEL_Y(SQ_SEL_Y) |
213 S_038010_DST_SEL_Z(SQ_SEL_Z) |
214 S_038010_DST_SEL_W(SQ_SEL_W);
215
216 cp_set_surface_sync(rdev,
217 PACKET3_TC_ACTION_ENA, size, gpu_addr);
218
219 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
220 radeon_ring_write(ring, 0);
221 radeon_ring_write(ring, sq_tex_resource_word0);
222 radeon_ring_write(ring, sq_tex_resource_word1);
223 radeon_ring_write(ring, gpu_addr >> 8);
224 radeon_ring_write(ring, gpu_addr >> 8);
225 radeon_ring_write(ring, sq_tex_resource_word4);
226 radeon_ring_write(ring, 0);
227 radeon_ring_write(ring, SQ_TEX_VTX_VALID_TEXTURE << 30);
228}
229
230/* emits 12 */
231static void
232set_scissors(struct radeon_device *rdev, int x1, int y1,
233 int x2, int y2)
234{
235 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
236 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
237 radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
238 radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
239 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
240
241 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
242 radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
243 radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
244 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
245
246 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
247 radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
248 radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
249 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
250}
251
252/* emits 10 */
253static void
254draw_auto(struct radeon_device *rdev)
255{
256 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
257 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
258 radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
259 radeon_ring_write(ring, DI_PT_RECTLIST);
260
261 radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
262 radeon_ring_write(ring,
263#ifdef __BIG_ENDIAN
264 (2 << 2) |
265#endif
266 DI_INDEX_SIZE_16_BIT);
267
268 radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
269 radeon_ring_write(ring, 1);
270
271 radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
272 radeon_ring_write(ring, 3);
273 radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
274
275}
276
277/* emits 14 */
278static void
279set_default_state(struct radeon_device *rdev)
280{
281 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
282 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
283 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
284 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
285 int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
286 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
287 u64 gpu_addr;
288 int dwords;
289
290 switch (rdev->family) {
291 case CHIP_R600:
292 num_ps_gprs = 192;
293 num_vs_gprs = 56;
294 num_temp_gprs = 4;
295 num_gs_gprs = 0;
296 num_es_gprs = 0;
297 num_ps_threads = 136;
298 num_vs_threads = 48;
299 num_gs_threads = 4;
300 num_es_threads = 4;
301 num_ps_stack_entries = 128;
302 num_vs_stack_entries = 128;
303 num_gs_stack_entries = 0;
304 num_es_stack_entries = 0;
305 break;
306 case CHIP_RV630:
307 case CHIP_RV635:
308 num_ps_gprs = 84;
309 num_vs_gprs = 36;
310 num_temp_gprs = 4;
311 num_gs_gprs = 0;
312 num_es_gprs = 0;
313 num_ps_threads = 144;
314 num_vs_threads = 40;
315 num_gs_threads = 4;
316 num_es_threads = 4;
317 num_ps_stack_entries = 40;
318 num_vs_stack_entries = 40;
319 num_gs_stack_entries = 32;
320 num_es_stack_entries = 16;
321 break;
322 case CHIP_RV610:
323 case CHIP_RV620:
324 case CHIP_RS780:
325 case CHIP_RS880:
326 default:
327 num_ps_gprs = 84;
328 num_vs_gprs = 36;
329 num_temp_gprs = 4;
330 num_gs_gprs = 0;
331 num_es_gprs = 0;
332 num_ps_threads = 136;
333 num_vs_threads = 48;
334 num_gs_threads = 4;
335 num_es_threads = 4;
336 num_ps_stack_entries = 40;
337 num_vs_stack_entries = 40;
338 num_gs_stack_entries = 32;
339 num_es_stack_entries = 16;
340 break;
341 case CHIP_RV670:
342 num_ps_gprs = 144;
343 num_vs_gprs = 40;
344 num_temp_gprs = 4;
345 num_gs_gprs = 0;
346 num_es_gprs = 0;
347 num_ps_threads = 136;
348 num_vs_threads = 48;
349 num_gs_threads = 4;
350 num_es_threads = 4;
351 num_ps_stack_entries = 40;
352 num_vs_stack_entries = 40;
353 num_gs_stack_entries = 32;
354 num_es_stack_entries = 16;
355 break;
356 case CHIP_RV770:
357 num_ps_gprs = 192;
358 num_vs_gprs = 56;
359 num_temp_gprs = 4;
360 num_gs_gprs = 0;
361 num_es_gprs = 0;
362 num_ps_threads = 188;
363 num_vs_threads = 60;
364 num_gs_threads = 0;
365 num_es_threads = 0;
366 num_ps_stack_entries = 256;
367 num_vs_stack_entries = 256;
368 num_gs_stack_entries = 0;
369 num_es_stack_entries = 0;
370 break;
371 case CHIP_RV730:
372 case CHIP_RV740:
373 num_ps_gprs = 84;
374 num_vs_gprs = 36;
375 num_temp_gprs = 4;
376 num_gs_gprs = 0;
377 num_es_gprs = 0;
378 num_ps_threads = 188;
379 num_vs_threads = 60;
380 num_gs_threads = 0;
381 num_es_threads = 0;
382 num_ps_stack_entries = 128;
383 num_vs_stack_entries = 128;
384 num_gs_stack_entries = 0;
385 num_es_stack_entries = 0;
386 break;
387 case CHIP_RV710:
388 num_ps_gprs = 192;
389 num_vs_gprs = 56;
390 num_temp_gprs = 4;
391 num_gs_gprs = 0;
392 num_es_gprs = 0;
393 num_ps_threads = 144;
394 num_vs_threads = 48;
395 num_gs_threads = 0;
396 num_es_threads = 0;
397 num_ps_stack_entries = 128;
398 num_vs_stack_entries = 128;
399 num_gs_stack_entries = 0;
400 num_es_stack_entries = 0;
401 break;
402 }
403
404 if ((rdev->family == CHIP_RV610) ||
405 (rdev->family == CHIP_RV620) ||
406 (rdev->family == CHIP_RS780) ||
407 (rdev->family == CHIP_RS880) ||
408 (rdev->family == CHIP_RV710))
409 sq_config = 0;
410 else
411 sq_config = VC_ENABLE;
412
413 sq_config |= (DX9_CONSTS |
414 ALU_INST_PREFER_VECTOR |
415 PS_PRIO(0) |
416 VS_PRIO(1) |
417 GS_PRIO(2) |
418 ES_PRIO(3));
419
420 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
421 NUM_VS_GPRS(num_vs_gprs) |
422 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
423 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
424 NUM_ES_GPRS(num_es_gprs));
425 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
426 NUM_VS_THREADS(num_vs_threads) |
427 NUM_GS_THREADS(num_gs_threads) |
428 NUM_ES_THREADS(num_es_threads));
429 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
430 NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
431 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
432 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
433
434 /* emit an IB pointing at default state */
435 dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
436 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
437 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
438 radeon_ring_write(ring,
439#ifdef __BIG_ENDIAN
440 (2 << 0) |
441#endif
442 (gpu_addr & 0xFFFFFFFC));
443 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
444 radeon_ring_write(ring, dwords);
445
446 /* SQ config */
447 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6));
448 radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
449 radeon_ring_write(ring, sq_config);
450 radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
451 radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
452 radeon_ring_write(ring, sq_thread_resource_mgmt);
453 radeon_ring_write(ring, sq_stack_resource_mgmt_1);
454 radeon_ring_write(ring, sq_stack_resource_mgmt_2);
455}
456
457int r600_blit_init(struct radeon_device *rdev)
458{
459 u32 obj_size;
460 int i, r, dwords;
461 void *ptr;
462 u32 packet2s[16];
463 int num_packet2s = 0;
464
465 rdev->r600_blit.primitives.set_render_target = set_render_target;
466 rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
467 rdev->r600_blit.primitives.set_shaders = set_shaders;
468 rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
469 rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
470 rdev->r600_blit.primitives.set_scissors = set_scissors;
471 rdev->r600_blit.primitives.draw_auto = draw_auto;
472 rdev->r600_blit.primitives.set_default_state = set_default_state;
473
474 rdev->r600_blit.ring_size_common = 8; /* sync semaphore */
475 rdev->r600_blit.ring_size_common += 40; /* shaders + def state */
476 rdev->r600_blit.ring_size_common += 5; /* done copy */
477 rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
478
479 rdev->r600_blit.ring_size_per_loop = 76;
480 /* set_render_target emits 2 extra dwords on rv6xx */
481 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
482 rdev->r600_blit.ring_size_per_loop += 2;
483
484 rdev->r600_blit.max_dim = 8192;
485
486 rdev->r600_blit.state_offset = 0;
487
488 if (rdev->family >= CHIP_RV770)
489 rdev->r600_blit.state_len = r7xx_default_size;
490 else
491 rdev->r600_blit.state_len = r6xx_default_size;
492
493 dwords = rdev->r600_blit.state_len;
494 while (dwords & 0xf) {
495 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
496 dwords++;
497 }
498
499 obj_size = dwords * 4;
500 obj_size = ALIGN(obj_size, 256);
501
502 rdev->r600_blit.vs_offset = obj_size;
503 obj_size += r6xx_vs_size * 4;
504 obj_size = ALIGN(obj_size, 256);
505
506 rdev->r600_blit.ps_offset = obj_size;
507 obj_size += r6xx_ps_size * 4;
508 obj_size = ALIGN(obj_size, 256);
509
510 /* pin copy shader into vram if not already initialized */
511 if (rdev->r600_blit.shader_obj == NULL) {
512 r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true,
513 RADEON_GEM_DOMAIN_VRAM,
514 NULL, &rdev->r600_blit.shader_obj);
515 if (r) {
516 DRM_ERROR("r600 failed to allocate shader\n");
517 return r;
518 }
519
520 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
521 if (unlikely(r != 0))
522 return r;
523 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
524 &rdev->r600_blit.shader_gpu_addr);
525 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
526 if (r) {
527 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
528 return r;
529 }
530 }
531
532 DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
533 obj_size,
534 rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
535
536 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
537 if (unlikely(r != 0))
538 return r;
539 r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
540 if (r) {
541 DRM_ERROR("failed to map blit object %d\n", r);
542 return r;
543 }
544 if (rdev->family >= CHIP_RV770)
545 memcpy_toio(ptr + rdev->r600_blit.state_offset,
546 r7xx_default_state, rdev->r600_blit.state_len * 4);
547 else
548 memcpy_toio(ptr + rdev->r600_blit.state_offset,
549 r6xx_default_state, rdev->r600_blit.state_len * 4);
550 if (num_packet2s)
551 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
552 packet2s, num_packet2s * 4);
553 for (i = 0; i < r6xx_vs_size; i++)
554 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]);
555 for (i = 0; i < r6xx_ps_size; i++)
556 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]);
557 radeon_bo_kunmap(rdev->r600_blit.shader_obj);
558 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
559
560 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
561 return 0;
562}
563
564void r600_blit_fini(struct radeon_device *rdev)
565{
566 int r;
567
568 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
569 if (rdev->r600_blit.shader_obj == NULL)
570 return;
571 /* If we can't reserve the bo, unref should be enough to destroy
572 * it when it becomes idle.
573 */
574 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
575 if (!r) {
576 radeon_bo_unpin(rdev->r600_blit.shader_obj);
577 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
578 }
579 radeon_bo_unref(&rdev->r600_blit.shader_obj);
580}
581
582static unsigned r600_blit_create_rect(unsigned num_gpu_pages,
583 int *width, int *height, int max_dim)
584{
585 unsigned max_pages;
586 unsigned pages = num_gpu_pages;
587 int w, h;
588
589 if (num_gpu_pages == 0) {
590 /* not supposed to be called with no pages, but just in case */
591 h = 0;
592 w = 0;
593 pages = 0;
594 WARN_ON(1);
595 } else {
596 int rect_order = 2;
597 h = RECT_UNIT_H;
598 while (num_gpu_pages / rect_order) {
599 h *= 2;
600 rect_order *= 4;
601 if (h >= max_dim) {
602 h = max_dim;
603 break;
604 }
605 }
606 max_pages = (max_dim * h) / (RECT_UNIT_W * RECT_UNIT_H);
607 if (pages > max_pages)
608 pages = max_pages;
609 w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
610 w = (w / RECT_UNIT_W) * RECT_UNIT_W;
611 pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H);
612 BUG_ON(pages == 0);
613 }
614
615
616 DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages);
617
618 /* return width and height only of the caller wants it */
619 if (height)
620 *height = h;
621 if (width)
622 *width = w;
623
624 return pages;
625}
626
627
628int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
629 struct radeon_fence **fence, struct radeon_sa_bo **vb,
630 struct radeon_semaphore **sem)
631{
632 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
633 int r;
634 int ring_size;
635 int num_loops = 0;
636 int dwords_per_loop = rdev->r600_blit.ring_size_per_loop;
637
638 /* num loops */
639 while (num_gpu_pages) {
640 num_gpu_pages -=
641 r600_blit_create_rect(num_gpu_pages, NULL, NULL,
642 rdev->r600_blit.max_dim);
643 num_loops++;
644 }
645
646 /* 48 bytes for vertex per loop */
647 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, vb,
648 (num_loops*48)+256, 256, true);
649 if (r) {
650 return r;
651 }
652
653 r = radeon_semaphore_create(rdev, sem);
654 if (r) {
655 radeon_sa_bo_free(rdev, vb, NULL);
656 return r;
657 }
658
659 /* calculate number of loops correctly */
660 ring_size = num_loops * dwords_per_loop;
661 ring_size += rdev->r600_blit.ring_size_common;
662 r = radeon_ring_lock(rdev, ring, ring_size);
663 if (r) {
664 radeon_sa_bo_free(rdev, vb, NULL);
665 radeon_semaphore_free(rdev, sem, NULL);
666 return r;
667 }
668
669 if (radeon_fence_need_sync(*fence, RADEON_RING_TYPE_GFX_INDEX)) {
670 radeon_semaphore_sync_rings(rdev, *sem, (*fence)->ring,
671 RADEON_RING_TYPE_GFX_INDEX);
672 radeon_fence_note_sync(*fence, RADEON_RING_TYPE_GFX_INDEX);
673 } else {
674 radeon_semaphore_free(rdev, sem, NULL);
675 }
676
677 rdev->r600_blit.primitives.set_default_state(rdev);
678 rdev->r600_blit.primitives.set_shaders(rdev);
679 return 0;
680}
681
682void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence,
683 struct radeon_sa_bo *vb, struct radeon_semaphore *sem)
684{
685 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
686 int r;
687
688 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
689 if (r) {
690 radeon_ring_unlock_undo(rdev, ring);
691 return;
692 }
693
694 radeon_ring_unlock_commit(rdev, ring);
695 radeon_sa_bo_free(rdev, &vb, *fence);
696 radeon_semaphore_free(rdev, &sem, *fence);
697}
698
699void r600_kms_blit_copy(struct radeon_device *rdev,
700 u64 src_gpu_addr, u64 dst_gpu_addr,
701 unsigned num_gpu_pages,
702 struct radeon_sa_bo *vb)
703{
704 u64 vb_gpu_addr;
705 u32 *vb_cpu_addr;
706
707 DRM_DEBUG("emitting copy %16llx %16llx %d\n",
708 src_gpu_addr, dst_gpu_addr, num_gpu_pages);
709 vb_cpu_addr = (u32 *)radeon_sa_bo_cpu_addr(vb);
710 vb_gpu_addr = radeon_sa_bo_gpu_addr(vb);
711
712 while (num_gpu_pages) {
713 int w, h;
714 unsigned size_in_bytes;
715 unsigned pages_per_loop =
716 r600_blit_create_rect(num_gpu_pages, &w, &h,
717 rdev->r600_blit.max_dim);
718
719 size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE;
720 DRM_DEBUG("rectangle w=%d h=%d\n", w, h);
721
722 vb_cpu_addr[0] = 0;
723 vb_cpu_addr[1] = 0;
724 vb_cpu_addr[2] = 0;
725 vb_cpu_addr[3] = 0;
726
727 vb_cpu_addr[4] = 0;
728 vb_cpu_addr[5] = int2float(h);
729 vb_cpu_addr[6] = 0;
730 vb_cpu_addr[7] = int2float(h);
731
732 vb_cpu_addr[8] = int2float(w);
733 vb_cpu_addr[9] = int2float(h);
734 vb_cpu_addr[10] = int2float(w);
735 vb_cpu_addr[11] = int2float(h);
736
737 rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8,
738 w, h, w, src_gpu_addr, size_in_bytes);
739 rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8,
740 w, h, dst_gpu_addr);
741 rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h);
742 rdev->r600_blit.primitives.set_vtx_resource(rdev, vb_gpu_addr);
743 rdev->r600_blit.primitives.draw_auto(rdev);
744 rdev->r600_blit.primitives.cp_set_surface_sync(rdev,
745 PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
746 size_in_bytes, dst_gpu_addr);
747
748 vb_cpu_addr += 12;
749 vb_gpu_addr += 4*12;
750 src_gpu_addr += size_in_bytes;
751 dst_gpu_addr += size_in_bytes;
752 num_gpu_pages -= pages_per_loop;
753 }
754}