tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2009
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * Description:
6 * Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
7 * driver to function correctly on these systems.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/fsl_devices.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20
21static struct clk *mxc_ahb_clk;
22static struct clk *mxc_per_clk;
23static struct clk *mxc_ipg_clk;
24
25/* workaround ENGcm09152 for i.MX35 */
26#define MX35_USBPHYCTRL_OFFSET 0x600
27#define USBPHYCTRL_OTGBASE_OFFSET 0x8
28#define USBPHYCTRL_EVDO (1 << 23)
29
30int fsl_udc_clk_init(struct platform_device *pdev)
31{
32 struct fsl_usb2_platform_data *pdata;
33 unsigned long freq;
34 int ret;
35
36 pdata = pdev->dev.platform_data;
37
38 mxc_ipg_clk = devm_clk_get(&pdev->dev, "ipg");
39 if (IS_ERR(mxc_ipg_clk)) {
40 dev_err(&pdev->dev, "clk_get(\"ipg\") failed\n");
41 return PTR_ERR(mxc_ipg_clk);
42 }
43
44 mxc_ahb_clk = devm_clk_get(&pdev->dev, "ahb");
45 if (IS_ERR(mxc_ahb_clk)) {
46 dev_err(&pdev->dev, "clk_get(\"ahb\") failed\n");
47 return PTR_ERR(mxc_ahb_clk);
48 }
49
50 mxc_per_clk = devm_clk_get(&pdev->dev, "per");
51 if (IS_ERR(mxc_per_clk)) {
52 dev_err(&pdev->dev, "clk_get(\"per\") failed\n");
53 return PTR_ERR(mxc_per_clk);
54 }
55
56 clk_prepare_enable(mxc_ipg_clk);
57 clk_prepare_enable(mxc_ahb_clk);
58 clk_prepare_enable(mxc_per_clk);
59
60 /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
61 if (!strcmp(pdev->id_entry->name, "imx-udc-mx27")) {
62 freq = clk_get_rate(mxc_per_clk);
63 if (pdata->phy_mode != FSL_USB2_PHY_ULPI &&
64 (freq < 59999000 || freq > 60001000)) {
65 dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq);
66 ret = -EINVAL;
67 goto eclkrate;
68 }
69 }
70
71 return 0;
72
73eclkrate:
74 clk_disable_unprepare(mxc_ipg_clk);
75 clk_disable_unprepare(mxc_ahb_clk);
76 clk_disable_unprepare(mxc_per_clk);
77 mxc_per_clk = NULL;
78 return ret;
79}
80
81int fsl_udc_clk_finalize(struct platform_device *pdev)
82{
83 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
84 int ret = 0;
85
86 /* workaround ENGcm09152 for i.MX35 */
87 if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) {
88 unsigned int v;
89 struct resource *res = platform_get_resource
90 (pdev, IORESOURCE_MEM, 0);
91 void __iomem *phy_regs = ioremap(res->start +
92 MX35_USBPHYCTRL_OFFSET, 512);
93 if (!phy_regs) {
94 dev_err(&pdev->dev, "ioremap for phy address fails\n");
95 ret = -EINVAL;
96 goto ioremap_err;
97 }
98
99 v = readl(phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
100 writel(v | USBPHYCTRL_EVDO,
101 phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
102
103 iounmap(phy_regs);
104 }
105
106
107ioremap_err:
108 /* ULPI transceivers don't need usbpll */
109 if (pdata->phy_mode == FSL_USB2_PHY_ULPI) {
110 clk_disable_unprepare(mxc_per_clk);
111 mxc_per_clk = NULL;
112 }
113
114 return ret;
115}
116
117void fsl_udc_clk_release(void)
118{
119 if (mxc_per_clk)
120 clk_disable_unprepare(mxc_per_clk);
121 clk_disable_unprepare(mxc_ahb_clk);
122 clk_disable_unprepare(mxc_ipg_clk);
123}