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1/*
2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
3 * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
4 * AT91SAM9X25, AT91SAM9X35 SoC
5 *
6 * Copyright (C) 2012 Atmel,
7 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 model = "Atmel AT91SAM9x5 family SoC";
16 compatible = "atmel,at91sam9x5";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 gpio0 = &pioA;
25 gpio1 = &pioB;
26 gpio2 = &pioC;
27 gpio3 = &pioD;
28 tcb0 = &tcb0;
29 tcb1 = &tcb1;
30 i2c0 = &i2c0;
31 i2c1 = &i2c1;
32 i2c2 = &i2c2;
33 ssc0 = &ssc0;
34 };
35 cpus {
36 cpu@0 {
37 compatible = "arm,arm926ejs";
38 };
39 };
40
41 memory {
42 reg = <0x20000000 0x10000000>;
43 };
44
45 ahb {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 ranges;
50
51 apb {
52 compatible = "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 aic: interrupt-controller@fffff000 {
58 #interrupt-cells = <3>;
59 compatible = "atmel,at91rm9200-aic";
60 interrupt-controller;
61 reg = <0xfffff000 0x200>;
62 atmel,external-irqs = <31>;
63 };
64
65 ramc0: ramc@ffffe800 {
66 compatible = "atmel,at91sam9g45-ddramc";
67 reg = <0xffffe800 0x200>;
68 };
69
70 pmc: pmc@fffffc00 {
71 compatible = "atmel,at91rm9200-pmc";
72 reg = <0xfffffc00 0x100>;
73 };
74
75 rstc@fffffe00 {
76 compatible = "atmel,at91sam9g45-rstc";
77 reg = <0xfffffe00 0x10>;
78 };
79
80 shdwc@fffffe10 {
81 compatible = "atmel,at91sam9x5-shdwc";
82 reg = <0xfffffe10 0x10>;
83 };
84
85 pit: timer@fffffe30 {
86 compatible = "atmel,at91sam9260-pit";
87 reg = <0xfffffe30 0xf>;
88 interrupts = <1 4 7>;
89 };
90
91 tcb0: timer@f8008000 {
92 compatible = "atmel,at91sam9x5-tcb";
93 reg = <0xf8008000 0x100>;
94 interrupts = <17 4 0>;
95 };
96
97 tcb1: timer@f800c000 {
98 compatible = "atmel,at91sam9x5-tcb";
99 reg = <0xf800c000 0x100>;
100 interrupts = <17 4 0>;
101 };
102
103 dma0: dma-controller@ffffec00 {
104 compatible = "atmel,at91sam9g45-dma";
105 reg = <0xffffec00 0x200>;
106 interrupts = <20 4 0>;
107 };
108
109 dma1: dma-controller@ffffee00 {
110 compatible = "atmel,at91sam9g45-dma";
111 reg = <0xffffee00 0x200>;
112 interrupts = <21 4 0>;
113 };
114
115 pinctrl@fffff400 {
116 #address-cells = <1>;
117 #size-cells = <1>;
118 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
119 ranges = <0xfffff400 0xfffff400 0x800>;
120
121 /* shared pinctrl settings */
122 dbgu {
123 pinctrl_dbgu: dbgu-0 {
124 atmel,pins =
125 <0 9 0x1 0x0 /* PA9 periph A */
126 0 10 0x1 0x1>; /* PA10 periph A with pullup */
127 };
128 };
129
130 usart0 {
131 pinctrl_usart0: usart0-0 {
132 atmel,pins =
133 <0 0 0x1 0x1 /* PA0 periph A with pullup */
134 0 1 0x1 0x0>; /* PA1 periph A */
135 };
136
137 pinctrl_usart0_rts: usart0_rts-0 {
138 atmel,pins =
139 <0 2 0x1 0x0>; /* PA2 periph A */
140 };
141
142 pinctrl_usart0_cts: usart0_cts-0 {
143 atmel,pins =
144 <0 3 0x1 0x0>; /* PA3 periph A */
145 };
146 };
147
148 usart1 {
149 pinctrl_usart1: usart1-0 {
150 atmel,pins =
151 <0 5 0x1 0x1 /* PA5 periph A with pullup */
152 0 6 0x1 0x0>; /* PA6 periph A */
153 };
154
155 pinctrl_usart1_rts: usart1_rts-0 {
156 atmel,pins =
157 <3 27 0x3 0x0>; /* PC27 periph C */
158 };
159
160 pinctrl_usart1_cts: usart1_cts-0 {
161 atmel,pins =
162 <3 28 0x3 0x0>; /* PC28 periph C */
163 };
164 };
165
166 usart2 {
167 pinctrl_usart2: usart2-0 {
168 atmel,pins =
169 <0 7 0x1 0x1 /* PA7 periph A with pullup */
170 0 8 0x1 0x0>; /* PA8 periph A */
171 };
172
173 pinctrl_uart2_rts: uart2_rts-0 {
174 atmel,pins =
175 <0 0 0x2 0x0>; /* PB0 periph B */
176 };
177
178 pinctrl_uart2_cts: uart2_cts-0 {
179 atmel,pins =
180 <0 1 0x2 0x0>; /* PB1 periph B */
181 };
182 };
183
184 usart3 {
185 pinctrl_uart3: usart3-0 {
186 atmel,pins =
187 <3 23 0x2 0x1 /* PC22 periph B with pullup */
188 3 23 0x2 0x0>; /* PC23 periph B */
189 };
190
191 pinctrl_usart3_rts: usart3_rts-0 {
192 atmel,pins =
193 <3 24 0x2 0x0>; /* PC24 periph B */
194 };
195
196 pinctrl_usart3_cts: usart3_cts-0 {
197 atmel,pins =
198 <3 25 0x2 0x0>; /* PC25 periph B */
199 };
200 };
201
202 uart0 {
203 pinctrl_uart0: uart0-0 {
204 atmel,pins =
205 <3 8 0x3 0x0 /* PC8 periph C */
206 3 9 0x3 0x1>; /* PC9 periph C with pullup */
207 };
208 };
209
210 uart1 {
211 pinctrl_uart1: uart1-0 {
212 atmel,pins =
213 <3 16 0x3 0x0 /* PC16 periph C */
214 3 17 0x3 0x1>; /* PC17 periph C with pullup */
215 };
216 };
217
218 nand {
219 pinctrl_nand: nand-0 {
220 atmel,pins =
221 <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
222 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
223 };
224 };
225
226 macb0 {
227 pinctrl_macb0_rmii: macb0_rmii-0 {
228 atmel,pins =
229 <1 0 0x1 0x0 /* PB0 periph A */
230 1 1 0x1 0x0 /* PB1 periph A */
231 1 2 0x1 0x0 /* PB2 periph A */
232 1 3 0x1 0x0 /* PB3 periph A */
233 1 4 0x1 0x0 /* PB4 periph A */
234 1 5 0x1 0x0 /* PB5 periph A */
235 1 6 0x1 0x0 /* PB6 periph A */
236 1 7 0x1 0x0 /* PB7 periph A */
237 1 9 0x1 0x0 /* PB9 periph A */
238 1 10 0x1 0x0>; /* PB10 periph A */
239 };
240
241 pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
242 atmel,pins =
243 <1 8 0x1 0x0 /* PA8 periph A */
244 1 11 0x1 0x0 /* PA11 periph A */
245 1 12 0x1 0x0 /* PA12 periph A */
246 1 13 0x1 0x0 /* PA13 periph A */
247 1 14 0x1 0x0 /* PA14 periph A */
248 1 15 0x1 0x0 /* PA15 periph A */
249 1 16 0x1 0x0 /* PA16 periph A */
250 1 17 0x1 0x0>; /* PA17 periph A */
251 };
252 };
253
254 mmc0 {
255 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
256 atmel,pins =
257 <0 17 0x1 0x0 /* PA17 periph A */
258 0 16 0x1 0x1 /* PA16 periph A with pullup */
259 0 15 0x1 0x1>; /* PA15 periph A with pullup */
260 };
261
262 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
263 atmel,pins =
264 <0 18 0x1 0x1 /* PA18 periph A with pullup */
265 0 19 0x1 0x1 /* PA19 periph A with pullup */
266 0 20 0x1 0x1>; /* PA20 periph A with pullup */
267 };
268 };
269
270 mmc1 {
271 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
272 atmel,pins =
273 <0 13 0x2 0x0 /* PA13 periph B */
274 0 12 0x2 0x1 /* PA12 periph B with pullup */
275 0 11 0x2 0x1>; /* PA11 periph B with pullup */
276 };
277
278 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
279 atmel,pins =
280 <0 2 0x2 0x1 /* PA2 periph B with pullup */
281 0 3 0x2 0x1 /* PA3 periph B with pullup */
282 0 4 0x2 0x1>; /* PA4 periph B with pullup */
283 };
284 };
285
286 ssc0 {
287 pinctrl_ssc0_tx: ssc0_tx-0 {
288 atmel,pins =
289 <0 24 0x2 0x0 /* PA24 periph B */
290 0 25 0x2 0x0 /* PA25 periph B */
291 0 26 0x2 0x0>; /* PA26 periph B */
292 };
293
294 pinctrl_ssc0_rx: ssc0_rx-0 {
295 atmel,pins =
296 <0 27 0x2 0x0 /* PA27 periph B */
297 0 28 0x2 0x0 /* PA28 periph B */
298 0 29 0x2 0x0>; /* PA29 periph B */
299 };
300 };
301
302 pioA: gpio@fffff400 {
303 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
304 reg = <0xfffff400 0x200>;
305 interrupts = <2 4 1>;
306 #gpio-cells = <2>;
307 gpio-controller;
308 interrupt-controller;
309 #interrupt-cells = <2>;
310 };
311
312 pioB: gpio@fffff600 {
313 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
314 reg = <0xfffff600 0x200>;
315 interrupts = <2 4 1>;
316 #gpio-cells = <2>;
317 gpio-controller;
318 #gpio-lines = <19>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
321 };
322
323 pioC: gpio@fffff800 {
324 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
325 reg = <0xfffff800 0x200>;
326 interrupts = <3 4 1>;
327 #gpio-cells = <2>;
328 gpio-controller;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 };
332
333 pioD: gpio@fffffa00 {
334 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
335 reg = <0xfffffa00 0x200>;
336 interrupts = <3 4 1>;
337 #gpio-cells = <2>;
338 gpio-controller;
339 #gpio-lines = <22>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 };
343 };
344
345 ssc0: ssc@f0010000 {
346 compatible = "atmel,at91sam9g45-ssc";
347 reg = <0xf0010000 0x4000>;
348 interrupts = <28 4 5>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
351 status = "disabled";
352 };
353
354 mmc0: mmc@f0008000 {
355 compatible = "atmel,hsmci";
356 reg = <0xf0008000 0x600>;
357 interrupts = <12 4 0>;
358 #address-cells = <1>;
359 #size-cells = <0>;
360 status = "disabled";
361 };
362
363 mmc1: mmc@f000c000 {
364 compatible = "atmel,hsmci";
365 reg = <0xf000c000 0x600>;
366 interrupts = <26 4 0>;
367 #address-cells = <1>;
368 #size-cells = <0>;
369 status = "disabled";
370 };
371
372 dbgu: serial@fffff200 {
373 compatible = "atmel,at91sam9260-usart";
374 reg = <0xfffff200 0x200>;
375 interrupts = <1 4 7>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_dbgu>;
378 status = "disabled";
379 };
380
381 usart0: serial@f801c000 {
382 compatible = "atmel,at91sam9260-usart";
383 reg = <0xf801c000 0x200>;
384 interrupts = <5 4 5>;
385 atmel,use-dma-rx;
386 atmel,use-dma-tx;
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_usart0>;
389 status = "disabled";
390 };
391
392 usart1: serial@f8020000 {
393 compatible = "atmel,at91sam9260-usart";
394 reg = <0xf8020000 0x200>;
395 interrupts = <6 4 5>;
396 atmel,use-dma-rx;
397 atmel,use-dma-tx;
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_usart1>;
400 status = "disabled";
401 };
402
403 usart2: serial@f8024000 {
404 compatible = "atmel,at91sam9260-usart";
405 reg = <0xf8024000 0x200>;
406 interrupts = <7 4 5>;
407 atmel,use-dma-rx;
408 atmel,use-dma-tx;
409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_usart2>;
411 status = "disabled";
412 };
413
414 macb0: ethernet@f802c000 {
415 compatible = "cdns,at32ap7000-macb", "cdns,macb";
416 reg = <0xf802c000 0x100>;
417 interrupts = <24 4 3>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_macb0_rmii>;
420 status = "disabled";
421 };
422
423 macb1: ethernet@f8030000 {
424 compatible = "cdns,at32ap7000-macb", "cdns,macb";
425 reg = <0xf8030000 0x100>;
426 interrupts = <27 4 3>;
427 status = "disabled";
428 };
429
430 i2c0: i2c@f8010000 {
431 compatible = "atmel,at91sam9x5-i2c";
432 reg = <0xf8010000 0x100>;
433 interrupts = <9 4 6>;
434 #address-cells = <1>;
435 #size-cells = <0>;
436 status = "disabled";
437 };
438
439 i2c1: i2c@f8014000 {
440 compatible = "atmel,at91sam9x5-i2c";
441 reg = <0xf8014000 0x100>;
442 interrupts = <10 4 6>;
443 #address-cells = <1>;
444 #size-cells = <0>;
445 status = "disabled";
446 };
447
448 i2c2: i2c@f8018000 {
449 compatible = "atmel,at91sam9x5-i2c";
450 reg = <0xf8018000 0x100>;
451 interrupts = <11 4 6>;
452 #address-cells = <1>;
453 #size-cells = <0>;
454 status = "disabled";
455 };
456
457 adc0: adc@f804c000 {
458 compatible = "atmel,at91sam9260-adc";
459 reg = <0xf804c000 0x100>;
460 interrupts = <19 4 0>;
461 atmel,adc-use-external;
462 atmel,adc-channels-used = <0xffff>;
463 atmel,adc-vref = <3300>;
464 atmel,adc-num-channels = <12>;
465 atmel,adc-startup-time = <40>;
466 atmel,adc-channel-base = <0x50>;
467 atmel,adc-drdy-mask = <0x1000000>;
468 atmel,adc-status-register = <0x30>;
469 atmel,adc-trigger-register = <0xc0>;
470
471 trigger@0 {
472 trigger-name = "external-rising";
473 trigger-value = <0x1>;
474 trigger-external;
475 };
476
477 trigger@1 {
478 trigger-name = "external-falling";
479 trigger-value = <0x2>;
480 trigger-external;
481 };
482
483 trigger@2 {
484 trigger-name = "external-any";
485 trigger-value = <0x3>;
486 trigger-external;
487 };
488
489 trigger@3 {
490 trigger-name = "continuous";
491 trigger-value = <0x6>;
492 };
493 };
494 };
495
496 nand0: nand@40000000 {
497 compatible = "atmel,at91rm9200-nand";
498 #address-cells = <1>;
499 #size-cells = <1>;
500 reg = <0x40000000 0x10000000
501 >;
502 atmel,nand-addr-offset = <21>;
503 atmel,nand-cmd-offset = <22>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_nand>;
506 gpios = <&pioD 5 0
507 &pioD 4 0
508 0
509 >;
510 status = "disabled";
511 };
512
513 usb0: ohci@00600000 {
514 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
515 reg = <0x00600000 0x100000>;
516 interrupts = <22 4 2>;
517 status = "disabled";
518 };
519
520 usb1: ehci@00700000 {
521 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
522 reg = <0x00700000 0x100000>;
523 interrupts = <22 4 2>;
524 status = "disabled";
525 };
526 };
527
528 i2c@0 {
529 compatible = "i2c-gpio";
530 gpios = <&pioA 30 0 /* sda */
531 &pioA 31 0 /* scl */
532 >;
533 i2c-gpio,sda-open-drain;
534 i2c-gpio,scl-open-drain;
535 i2c-gpio,delay-us = <2>; /* ~100 kHz */
536 #address-cells = <1>;
537 #size-cells = <0>;
538 status = "disabled";
539 };
540
541 i2c@1 {
542 compatible = "i2c-gpio";
543 gpios = <&pioC 0 0 /* sda */
544 &pioC 1 0 /* scl */
545 >;
546 i2c-gpio,sda-open-drain;
547 i2c-gpio,scl-open-drain;
548 i2c-gpio,delay-us = <2>; /* ~100 kHz */
549 #address-cells = <1>;
550 #size-cells = <0>;
551 status = "disabled";
552 };
553
554 i2c@2 {
555 compatible = "i2c-gpio";
556 gpios = <&pioB 4 0 /* sda */
557 &pioB 5 0 /* scl */
558 >;
559 i2c-gpio,sda-open-drain;
560 i2c-gpio,scl-open-drain;
561 i2c-gpio,delay-us = <2>; /* ~100 kHz */
562 #address-cells = <1>;
563 #size-cells = <0>;
564 status = "disabled";
565 };
566};