tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * provides masks and opcode images for use by code generation, emulation
10 * and for instructions that older assemblers might not know about
11 */
12#ifndef _ASM_POWERPC_PPC_OPCODE_H
13#define _ASM_POWERPC_PPC_OPCODE_H
14
15#include <linux/stringify.h>
16#include <asm/asm-compat.h>
17
18#define __REG_R0 0
19#define __REG_R1 1
20#define __REG_R2 2
21#define __REG_R3 3
22#define __REG_R4 4
23#define __REG_R5 5
24#define __REG_R6 6
25#define __REG_R7 7
26#define __REG_R8 8
27#define __REG_R9 9
28#define __REG_R10 10
29#define __REG_R11 11
30#define __REG_R12 12
31#define __REG_R13 13
32#define __REG_R14 14
33#define __REG_R15 15
34#define __REG_R16 16
35#define __REG_R17 17
36#define __REG_R18 18
37#define __REG_R19 19
38#define __REG_R20 20
39#define __REG_R21 21
40#define __REG_R22 22
41#define __REG_R23 23
42#define __REG_R24 24
43#define __REG_R25 25
44#define __REG_R26 26
45#define __REG_R27 27
46#define __REG_R28 28
47#define __REG_R29 29
48#define __REG_R30 30
49#define __REG_R31 31
50
51#define __REGA0_0 0
52#define __REGA0_R1 1
53#define __REGA0_R2 2
54#define __REGA0_R3 3
55#define __REGA0_R4 4
56#define __REGA0_R5 5
57#define __REGA0_R6 6
58#define __REGA0_R7 7
59#define __REGA0_R8 8
60#define __REGA0_R9 9
61#define __REGA0_R10 10
62#define __REGA0_R11 11
63#define __REGA0_R12 12
64#define __REGA0_R13 13
65#define __REGA0_R14 14
66#define __REGA0_R15 15
67#define __REGA0_R16 16
68#define __REGA0_R17 17
69#define __REGA0_R18 18
70#define __REGA0_R19 19
71#define __REGA0_R20 20
72#define __REGA0_R21 21
73#define __REGA0_R22 22
74#define __REGA0_R23 23
75#define __REGA0_R24 24
76#define __REGA0_R25 25
77#define __REGA0_R26 26
78#define __REGA0_R27 27
79#define __REGA0_R28 28
80#define __REGA0_R29 29
81#define __REGA0_R30 30
82#define __REGA0_R31 31
83
84/* sorted alphabetically */
85#define PPC_INST_DCBA 0x7c0005ec
86#define PPC_INST_DCBA_MASK 0xfc0007fe
87#define PPC_INST_DCBAL 0x7c2005ec
88#define PPC_INST_DCBZL 0x7c2007ec
89#define PPC_INST_ICBT 0x7c00002c
90#define PPC_INST_ISEL 0x7c00001e
91#define PPC_INST_ISEL_MASK 0xfc00003e
92#define PPC_INST_LDARX 0x7c0000a8
93#define PPC_INST_LSWI 0x7c0004aa
94#define PPC_INST_LSWX 0x7c00042a
95#define PPC_INST_LWARX 0x7c000028
96#define PPC_INST_LWSYNC 0x7c2004ac
97#define PPC_INST_LXVD2X 0x7c000698
98#define PPC_INST_MCRXR 0x7c000400
99#define PPC_INST_MCRXR_MASK 0xfc0007fe
100#define PPC_INST_MFSPR_PVR 0x7c1f42a6
101#define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff
102#define PPC_INST_MSGSND 0x7c00019c
103#define PPC_INST_NOP 0x60000000
104#define PPC_INST_POPCNTB 0x7c0000f4
105#define PPC_INST_POPCNTB_MASK 0xfc0007fe
106#define PPC_INST_POPCNTD 0x7c0003f4
107#define PPC_INST_POPCNTW 0x7c0002f4
108#define PPC_INST_RFCI 0x4c000066
109#define PPC_INST_RFDI 0x4c00004e
110#define PPC_INST_RFMCI 0x4c00004c
111#define PPC_INST_MFSPR_DSCR 0x7c1102a6
112#define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff
113#define PPC_INST_MTSPR_DSCR 0x7c1103a6
114#define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff
115#define PPC_INST_SLBFEE 0x7c0007a7
116
117#define PPC_INST_STRING 0x7c00042a
118#define PPC_INST_STRING_MASK 0xfc0007fe
119#define PPC_INST_STRING_GEN_MASK 0xfc00067e
120
121#define PPC_INST_STSWI 0x7c0005aa
122#define PPC_INST_STSWX 0x7c00052a
123#define PPC_INST_STXVD2X 0x7c000798
124#define PPC_INST_TLBIE 0x7c000264
125#define PPC_INST_TLBILX 0x7c000024
126#define PPC_INST_WAIT 0x7c00007c
127#define PPC_INST_TLBIVAX 0x7c000624
128#define PPC_INST_TLBSRX_DOT 0x7c0006a5
129#define PPC_INST_XXLOR 0xf0000510
130#define PPC_INST_XVCPSGNDP 0xf0000780
131
132#define PPC_INST_NAP 0x4c000364
133#define PPC_INST_SLEEP 0x4c0003a4
134
135/* A2 specific instructions */
136#define PPC_INST_ERATWE 0x7c0001a6
137#define PPC_INST_ERATRE 0x7c000166
138#define PPC_INST_ERATILX 0x7c000066
139#define PPC_INST_ERATIVAX 0x7c000666
140#define PPC_INST_ERATSX 0x7c000126
141#define PPC_INST_ERATSX_DOT 0x7c000127
142
143/* Misc instructions for BPF compiler */
144#define PPC_INST_LD 0xe8000000
145#define PPC_INST_LHZ 0xa0000000
146#define PPC_INST_LWZ 0x80000000
147#define PPC_INST_STD 0xf8000000
148#define PPC_INST_STDU 0xf8000001
149#define PPC_INST_MFLR 0x7c0802a6
150#define PPC_INST_MTLR 0x7c0803a6
151#define PPC_INST_CMPWI 0x2c000000
152#define PPC_INST_CMPDI 0x2c200000
153#define PPC_INST_CMPLW 0x7c000040
154#define PPC_INST_CMPLWI 0x28000000
155#define PPC_INST_ADDI 0x38000000
156#define PPC_INST_ADDIS 0x3c000000
157#define PPC_INST_ADD 0x7c000214
158#define PPC_INST_SUB 0x7c000050
159#define PPC_INST_BLR 0x4e800020
160#define PPC_INST_BLRL 0x4e800021
161#define PPC_INST_MULLW 0x7c0001d6
162#define PPC_INST_MULHWU 0x7c000016
163#define PPC_INST_MULLI 0x1c000000
164#define PPC_INST_DIVWU 0x7c0003d6
165#define PPC_INST_RLWINM 0x54000000
166#define PPC_INST_RLDICR 0x78000004
167#define PPC_INST_SLW 0x7c000030
168#define PPC_INST_SRW 0x7c000430
169#define PPC_INST_AND 0x7c000038
170#define PPC_INST_ANDDOT 0x7c000039
171#define PPC_INST_OR 0x7c000378
172#define PPC_INST_XOR 0x7c000278
173#define PPC_INST_ANDI 0x70000000
174#define PPC_INST_ORI 0x60000000
175#define PPC_INST_ORIS 0x64000000
176#define PPC_INST_XORI 0x68000000
177#define PPC_INST_XORIS 0x6c000000
178#define PPC_INST_NEG 0x7c0000d0
179#define PPC_INST_BRANCH 0x48000000
180#define PPC_INST_BRANCH_COND 0x40800000
181#define PPC_INST_LBZCIX 0x7c0006aa
182#define PPC_INST_STBCIX 0x7c0007aa
183
184/* macros to insert fields into opcodes */
185#define ___PPC_RA(a) (((a) & 0x1f) << 16)
186#define ___PPC_RB(b) (((b) & 0x1f) << 11)
187#define ___PPC_RS(s) (((s) & 0x1f) << 21)
188#define ___PPC_RT(t) ___PPC_RS(t)
189#define __PPC_RA(a) ___PPC_RA(__REG_##a)
190#define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
191#define __PPC_RB(b) ___PPC_RB(__REG_##b)
192#define __PPC_RS(s) ___PPC_RS(__REG_##s)
193#define __PPC_RT(t) ___PPC_RT(__REG_##t)
194#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
195#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
196#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
197#define __PPC_XT(s) __PPC_XS(s)
198#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
199#define __PPC_WC(w) (((w) & 0x3) << 21)
200#define __PPC_WS(w) (((w) & 0x1f) << 11)
201#define __PPC_SH(s) __PPC_WS(s)
202#define __PPC_MB(s) (((s) & 0x1f) << 6)
203#define __PPC_ME(s) (((s) & 0x1f) << 1)
204#define __PPC_BI(s) (((s) & 0x1f) << 16)
205#define __PPC_CT(t) (((t) & 0x0f) << 21)
206
207/*
208 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
209 * larx with EH set as an illegal instruction.
210 */
211#ifdef CONFIG_PPC64
212#define __PPC_EH(eh) (((eh) & 0x1) << 0)
213#else
214#define __PPC_EH(eh) 0
215#endif
216
217/* Deal with instructions that older assemblers aren't aware of */
218#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \
219 __PPC_RA(a) | __PPC_RB(b))
220#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \
221 __PPC_RA(a) | __PPC_RB(b))
222#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \
223 ___PPC_RT(t) | ___PPC_RA(a) | \
224 ___PPC_RB(b) | __PPC_EH(eh))
225#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \
226 ___PPC_RT(t) | ___PPC_RA(a) | \
227 ___PPC_RB(b) | __PPC_EH(eh))
228#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
229 ___PPC_RB(b))
230#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \
231 __PPC_RA(a) | __PPC_RS(s))
232#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \
233 __PPC_RA(a) | __PPC_RS(s))
234#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \
235 __PPC_RA(a) | __PPC_RS(s))
236#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI)
237#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
238#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
239#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
240 __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
241#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
242#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
243#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
244#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
245 __PPC_WC(w))
246#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
247 ___PPC_RB(a) | ___PPC_RS(lp))
248#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
249 __PPC_RA0(a) | __PPC_RB(b))
250#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
251 __PPC_RA0(a) | __PPC_RB(b))
252
253#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \
254 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
255#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \
256 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
257#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \
258 __PPC_T_TLB(t) | __PPC_RA0(a) | \
259 __PPC_RB(b))
260#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \
261 __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
262#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \
263 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
264#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
265 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
266#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \
267 __PPC_RT(t) | __PPC_RB(b))
268#define PPC_ICBT(c,a,b) stringify_in_c(.long PPC_INST_ICBT | \
269 __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
270/* PASemi instructions */
271#define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \
272 __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
273#define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \
274 __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
275
276/*
277 * Define what the VSX XX1 form instructions will look like, then add
278 * the 128 bit load store instructions based on that.
279 */
280#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
281#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
282#define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \
283 VSX_XX1((s), a, b))
284#define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \
285 VSX_XX1((s), a, b))
286#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \
287 VSX_XX3((t), a, b))
288#define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
289 VSX_XX3((t), (a), (b))))
290
291#define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
292#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
293
294#endif /* _ASM_POWERPC_PPC_OPCODE_H */